Merge branch 'next' of git://git.denx.de/u-boot-blackfin
[platform/kernel/u-boot.git] / arch / powerpc / include / asm / fsl_law.h
1 /*
2  * Copyright 2008-2011 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * Version 2 as published by the Free Software Foundation.
7  */
8
9 #ifndef _FSL_LAW_H_
10 #define _FSL_LAW_H_
11
12 #include <asm/io.h>
13 #include <linux/log2.h>
14
15 #define LAW_EN  0x80000000
16
17 #define SET_LAW_ENTRY(idx, a, sz, trgt) \
18         { .index = idx, .addr = a, .size = sz, .trgt_id = trgt }
19
20 #define SET_LAW(a, sz, trgt) \
21         { .index = -1, .addr = a, .size = sz, .trgt_id = trgt }
22
23 enum law_size {
24         LAW_SIZE_4K = 0xb,
25         LAW_SIZE_8K,
26         LAW_SIZE_16K,
27         LAW_SIZE_32K,
28         LAW_SIZE_64K,
29         LAW_SIZE_128K,
30         LAW_SIZE_256K,
31         LAW_SIZE_512K,
32         LAW_SIZE_1M,
33         LAW_SIZE_2M,
34         LAW_SIZE_4M,
35         LAW_SIZE_8M,
36         LAW_SIZE_16M,
37         LAW_SIZE_32M,
38         LAW_SIZE_64M,
39         LAW_SIZE_128M,
40         LAW_SIZE_256M,
41         LAW_SIZE_512M,
42         LAW_SIZE_1G,
43         LAW_SIZE_2G,
44         LAW_SIZE_4G,
45         LAW_SIZE_8G,
46         LAW_SIZE_16G,
47         LAW_SIZE_32G,
48 };
49
50 #define law_size_bits(sz)       (__ilog2_u64(sz) - 1)
51 #define lawar_size(x)   (1ULL << ((x & 0x3f) + 1))
52
53 #ifdef CONFIG_FSL_CORENET
54 enum law_trgt_if {
55         LAW_TRGT_IF_PCIE_1 = 0x00,
56         LAW_TRGT_IF_PCIE_2 = 0x01,
57         LAW_TRGT_IF_PCIE_3 = 0x02,
58         LAW_TRGT_IF_PCIE_4 = 0x03,
59         LAW_TRGT_IF_RIO_1 = 0x08,
60         LAW_TRGT_IF_RIO_2 = 0x09,
61
62         LAW_TRGT_IF_DDR_1 = 0x10,
63         LAW_TRGT_IF_DDR_2 = 0x11,       /* 2nd controller */
64         LAW_TRGT_IF_DDR_3 = 0x12,
65         LAW_TRGT_IF_DDR_4 = 0x13,
66         LAW_TRGT_IF_DDR_INTRLV = 0x14,
67         LAW_TRGT_IF_DDR_INTLV_34 = 0x15,
68         LAW_TRGT_IF_DDR_INTLV_123 = 0x17,
69         LAW_TRGT_IF_DDR_INTLV_1234 = 0x16,
70         LAW_TRGT_IF_BMAN = 0x18,
71         LAW_TRGT_IF_DCSR = 0x1d,
72         LAW_TRGT_IF_CCSR = 0x1e,
73         LAW_TRGT_IF_LBC = 0x1f,
74         LAW_TRGT_IF_QMAN = 0x3c,
75
76         LAW_TRGT_IF_MAPLE = 0x50,
77 };
78 #define LAW_TRGT_IF_DDR         LAW_TRGT_IF_DDR_1
79 #define LAW_TRGT_IF_IFC         LAW_TRGT_IF_LBC
80 #else
81 enum law_trgt_if {
82         LAW_TRGT_IF_PCI = 0x00,
83         LAW_TRGT_IF_PCI_2 = 0x01,
84 #ifndef CONFIG_MPC8641
85         LAW_TRGT_IF_PCIE_1 = 0x02,
86 #endif
87 #if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
88         LAW_TRGT_IF_OCN_DSP = 0x03,
89 #else
90 #if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020)
91         LAW_TRGT_IF_PCIE_3 = 0x03,
92 #endif
93 #endif
94         LAW_TRGT_IF_LBC = 0x04,
95         LAW_TRGT_IF_CCSR = 0x08,
96         LAW_TRGT_IF_DSP_CCSR = 0x09,
97         LAW_TRGT_IF_PLATFORM_SRAM = 0x0a,
98         LAW_TRGT_IF_DDR_INTRLV = 0x0b,
99         LAW_TRGT_IF_RIO = 0x0c,
100 #if defined(CONFIG_BSC9132)
101         LAW_TRGT_IF_CLASS_DSP = 0x0d,
102 #else
103         LAW_TRGT_IF_RIO_2 = 0x0d,
104 #endif
105         LAW_TRGT_IF_DPAA_SWP_SRAM = 0x0e,
106         LAW_TRGT_IF_DDR = 0x0f,
107         LAW_TRGT_IF_DDR_2 = 0x16,       /* 2nd controller */
108         /* place holder for 3-way and 4-way interleaving */
109         LAW_TRGT_IF_DDR_3,
110         LAW_TRGT_IF_DDR_4,
111         LAW_TRGT_IF_DDR_INTLV_34,
112         LAW_TRGT_IF_DDR_INTLV_123,
113         LAW_TRGT_IF_DDR_INTLV_1234,
114 };
115 #define LAW_TRGT_IF_DDR_1       LAW_TRGT_IF_DDR
116 #define LAW_TRGT_IF_PCI_1       LAW_TRGT_IF_PCI
117 #define LAW_TRGT_IF_PCIX        LAW_TRGT_IF_PCI
118 #define LAW_TRGT_IF_PCIE_2      LAW_TRGT_IF_PCI_2
119 #define LAW_TRGT_IF_RIO_1       LAW_TRGT_IF_RIO
120 #define LAW_TRGT_IF_IFC         LAW_TRGT_IF_LBC
121
122 #ifdef CONFIG_MPC8641
123 #define LAW_TRGT_IF_PCIE_1      LAW_TRGT_IF_PCI
124 #endif
125
126 #if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
127 #define LAW_TRGT_IF_PCIE_3      LAW_TRGT_IF_PCI
128 #endif
129 #endif /* CONFIG_FSL_CORENET */
130
131 struct law_entry {
132         int index;
133         phys_addr_t addr;
134         enum law_size size;
135         enum law_trgt_if trgt_id;
136 };
137
138 extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
139 extern int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
140 extern int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
141 extern int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id);
142 extern struct law_entry find_law(phys_addr_t addr);
143 extern void disable_law(u8 idx);
144 extern void init_laws(void);
145 extern void print_laws(void);
146
147 /* define in board code */
148 extern struct law_entry law_table[];
149 extern int num_law_entries;
150 #endif