1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
6 #ifndef _ASM_MPC85xx_CONFIG_H_
7 #define _ASM_MPC85xx_CONFIG_H_
9 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
12 * This macro should be removed when we no longer care about backwards
13 * compatibility with older operating systems.
15 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
17 #include <fsl_ddrc_version.h>
20 #define CONFIG_SYS_FSL_IFC_BE
21 #define CONFIG_SYS_FSL_SFP_BE
22 #define CONFIG_SYS_FSL_SEC_MON_BE
24 #if defined(CONFIG_ARCH_MPC8548)
25 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
26 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
27 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
28 #define CONFIG_SYS_FSL_RMU
29 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
31 #elif defined(CONFIG_ARCH_MPC8568)
32 #define QE_MURAM_SIZE 0x10000UL
34 #define QE_NUM_OF_SNUM 28
35 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
36 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
37 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
38 #define CONFIG_SYS_FSL_RMU
39 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
41 #elif defined(CONFIG_ARCH_MPC8569)
42 #define QE_MURAM_SIZE 0x20000UL
44 #define QE_NUM_OF_SNUM 46
45 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
46 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
47 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
48 #define CONFIG_SYS_FSL_RMU
49 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
51 #elif defined(CONFIG_ARCH_P1010)
52 #define CONFIG_FSL_SDHC_V2_3
54 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
55 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
56 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
57 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
58 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
59 #define CONFIG_ESDHC_HC_BLK_ADDR
61 /* P1011 is single core version of P1020 */
62 #elif defined(CONFIG_ARCH_P1011)
64 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
66 #elif defined(CONFIG_ARCH_P1020)
68 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
69 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
72 #elif defined(CONFIG_ARCH_P1021)
74 #define QE_MURAM_SIZE 0x6000UL
76 #define QE_NUM_OF_SNUM 28
77 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
79 #elif defined(CONFIG_ARCH_P1022)
81 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
83 #elif defined(CONFIG_ARCH_P1023)
84 #define CONFIG_SYS_NUM_FMAN 1
85 #define CONFIG_SYS_NUM_FM1_DTSEC 2
86 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
87 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
88 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
89 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
90 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
92 /* P1024 is lower end variant of P1020 */
93 #elif defined(CONFIG_ARCH_P1024)
95 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
97 /* P1025 is lower end variant of P1021 */
98 #elif defined(CONFIG_ARCH_P1025)
99 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
100 #define CONFIG_TSECV2
101 #define QE_MURAM_SIZE 0x6000UL
102 #define MAX_QE_RISC 1
103 #define QE_NUM_OF_SNUM 28
105 #elif defined(CONFIG_ARCH_P2020)
106 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
107 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
108 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
109 #define CONFIG_SYS_FSL_RMU
110 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
111 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
113 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
114 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
115 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
116 #define CONFIG_SYS_NUM_FMAN 1
117 #define CONFIG_SYS_NUM_FM1_DTSEC 5
118 #define CONFIG_SYS_NUM_FM1_10GEC 1
119 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
120 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
121 #define CONFIG_SYS_FSL_TBCLK_DIV 32
122 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
123 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
124 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
125 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
126 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
127 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
128 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
129 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
131 #elif defined(CONFIG_ARCH_P3041)
132 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
133 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
134 #define CONFIG_SYS_NUM_FMAN 1
135 #define CONFIG_SYS_NUM_FM1_DTSEC 5
136 #define CONFIG_SYS_NUM_FM1_10GEC 1
137 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
138 #define CONFIG_SYS_FSL_TBCLK_DIV 32
139 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
140 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
141 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
142 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
143 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
144 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
145 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
146 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
147 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
149 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
150 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
151 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
152 #define CONFIG_SYS_NUM_FMAN 2
153 #define CONFIG_SYS_NUM_FM1_DTSEC 4
154 #define CONFIG_SYS_NUM_FM2_DTSEC 4
155 #define CONFIG_SYS_NUM_FM1_10GEC 1
156 #define CONFIG_SYS_NUM_FM2_10GEC 1
157 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
158 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
159 #define CONFIG_SYS_FSL_TBCLK_DIV 16
160 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
161 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
162 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
163 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
164 #define CONFIG_SYS_FSL_RMU
165 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
166 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
168 #elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */
169 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
170 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
171 #define CONFIG_SYS_NUM_FMAN 1
172 #define CONFIG_SYS_NUM_FM1_DTSEC 5
173 #define CONFIG_SYS_NUM_FM1_10GEC 1
174 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
175 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
176 #define CONFIG_SYS_FSL_TBCLK_DIV 32
177 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
178 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
179 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
180 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
181 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
182 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
183 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
184 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
186 #elif defined(CONFIG_ARCH_P5040)
187 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
188 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
189 #define CONFIG_SYS_NUM_FMAN 2
190 #define CONFIG_SYS_NUM_FM1_DTSEC 5
191 #define CONFIG_SYS_NUM_FM1_10GEC 1
192 #define CONFIG_SYS_NUM_FM2_DTSEC 5
193 #define CONFIG_SYS_NUM_FM2_10GEC 1
194 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
195 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
196 #define CONFIG_SYS_FSL_TBCLK_DIV 16
197 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
198 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
199 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
200 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
201 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
203 #elif defined(CONFIG_ARCH_BSC9131)
204 #define CONFIG_FSL_SDHC_V2_3
205 #define CONFIG_TSECV2
206 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
207 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
208 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
209 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
210 #define CONFIG_NAND_FSL_IFC
211 #define CONFIG_ESDHC_HC_BLK_ADDR
213 #elif defined(CONFIG_ARCH_BSC9132)
214 #define CONFIG_FSL_SDHC_V2_3
215 #define CONFIG_TSECV2
216 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
217 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
218 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
219 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
220 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
221 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
222 #define CONFIG_NAND_FSL_IFC
223 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
224 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
225 #define CONFIG_ESDHC_HC_BLK_ADDR
227 #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
228 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
229 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
230 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
231 #ifdef CONFIG_ARCH_T4240
232 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
233 #define CONFIG_SYS_NUM_FM1_DTSEC 8
234 #define CONFIG_SYS_NUM_FM1_10GEC 2
235 #define CONFIG_SYS_NUM_FM2_DTSEC 8
236 #define CONFIG_SYS_NUM_FM2_10GEC 2
238 #define CONFIG_SYS_NUM_FM1_DTSEC 6
239 #define CONFIG_SYS_NUM_FM1_10GEC 1
240 #define CONFIG_SYS_NUM_FM2_DTSEC 8
241 #define CONFIG_SYS_NUM_FM2_10GEC 1
242 #if defined(CONFIG_ARCH_T4160)
243 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
246 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
247 #define CONFIG_SYS_FSL_SRDS_1
248 #define CONFIG_SYS_FSL_SRDS_2
249 #define CONFIG_SYS_FSL_SRDS_3
250 #define CONFIG_SYS_FSL_SRDS_4
251 #define CONFIG_SYS_NUM_FMAN 2
252 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
253 #define CONFIG_SYS_PME_CLK 0
254 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
255 #define CONFIG_SYS_FMAN_V3
256 #define CONFIG_SYS_FM1_CLK 3
257 #define CONFIG_SYS_FM2_CLK 3
258 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
259 #define CONFIG_SYS_FSL_TBCLK_DIV 16
260 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
261 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
262 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
263 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
264 #define CONFIG_SYS_FSL_SRIO_LIODN
265 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
266 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
267 #define CONFIG_SYS_FSL_SFP_VER_3_0
268 #define CONFIG_SYS_FSL_PCI_VER_3_X
270 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
271 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
272 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
273 #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
274 #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
275 #define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/
276 #define CONFIG_SYS_FSL_SRDS_1
277 #define CONFIG_SYS_FSL_SRDS_2
278 #define CONFIG_SYS_MAPLE
279 #define CONFIG_SYS_CPRI
280 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
281 #define CONFIG_SYS_NUM_FMAN 1
282 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
283 #define CONFIG_SYS_FM1_CLK 0
284 #define CONFIG_SYS_CPRI_CLK 3
285 #define CONFIG_SYS_ULB_CLK 4
286 #define CONFIG_SYS_ETVPE_CLK 1
287 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
288 #define CONFIG_SYS_FMAN_V3
289 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
290 #define CONFIG_SYS_FSL_TBCLK_DIV 16
291 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
292 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
293 #define CONFIG_SYS_FSL_SFP_VER_3_0
295 #ifdef CONFIG_ARCH_B4860
296 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
297 #define CONFIG_MAX_DSP_CPUS 12
298 #define CONFIG_NUM_DSP_CPUS 6
299 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
300 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
301 #define CONFIG_SYS_NUM_FM1_DTSEC 6
302 #define CONFIG_SYS_NUM_FM1_10GEC 2
303 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
304 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
305 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
306 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
307 #define CONFIG_SYS_FSL_SRIO_LIODN
309 #define CONFIG_MAX_DSP_CPUS 2
310 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
311 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
312 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
313 #define CONFIG_SYS_NUM_FM1_DTSEC 4
314 #define CONFIG_SYS_NUM_FM1_10GEC 0
317 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
319 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
320 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
321 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
322 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
323 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
324 #define CONFIG_SYS_FSL_SRDS_1
325 #define CONFIG_SYS_NUM_FMAN 1
326 #define CONFIG_SYS_NUM_FM1_DTSEC 5
327 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
328 #define CONFIG_PME_PLAT_CLK_DIV 2
329 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
330 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
331 #define CONFIG_SYS_FMAN_V3
332 #define CONFIG_FM_PLAT_CLK_DIV 1
333 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
334 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
335 per rcw field value */
336 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
337 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
338 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
339 #define CONFIG_SYS_FSL_TBCLK_DIV 16
340 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
341 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
342 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
343 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
344 #define QE_MURAM_SIZE 0x6000UL
345 #define MAX_QE_RISC 1
346 #define QE_NUM_OF_SNUM 28
347 #define CONFIG_SYS_FSL_SFP_VER_3_0
349 #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
351 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
352 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
353 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
354 #define CONFIG_SYS_FMAN_V3
355 #define CONFIG_SYS_FSL_NUM_CC_PLL 2
356 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
357 #define CONFIG_SYS_FSL_SRDS_1
358 #define CONFIG_SYS_NUM_FMAN 1
359 #define CONFIG_SYS_NUM_FM1_DTSEC 4
360 #define CONFIG_SYS_NUM_FM1_10GEC 1
361 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
362 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
363 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
364 #define CONFIG_SYS_FM1_CLK 0
365 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
366 per rcw field value */
367 #define CONFIG_QBMAN_CLK_DIV 1
368 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
369 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
370 #define CONFIG_SYS_FSL_TBCLK_DIV 16
371 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
372 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
373 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
374 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
375 #define QE_MURAM_SIZE 0x6000UL
376 #define MAX_QE_RISC 1
377 #define QE_NUM_OF_SNUM 28
378 #define CONFIG_SYS_FSL_SFP_VER_3_0
380 #elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
381 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
382 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
383 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
384 #define CONFIG_SYS_FSL_QMAN_V3
385 #define CONFIG_SYS_NUM_FMAN 1
386 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
387 #define CONFIG_SYS_FSL_SRDS_1
388 #define CONFIG_SYS_FSL_PCI_VER_3_X
389 #if defined(CONFIG_ARCH_T2080)
390 #define CONFIG_SYS_NUM_FM1_DTSEC 8
391 #define CONFIG_SYS_NUM_FM1_10GEC 4
392 #define CONFIG_SYS_FSL_SRDS_2
393 #define CONFIG_SYS_FSL_SRIO_LIODN
394 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
395 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
396 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
397 #elif defined(CONFIG_ARCH_T2081)
398 #define CONFIG_SYS_NUM_FM1_DTSEC 6
399 #define CONFIG_SYS_NUM_FM1_10GEC 2
401 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
402 #define CONFIG_PME_PLAT_CLK_DIV 1
403 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
404 #define CONFIG_SYS_FM1_CLK 0
405 #define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2
406 per rcw field value */
407 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
408 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
409 #define CONFIG_SYS_FMAN_V3
410 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
411 #define CONFIG_SYS_FSL_TBCLK_DIV 16
412 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
413 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
414 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
415 #define CONFIG_SYS_FSL_SFP_VER_3_0
416 #define CONFIG_SYS_FSL_ISBC_VER 2
417 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
418 #define CONFIG_SYS_FSL_SFP_VER_3_0
421 #elif defined(CONFIG_ARCH_C29X)
422 #define CONFIG_FSL_SDHC_V2_3
423 #define CONFIG_TSECV2_1
424 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
425 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
426 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
430 #if !defined(CONFIG_ARCH_C29X)
431 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
434 #endif /* _ASM_MPC85xx_CONFIG_H_ */