2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _ASM_MPC85xx_CONFIG_H_
8 #define _ASM_MPC85xx_CONFIG_H_
10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
13 * This macro should be removed when we no longer care about backwards
14 * compatibility with older operating systems.
16 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
18 #include <fsl_ddrc_version.h>
19 #define CONFIG_SYS_FSL_DDR_BE
22 #define CONFIG_SYS_FSL_IFC_BE
23 #define CONFIG_SYS_FSL_SEC_BE
24 #define CONFIG_SYS_FSL_SFP_BE
25 #define CONFIG_SYS_FSL_SEC_MON_BE
27 /* Number of TLB CAM entries we have on FSL Book-E chips */
28 #if defined(CONFIG_E500MC)
29 #define CONFIG_SYS_NUM_TLBCAMS 64
30 #elif defined(CONFIG_E500)
31 #define CONFIG_SYS_NUM_TLBCAMS 16
34 #if defined(CONFIG_ARCH_MPC8536)
35 #define CONFIG_SYS_FSL_NUM_LAWS 12
36 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
37 #define CONFIG_SYS_FSL_SEC_COMPAT 2
38 #define CONFIG_SYS_FSL_ERRATUM_A004508
39 #define CONFIG_SYS_FSL_ERRATUM_A005125
41 #elif defined(CONFIG_ARCH_MPC8540)
42 #define CONFIG_SYS_FSL_NUM_LAWS 8
43 #define CONFIG_SYS_FSL_DDRC_GEN1
45 #elif defined(CONFIG_ARCH_MPC8541)
46 #define CONFIG_SYS_FSL_NUM_LAWS 8
47 #define CONFIG_SYS_FSL_DDRC_GEN1
48 #define CONFIG_SYS_FSL_SEC_COMPAT 2
50 #elif defined(CONFIG_ARCH_MPC8544)
51 #define CONFIG_SYS_FSL_NUM_LAWS 10
52 #define CONFIG_SYS_FSL_DDRC_GEN2
53 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
54 #define CONFIG_SYS_FSL_SEC_COMPAT 2
55 #define CONFIG_SYS_FSL_ERRATUM_A005125
57 #elif defined(CONFIG_ARCH_MPC8548)
58 #define CONFIG_SYS_FSL_NUM_LAWS 10
59 #define CONFIG_SYS_FSL_DDRC_GEN2
60 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
61 #define CONFIG_SYS_FSL_SEC_COMPAT 2
62 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
63 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
64 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
65 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
66 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
67 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
68 #define CONFIG_SYS_FSL_RMU
69 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
70 #define CONFIG_SYS_FSL_ERRATUM_A005125
71 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
72 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
74 #elif defined(CONFIG_ARCH_MPC8555)
75 #define CONFIG_SYS_FSL_NUM_LAWS 8
76 #define CONFIG_SYS_FSL_DDRC_GEN1
77 #define CONFIG_SYS_FSL_SEC_COMPAT 2
79 #elif defined(CONFIG_ARCH_MPC8560)
80 #define CONFIG_SYS_FSL_NUM_LAWS 8
81 #define CONFIG_SYS_FSL_DDRC_GEN1
83 #elif defined(CONFIG_ARCH_MPC8568)
84 #define CONFIG_SYS_FSL_NUM_LAWS 10
85 #define CONFIG_SYS_FSL_DDRC_GEN2
86 #define CONFIG_SYS_FSL_SEC_COMPAT 2
87 #define QE_MURAM_SIZE 0x10000UL
89 #define QE_NUM_OF_SNUM 28
90 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
91 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
92 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
93 #define CONFIG_SYS_FSL_RMU
94 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
96 #elif defined(CONFIG_ARCH_MPC8569)
97 #define CONFIG_SYS_FSL_NUM_LAWS 10
98 #define CONFIG_SYS_FSL_SEC_COMPAT 2
99 #define QE_MURAM_SIZE 0x20000UL
100 #define MAX_QE_RISC 4
101 #define QE_NUM_OF_SNUM 46
102 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
103 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
104 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
105 #define CONFIG_SYS_FSL_RMU
106 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
107 #define CONFIG_SYS_FSL_ERRATUM_A004508
108 #define CONFIG_SYS_FSL_ERRATUM_A005125
110 #elif defined(CONFIG_ARCH_MPC8572)
111 #define CONFIG_SYS_FSL_NUM_LAWS 12
112 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
113 #define CONFIG_SYS_FSL_SEC_COMPAT 2
114 #define CONFIG_SYS_FSL_ERRATUM_DDR_115
115 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
116 #define CONFIG_SYS_FSL_ERRATUM_A004508
117 #define CONFIG_SYS_FSL_ERRATUM_A005125
119 #elif defined(CONFIG_ARCH_P1010)
120 #define CONFIG_FSL_SDHC_V2_3
121 #define CONFIG_SYS_FSL_NUM_LAWS 12
122 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
123 #define CONFIG_TSECV2
124 #define CONFIG_SYS_FSL_SEC_COMPAT 4
125 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
126 #define CONFIG_NUM_DDR_CONTROLLERS 1
127 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
128 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
129 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
130 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
131 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
132 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
133 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
134 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
135 #define CONFIG_SYS_FSL_ERRATUM_A005125
136 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
137 #define CONFIG_SYS_FSL_ERRATUM_A004508
138 #define CONFIG_SYS_FSL_ERRATUM_A007075
139 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
140 #define CONFIG_SYS_FSL_ERRATUM_A006261
141 #define CONFIG_SYS_FSL_ERRATUM_A004477
142 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
143 #define CONFIG_ESDHC_HC_BLK_ADDR
145 /* P1011 is single core version of P1020 */
146 #elif defined(CONFIG_ARCH_P1011)
147 #define CONFIG_SYS_FSL_NUM_LAWS 12
148 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
149 #define CONFIG_TSECV2
150 #define CONFIG_FSL_PCIE_DISABLE_ASPM
151 #define CONFIG_SYS_FSL_SEC_COMPAT 2
152 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
153 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
154 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
155 #define CONFIG_SYS_FSL_ERRATUM_A004508
156 #define CONFIG_SYS_FSL_ERRATUM_A005125
158 #elif defined(CONFIG_ARCH_P1020)
159 #define CONFIG_SYS_FSL_NUM_LAWS 12
160 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
161 #define CONFIG_TSECV2
162 #define CONFIG_FSL_PCIE_DISABLE_ASPM
163 #define CONFIG_SYS_FSL_SEC_COMPAT 2
164 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
165 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
166 #define CONFIG_SYS_FSL_ERRATUM_A004508
167 #define CONFIG_SYS_FSL_ERRATUM_A005125
168 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
169 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
172 #elif defined(CONFIG_ARCH_P1021)
173 #define CONFIG_SYS_FSL_NUM_LAWS 12
174 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
175 #define CONFIG_TSECV2
176 #define CONFIG_FSL_PCIE_DISABLE_ASPM
177 #define CONFIG_SYS_FSL_SEC_COMPAT 2
178 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
179 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
180 #define QE_MURAM_SIZE 0x6000UL
181 #define MAX_QE_RISC 1
182 #define QE_NUM_OF_SNUM 28
183 #define CONFIG_SYS_FSL_ERRATUM_A004508
184 #define CONFIG_SYS_FSL_ERRATUM_A005125
185 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
187 #elif defined(CONFIG_ARCH_P1022)
188 #define CONFIG_SYS_FSL_NUM_LAWS 12
189 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
190 #define CONFIG_TSECV2
191 #define CONFIG_SYS_FSL_SEC_COMPAT 2
192 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
193 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
194 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
195 #define CONFIG_FSL_SATA_ERRATUM_A001
196 #define CONFIG_SYS_FSL_ERRATUM_A004508
197 #define CONFIG_SYS_FSL_ERRATUM_A005125
198 #define CONFIG_SYS_FSL_ERRATUM_A004477
200 #elif defined(CONFIG_ARCH_P1023)
201 #define CONFIG_SYS_FSL_NUM_LAWS 12
202 #define CONFIG_SYS_FSL_SEC_COMPAT 4
203 #define CONFIG_SYS_NUM_FMAN 1
204 #define CONFIG_SYS_NUM_FM1_DTSEC 2
205 #define CONFIG_NUM_DDR_CONTROLLERS 1
206 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
207 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
208 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
209 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
210 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
211 #define CONFIG_SYS_FSL_ERRATUM_A004508
212 #define CONFIG_SYS_FSL_ERRATUM_A005125
213 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
214 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
216 /* P1024 is lower end variant of P1020 */
217 #elif defined(CONFIG_ARCH_P1024)
218 #define CONFIG_SYS_FSL_NUM_LAWS 12
219 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
220 #define CONFIG_TSECV2
221 #define CONFIG_FSL_PCIE_DISABLE_ASPM
222 #define CONFIG_SYS_FSL_SEC_COMPAT 2
223 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
224 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
225 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
226 #define CONFIG_SYS_FSL_ERRATUM_A004508
227 #define CONFIG_SYS_FSL_ERRATUM_A005125
229 /* P1025 is lower end variant of P1021 */
230 #elif defined(CONFIG_ARCH_P1025)
231 #define CONFIG_SYS_FSL_NUM_LAWS 12
232 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
233 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
234 #define CONFIG_TSECV2
235 #define CONFIG_FSL_PCIE_DISABLE_ASPM
236 #define CONFIG_SYS_FSL_SEC_COMPAT 2
237 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
238 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
239 #define QE_MURAM_SIZE 0x6000UL
240 #define MAX_QE_RISC 1
241 #define QE_NUM_OF_SNUM 28
242 #define CONFIG_SYS_FSL_ERRATUM_A004508
243 #define CONFIG_SYS_FSL_ERRATUM_A005125
245 #elif defined(CONFIG_ARCH_P2020)
246 #define CONFIG_SYS_FSL_NUM_LAWS 12
247 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
248 #define CONFIG_SYS_FSL_SEC_COMPAT 2
249 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
250 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
251 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
252 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
253 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
254 #define CONFIG_SYS_FSL_RMU
255 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
256 #define CONFIG_SYS_FSL_ERRATUM_A004508
257 #define CONFIG_SYS_FSL_ERRATUM_A005125
258 #define CONFIG_SYS_FSL_ERRATUM_A004477
259 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
261 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
262 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
263 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
264 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
265 #define CONFIG_SYS_FSL_NUM_LAWS 32
266 #define CONFIG_SYS_FSL_SEC_COMPAT 4
267 #define CONFIG_SYS_NUM_FMAN 1
268 #define CONFIG_SYS_NUM_FM1_DTSEC 5
269 #define CONFIG_SYS_NUM_FM1_10GEC 1
270 #define CONFIG_NUM_DDR_CONTROLLERS 1
271 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
272 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
273 #define CONFIG_SYS_FSL_TBCLK_DIV 32
274 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
275 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
276 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
277 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
278 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
279 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
280 #define CONFIG_SYS_FSL_ERRATUM_USB14
281 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
282 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
283 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
284 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
285 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
286 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
287 #define CONFIG_SYS_FSL_ERRATUM_A004510
288 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
289 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
290 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
291 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
292 #define CONFIG_SYS_FSL_ERRATUM_A004849
293 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
294 #define CONFIG_SYS_FSL_ERRATUM_A006261
295 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
297 #elif defined(CONFIG_ARCH_P3041)
298 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
299 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
300 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
301 #define CONFIG_SYS_FSL_NUM_LAWS 32
302 #define CONFIG_SYS_FSL_SEC_COMPAT 4
303 #define CONFIG_SYS_NUM_FMAN 1
304 #define CONFIG_SYS_NUM_FM1_DTSEC 5
305 #define CONFIG_SYS_NUM_FM1_10GEC 1
306 #define CONFIG_NUM_DDR_CONTROLLERS 1
307 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5
308 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
309 #define CONFIG_SYS_FSL_TBCLK_DIV 32
310 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
311 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
312 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
313 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
314 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
315 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
316 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
317 #define CONFIG_SYS_FSL_ERRATUM_USB14
318 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
319 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
320 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
321 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
322 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
323 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
324 #define CONFIG_SYS_FSL_ERRATUM_A004510
325 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
326 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
327 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
328 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
329 #define CONFIG_SYS_FSL_ERRATUM_A004849
330 #define CONFIG_SYS_FSL_ERRATUM_A005812
331 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
332 #define CONFIG_SYS_FSL_ERRATUM_A006261
333 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
335 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
336 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
337 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
338 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
339 #define CONFIG_SYS_FSL_NUM_LAWS 32
340 #define CONFIG_SYS_FSL_SEC_COMPAT 4
341 #define CONFIG_SYS_NUM_FMAN 2
342 #define CONFIG_SYS_NUM_FM1_DTSEC 4
343 #define CONFIG_SYS_NUM_FM2_DTSEC 4
344 #define CONFIG_SYS_NUM_FM1_10GEC 1
345 #define CONFIG_SYS_NUM_FM2_10GEC 1
346 #define CONFIG_NUM_DDR_CONTROLLERS 2
347 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
348 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
349 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
350 #define CONFIG_SYS_FSL_TBCLK_DIV 16
351 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
352 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
353 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
354 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
355 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
356 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
357 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
358 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13
359 #define CONFIG_SYS_P4080_ERRATUM_CPU22
360 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
361 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
362 #define CONFIG_SYS_P4080_ERRATUM_SERDES9
363 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
364 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
365 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
366 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
367 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
368 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
369 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
370 #define CONFIG_SYS_FSL_RMU
371 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
372 #define CONFIG_SYS_FSL_ERRATUM_A004510
373 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
374 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
375 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
376 #define CONFIG_SYS_FSL_ERRATUM_A004849
377 #define CONFIG_SYS_FSL_ERRATUM_A004580
378 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
379 #define CONFIG_SYS_FSL_ERRATUM_A005812
380 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
381 #define CONFIG_SYS_FSL_ERRATUM_A007075
382 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
384 #elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */
385 #define CONFIG_SYS_PPC64 /* 64-bit core */
386 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
387 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
388 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
389 #define CONFIG_SYS_FSL_NUM_LAWS 32
390 #define CONFIG_SYS_FSL_SEC_COMPAT 4
391 #define CONFIG_SYS_NUM_FMAN 1
392 #define CONFIG_SYS_NUM_FM1_DTSEC 5
393 #define CONFIG_SYS_NUM_FM1_10GEC 1
394 #define CONFIG_NUM_DDR_CONTROLLERS 2
395 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
396 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
397 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
398 #define CONFIG_SYS_FSL_TBCLK_DIV 32
399 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
400 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
401 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
402 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
403 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
404 #define CONFIG_SYS_FSL_ERRATUM_USB14
405 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
406 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
407 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
408 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
409 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
410 #define CONFIG_SYS_FSL_ERRATUM_A004510
411 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
412 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
413 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
414 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
415 #define CONFIG_SYS_FSL_ERRATUM_A006261
416 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
418 #elif defined(CONFIG_ARCH_P5040)
419 #define CONFIG_SYS_PPC64
420 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
421 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
422 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
423 #define CONFIG_SYS_FSL_NUM_LAWS 32
424 #define CONFIG_SYS_FSL_SEC_COMPAT 4
425 #define CONFIG_SYS_NUM_FMAN 2
426 #define CONFIG_SYS_NUM_FM1_DTSEC 5
427 #define CONFIG_SYS_NUM_FM1_10GEC 1
428 #define CONFIG_SYS_NUM_FM2_DTSEC 5
429 #define CONFIG_SYS_NUM_FM2_10GEC 1
430 #define CONFIG_NUM_DDR_CONTROLLERS 2
431 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
432 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
433 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
434 #define CONFIG_SYS_FSL_TBCLK_DIV 16
435 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
436 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
437 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
438 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
439 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
440 #define CONFIG_SYS_FSL_ERRATUM_USB14
441 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
442 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
443 #define CONFIG_SYS_FSL_ERRATUM_A004699
444 #define CONFIG_SYS_FSL_ERRATUM_A004510
445 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
446 #define CONFIG_SYS_FSL_ERRATUM_A006261
447 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
448 #define CONFIG_SYS_FSL_ERRATUM_A005812
450 #elif defined(CONFIG_ARCH_BSC9131)
451 #define CONFIG_FSL_SDHC_V2_3
452 #define CONFIG_SYS_FSL_NUM_LAWS 12
453 #define CONFIG_TSECV2
454 #define CONFIG_SYS_FSL_SEC_COMPAT 4
455 #define CONFIG_NUM_DDR_CONTROLLERS 1
456 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
457 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
458 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
459 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
460 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
461 #define CONFIG_NAND_FSL_IFC
462 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
463 #define CONFIG_SYS_FSL_ERRATUM_A005125
464 #define CONFIG_SYS_FSL_ERRATUM_A004477
465 #define CONFIG_ESDHC_HC_BLK_ADDR
467 #elif defined(CONFIG_ARCH_BSC9132)
468 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
469 #define CONFIG_FSL_SDHC_V2_3
470 #define CONFIG_SYS_FSL_NUM_LAWS 12
471 #define CONFIG_TSECV2
472 #define CONFIG_SYS_FSL_SEC_COMPAT 4
473 #define CONFIG_NUM_DDR_CONTROLLERS 2
474 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
475 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
476 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
477 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
478 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
479 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
480 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
481 #define CONFIG_NAND_FSL_IFC
482 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
483 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
484 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
485 #define CONFIG_SYS_FSL_ERRATUM_A005125
486 #define CONFIG_SYS_FSL_ERRATUM_A005434
487 #define CONFIG_SYS_FSL_ERRATUM_A004477
488 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
489 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
490 #define CONFIG_ESDHC_HC_BLK_ADDR
492 #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
494 #define CONFIG_SYS_PPC64 /* 64-bit core */
495 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
496 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
497 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
498 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
499 #ifdef CONFIG_ARCH_T4240
500 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
501 #define CONFIG_SYS_NUM_FM1_DTSEC 8
502 #define CONFIG_SYS_NUM_FM1_10GEC 2
503 #define CONFIG_SYS_NUM_FM2_DTSEC 8
504 #define CONFIG_SYS_NUM_FM2_10GEC 2
505 #define CONFIG_NUM_DDR_CONTROLLERS 3
506 #define CONFIG_SYS_FSL_ERRATUM_A006261
508 #define CONFIG_SYS_NUM_FM1_DTSEC 6
509 #define CONFIG_SYS_NUM_FM1_10GEC 1
510 #define CONFIG_SYS_NUM_FM2_DTSEC 8
511 #define CONFIG_SYS_NUM_FM2_10GEC 1
512 #define CONFIG_NUM_DDR_CONTROLLERS 2
513 #if defined(CONFIG_ARCH_T4160)
514 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
517 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
518 #define CONFIG_SYS_FSL_NUM_LAWS 32
519 #define CONFIG_SYS_FSL_SRDS_1
520 #define CONFIG_SYS_FSL_SRDS_2
521 #define CONFIG_SYS_FSL_SRDS_3
522 #define CONFIG_SYS_FSL_SRDS_4
523 #define CONFIG_SYS_FSL_SEC_COMPAT 4
524 #define CONFIG_SYS_NUM_FMAN 2
525 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
526 #define CONFIG_SYS_PME_CLK 0
527 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
528 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
529 #define CONFIG_SYS_FMAN_V3
530 #define CONFIG_SYS_FM1_CLK 3
531 #define CONFIG_SYS_FM2_CLK 3
532 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
533 #define CONFIG_SYS_FSL_TBCLK_DIV 16
534 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
535 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
536 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
537 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
538 #define CONFIG_SYS_FSL_SRIO_LIODN
539 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
540 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
541 #define CONFIG_SYS_FSL_ERRATUM_A004468
542 #define CONFIG_SYS_FSL_ERRATUM_A_004934
543 #define CONFIG_SYS_FSL_ERRATUM_A005871
544 #define CONFIG_SYS_FSL_ERRATUM_A006379
545 #define CONFIG_SYS_FSL_ERRATUM_A007186
546 #define CONFIG_SYS_FSL_ERRATUM_A006593
547 #define CONFIG_SYS_FSL_ERRATUM_A007798
548 #define CONFIG_SYS_FSL_SFP_VER_3_0
549 #define CONFIG_SYS_FSL_PCI_VER_3_X
551 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
553 #define CONFIG_SYS_PPC64 /* 64-bit core */
554 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
555 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
556 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
557 #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
558 #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
559 #define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/
560 #define CONFIG_SYS_FSL_NUM_LAWS 32
561 #define CONFIG_SYS_FSL_SRDS_1
562 #define CONFIG_SYS_FSL_SRDS_2
563 #define CONFIG_SYS_MAPLE
564 #define CONFIG_SYS_CPRI
565 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
566 #define CONFIG_SYS_FSL_SEC_COMPAT 4
567 #define CONFIG_SYS_NUM_FMAN 1
568 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
569 #define CONFIG_SYS_FM1_CLK 0
570 #define CONFIG_SYS_CPRI_CLK 3
571 #define CONFIG_SYS_ULB_CLK 4
572 #define CONFIG_SYS_ETVPE_CLK 1
573 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
574 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
575 #define CONFIG_SYS_FMAN_V3
576 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
577 #define CONFIG_SYS_FSL_TBCLK_DIV 16
578 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
579 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
580 #define CONFIG_SYS_FSL_ERRATUM_A_004934
581 #define CONFIG_SYS_FSL_ERRATUM_A005871
582 #define CONFIG_SYS_FSL_ERRATUM_A006379
583 #define CONFIG_SYS_FSL_ERRATUM_A007186
584 #define CONFIG_SYS_FSL_ERRATUM_A006593
585 #define CONFIG_SYS_FSL_ERRATUM_A007075
586 #define CONFIG_SYS_FSL_ERRATUM_A006475
587 #define CONFIG_SYS_FSL_ERRATUM_A006384
588 #define CONFIG_SYS_FSL_ERRATUM_A007212
589 #define CONFIG_SYS_FSL_ERRATUM_A004477
590 #define CONFIG_SYS_FSL_SFP_VER_3_0
592 #ifdef CONFIG_ARCH_B4860
593 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
594 #define CONFIG_MAX_DSP_CPUS 12
595 #define CONFIG_NUM_DSP_CPUS 6
596 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
597 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
598 #define CONFIG_SYS_NUM_FM1_DTSEC 6
599 #define CONFIG_SYS_NUM_FM1_10GEC 2
600 #define CONFIG_NUM_DDR_CONTROLLERS 2
601 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
602 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
603 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
604 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
605 #define CONFIG_SYS_FSL_SRIO_LIODN
607 #define CONFIG_MAX_DSP_CPUS 2
608 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
609 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
610 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
611 #define CONFIG_SYS_NUM_FM1_DTSEC 4
612 #define CONFIG_SYS_NUM_FM1_10GEC 0
613 #define CONFIG_NUM_DDR_CONTROLLERS 1
616 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) ||\
617 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
619 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
620 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
621 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
622 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
623 #ifdef CONFIG_SYS_FSL_DDR4
624 #define CONFIG_SYS_FSL_DDRC_GEN4
626 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
627 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
628 #define CONFIG_SYS_FSL_NUM_LAWS 16
629 #define CONFIG_SYS_FSL_SRDS_1
630 #define CONFIG_SYS_FSL_SEC_COMPAT 5
631 #define CONFIG_SYS_NUM_FMAN 1
632 #define CONFIG_SYS_NUM_FM1_DTSEC 5
633 #define CONFIG_NUM_DDR_CONTROLLERS 1
634 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
635 #define CONFIG_PME_PLAT_CLK_DIV 2
636 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
637 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
638 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
639 #define CONFIG_SYS_FSL_ERRATUM_A008044
640 #define CONFIG_SYS_FMAN_V3
641 #define CONFIG_FM_PLAT_CLK_DIV 1
642 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
643 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
644 per rcw field value */
645 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
646 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
647 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
648 #define CONFIG_SYS_FSL_TBCLK_DIV 16
649 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
650 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
651 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
652 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
653 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
654 #define QE_MURAM_SIZE 0x6000UL
655 #define MAX_QE_RISC 1
656 #define QE_NUM_OF_SNUM 28
657 #define CONFIG_SYS_FSL_SFP_VER_3_0
658 #define CONFIG_SYS_FSL_ERRATUM_A008378
659 #define CONFIG_SYS_FSL_ERRATUM_A009663
661 #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) ||\
662 defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
664 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
665 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
666 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
667 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
668 #define CONFIG_SYS_FMAN_V3
669 #ifdef CONFIG_SYS_FSL_DDR4
670 #define CONFIG_SYS_FSL_DDRC_GEN4
672 #define CONFIG_SYS_FSL_NUM_CC_PLL 2
673 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
674 #define CONFIG_SYS_FSL_NUM_LAWS 16
675 #define CONFIG_SYS_FSL_SRDS_1
676 #define CONFIG_SYS_FSL_SEC_COMPAT 5
677 #define CONFIG_SYS_NUM_FMAN 1
678 #define CONFIG_SYS_NUM_FM1_DTSEC 4
679 #define CONFIG_SYS_NUM_FM1_10GEC 1
680 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
681 #define CONFIG_NUM_DDR_CONTROLLERS 1
682 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
683 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
684 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
685 #define CONFIG_SYS_FM1_CLK 0
686 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
687 per rcw field value */
688 #define CONFIG_QBMAN_CLK_DIV 1
689 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
690 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
691 #define CONFIG_SYS_FSL_TBCLK_DIV 16
692 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
693 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
694 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
695 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
696 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
697 #define QE_MURAM_SIZE 0x6000UL
698 #define MAX_QE_RISC 1
699 #define QE_NUM_OF_SNUM 28
700 #define CONFIG_SYS_FSL_SFP_VER_3_0
701 #define CONFIG_SYS_FSL_ERRATUM_A008378
702 #define CONFIG_SYS_FSL_ERRATUM_A009663
704 #elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
706 #define CONFIG_SYS_PPC64 /* 64-bit core */
707 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
708 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
709 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
710 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
711 #define CONFIG_SYS_FSL_QMAN_V3
712 #define CONFIG_SYS_FSL_NUM_LAWS 32
713 #define CONFIG_SYS_FSL_SEC_COMPAT 4
714 #define CONFIG_SYS_NUM_FMAN 1
715 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
716 #define CONFIG_SYS_FSL_SRDS_1
717 #define CONFIG_SYS_FSL_PCI_VER_3_X
718 #if defined(CONFIG_ARCH_T2080)
719 #define CONFIG_SYS_NUM_FM1_DTSEC 8
720 #define CONFIG_SYS_NUM_FM1_10GEC 4
721 #define CONFIG_SYS_FSL_SRDS_2
722 #define CONFIG_SYS_FSL_SRIO_LIODN
723 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
724 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
725 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
726 #elif defined(CONFIG_ARCH_T2081)
727 #define CONFIG_SYS_NUM_FM1_DTSEC 6
728 #define CONFIG_SYS_NUM_FM1_10GEC 2
730 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
731 #define CONFIG_NUM_DDR_CONTROLLERS 1
732 #define CONFIG_PME_PLAT_CLK_DIV 1
733 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
734 #define CONFIG_SYS_FM1_CLK 0
735 #define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2
736 per rcw field value */
737 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
738 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
739 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
740 #define CONFIG_SYS_FMAN_V3
741 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
742 #define CONFIG_SYS_FSL_TBCLK_DIV 16
743 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
744 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
745 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
746 #define CONFIG_SYS_FSL_ERRATUM_A007212
747 #define CONFIG_SYS_FSL_SFP_VER_3_0
748 #define CONFIG_SYS_FSL_ISBC_VER 2
749 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
750 #define CONFIG_SYS_FSL_ERRATUM_A006593
751 #define CONFIG_SYS_FSL_ERRATUM_A007186
752 #define CONFIG_SYS_FSL_ERRATUM_A006379
753 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
754 #define CONFIG_SYS_FSL_SFP_VER_3_0
757 #elif defined(CONFIG_ARCH_C29X)
758 #define CONFIG_FSL_SDHC_V2_3
759 #define CONFIG_SYS_FSL_NUM_LAWS 12
760 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
761 #define CONFIG_TSECV2_1
762 #define CONFIG_SYS_FSL_SEC_COMPAT 6
763 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
764 #define CONFIG_NUM_DDR_CONTROLLERS 1
765 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
766 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
767 #define CONFIG_SYS_FSL_ERRATUM_A005125
768 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
769 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
771 #elif defined(CONFIG_ARCH_QEMU_E500)
774 #error Processor type not defined for this platform
778 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2
780 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1
783 #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
784 !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
785 !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \
786 !defined(CONFIG_SYS_FSL_DDRC_GEN4)
787 #define CONFIG_SYS_FSL_DDRC_GEN3
790 #if !defined(CONFIG_ARCH_C29X)
791 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
794 #endif /* _ASM_MPC85xx_CONFIG_H_ */