1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
6 #ifndef _ASM_MPC85xx_CONFIG_H_
7 #define _ASM_MPC85xx_CONFIG_H_
9 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
12 * This macro should be removed when we no longer care about backwards
13 * compatibility with older operating systems.
15 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
17 #include <fsl_ddrc_version.h>
20 #define CONFIG_SYS_FSL_IFC_BE
22 #if defined(CONFIG_ARCH_MPC8548)
23 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
24 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
25 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
26 #define CONFIG_SYS_FSL_RMU
27 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
29 #elif defined(CONFIG_ARCH_P1010)
30 #define CONFIG_FSL_SDHC_V2_3
32 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
33 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
34 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
35 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
37 /* P1011 is single core version of P1020 */
38 #elif defined(CONFIG_ARCH_P1011)
41 #elif defined(CONFIG_ARCH_P1020)
44 #elif defined(CONFIG_ARCH_P1021)
46 #define QE_MURAM_SIZE 0x6000UL
48 #define QE_NUM_OF_SNUM 28
50 #elif defined(CONFIG_ARCH_P1023)
51 #define CONFIG_SYS_NUM_FMAN 1
52 #define CONFIG_SYS_NUM_FM1_DTSEC 2
53 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
54 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
55 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
56 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
58 /* P1024 is lower end variant of P1020 */
59 #elif defined(CONFIG_ARCH_P1024)
62 /* P1025 is lower end variant of P1021 */
63 #elif defined(CONFIG_ARCH_P1025)
65 #define QE_MURAM_SIZE 0x6000UL
67 #define QE_NUM_OF_SNUM 28
69 #elif defined(CONFIG_ARCH_P2020)
70 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
71 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
72 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
73 #define CONFIG_SYS_FSL_RMU
74 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
76 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
77 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
78 #define CONFIG_SYS_NUM_FMAN 1
79 #define CONFIG_SYS_NUM_FM1_DTSEC 5
80 #define CONFIG_SYS_NUM_FM1_10GEC 1
81 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
82 #define CONFIG_SYS_FSL_TBCLK_DIV 32
83 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
84 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
85 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
86 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
87 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
88 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
89 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
90 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
92 #elif defined(CONFIG_ARCH_P3041)
93 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
94 #define CONFIG_SYS_NUM_FMAN 1
95 #define CONFIG_SYS_NUM_FM1_DTSEC 5
96 #define CONFIG_SYS_NUM_FM1_10GEC 1
97 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
98 #define CONFIG_SYS_FSL_TBCLK_DIV 32
99 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
100 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
101 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
102 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
103 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
104 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
105 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
106 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
108 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
109 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
110 #define CONFIG_SYS_NUM_FMAN 2
111 #define CONFIG_SYS_NUM_FM1_DTSEC 4
112 #define CONFIG_SYS_NUM_FM2_DTSEC 4
113 #define CONFIG_SYS_NUM_FM1_10GEC 1
114 #define CONFIG_SYS_NUM_FM2_10GEC 1
115 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
116 #define CONFIG_SYS_FSL_TBCLK_DIV 16
117 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
118 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
119 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
120 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
121 #define CONFIG_SYS_FSL_RMU
122 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
123 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
125 #elif defined(CONFIG_ARCH_P5040)
126 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
127 #define CONFIG_SYS_NUM_FMAN 2
128 #define CONFIG_SYS_NUM_FM1_DTSEC 5
129 #define CONFIG_SYS_NUM_FM1_10GEC 1
130 #define CONFIG_SYS_NUM_FM2_DTSEC 5
131 #define CONFIG_SYS_NUM_FM2_10GEC 1
132 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
133 #define CONFIG_SYS_FSL_TBCLK_DIV 16
134 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
135 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
136 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
137 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
138 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
140 #elif defined(CONFIG_ARCH_BSC9131)
141 #define CONFIG_FSL_SDHC_V2_3
142 #define CONFIG_TSECV2
143 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
144 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
145 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
147 #elif defined(CONFIG_ARCH_BSC9132)
148 #define CONFIG_FSL_SDHC_V2_3
149 #define CONFIG_TSECV2
150 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
151 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
152 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
153 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
154 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
155 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
156 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
158 #elif defined(CONFIG_ARCH_T4240)
159 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
160 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
161 #ifdef CONFIG_ARCH_T4240
162 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
163 #define CONFIG_SYS_NUM_FM1_DTSEC 8
164 #define CONFIG_SYS_NUM_FM1_10GEC 2
165 #define CONFIG_SYS_NUM_FM2_DTSEC 8
166 #define CONFIG_SYS_NUM_FM2_10GEC 2
168 #define CONFIG_SYS_NUM_FM1_DTSEC 6
169 #define CONFIG_SYS_NUM_FM1_10GEC 1
170 #define CONFIG_SYS_NUM_FM2_DTSEC 8
171 #define CONFIG_SYS_NUM_FM2_10GEC 1
173 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
174 #define CONFIG_SYS_FSL_SRDS_1
175 #define CONFIG_SYS_FSL_SRDS_2
176 #define CONFIG_SYS_FSL_SRDS_3
177 #define CONFIG_SYS_FSL_SRDS_4
178 #define CONFIG_SYS_NUM_FMAN 2
179 #define CONFIG_SYS_PME_CLK 0
180 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
181 #define CONFIG_SYS_FM1_CLK 3
182 #define CONFIG_SYS_FM2_CLK 3
183 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
184 #define CONFIG_SYS_FSL_TBCLK_DIV 16
185 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
186 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
187 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
188 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
189 #define CONFIG_SYS_FSL_SRIO_LIODN
190 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
191 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
193 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
194 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
195 #define CONFIG_SYS_FSL_SRDS_1
196 #define CONFIG_SYS_FSL_SRDS_2
197 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
198 #define CONFIG_SYS_NUM_FMAN 1
199 #define CONFIG_SYS_FM1_CLK 0
200 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
201 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
202 #define CONFIG_SYS_FSL_TBCLK_DIV 16
203 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
204 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
206 #ifdef CONFIG_ARCH_B4860
207 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
208 #define CONFIG_MAX_DSP_CPUS 12
209 #define CONFIG_NUM_DSP_CPUS 6
210 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
211 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
212 #define CONFIG_SYS_NUM_FM1_DTSEC 6
213 #define CONFIG_SYS_NUM_FM1_10GEC 2
214 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
215 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
216 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
217 #define CONFIG_SYS_FSL_SRIO_LIODN
219 #define CONFIG_MAX_DSP_CPUS 2
220 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
221 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
222 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
223 #define CONFIG_SYS_NUM_FM1_DTSEC 4
224 #define CONFIG_SYS_NUM_FM1_10GEC 0
227 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
228 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
229 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
230 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
231 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
232 #define CONFIG_SYS_FSL_SRDS_1
233 #define CONFIG_SYS_NUM_FMAN 1
234 #define CONFIG_SYS_NUM_FM1_DTSEC 5
235 #define CONFIG_PME_PLAT_CLK_DIV 2
236 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
237 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
238 #define CONFIG_FM_PLAT_CLK_DIV 1
239 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
240 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
241 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
242 #define CONFIG_SYS_FSL_TBCLK_DIV 16
243 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
244 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
245 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
246 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
247 #define QE_MURAM_SIZE 0x6000UL
248 #define MAX_QE_RISC 1
249 #define QE_NUM_OF_SNUM 28
251 #elif defined(CONFIG_ARCH_T1024)
252 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
253 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
254 #define CONFIG_SYS_FSL_NUM_CC_PLL 2
255 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
256 #define CONFIG_SYS_FSL_SRDS_1
257 #define CONFIG_SYS_NUM_FMAN 1
258 #define CONFIG_SYS_NUM_FM1_DTSEC 4
259 #define CONFIG_SYS_NUM_FM1_10GEC 1
260 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
261 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
262 #define CONFIG_SYS_FM1_CLK 0
263 #define CONFIG_QBMAN_CLK_DIV 1
264 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
265 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
266 #define CONFIG_SYS_FSL_TBCLK_DIV 16
267 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
268 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
269 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
270 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
271 #define QE_MURAM_SIZE 0x6000UL
272 #define MAX_QE_RISC 1
273 #define QE_NUM_OF_SNUM 28
275 #elif defined(CONFIG_ARCH_T2080)
276 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
277 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
278 #define CONFIG_SYS_FSL_QMAN_V3
279 #define CONFIG_SYS_NUM_FMAN 1
280 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
281 #define CONFIG_SYS_FSL_SRDS_1
282 #if defined(CONFIG_ARCH_T2080)
283 #define CONFIG_SYS_NUM_FM1_DTSEC 8
284 #define CONFIG_SYS_NUM_FM1_10GEC 4
285 #define CONFIG_SYS_FSL_SRDS_2
286 #define CONFIG_SYS_FSL_SRIO_LIODN
287 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
288 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
289 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
291 #define CONFIG_PME_PLAT_CLK_DIV 1
292 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
293 #define CONFIG_SYS_FM1_CLK 0
294 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
295 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
296 #define CONFIG_SYS_FSL_TBCLK_DIV 16
297 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
298 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
299 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
300 #define CONFIG_SYS_FSL_ISBC_VER 2
301 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
304 #elif defined(CONFIG_ARCH_C29X)
305 #define CONFIG_FSL_SDHC_V2_3
306 #define CONFIG_TSECV2_1
307 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
308 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
309 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
313 #if !defined(CONFIG_ARCH_C29X)
314 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
317 #endif /* _ASM_MPC85xx_CONFIG_H_ */