2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _ASM_MPC85xx_CONFIG_H_
8 #define _ASM_MPC85xx_CONFIG_H_
10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
13 * This macro should be removed when we no longer care about backwards
14 * compatibility with older operating systems.
16 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
18 #include <fsl_ddrc_version.h>
21 #define CONFIG_SYS_FSL_IFC_BE
22 #define CONFIG_SYS_FSL_SFP_BE
23 #define CONFIG_SYS_FSL_SEC_MON_BE
25 #if defined(CONFIG_ARCH_MPC8536)
27 #elif defined(CONFIG_ARCH_MPC8540)
29 #elif defined(CONFIG_ARCH_MPC8541)
31 #elif defined(CONFIG_ARCH_MPC8544)
33 #elif defined(CONFIG_ARCH_MPC8548)
34 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
35 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
36 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
37 #define CONFIG_SYS_FSL_RMU
38 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
40 #elif defined(CONFIG_ARCH_MPC8555)
42 #elif defined(CONFIG_ARCH_MPC8560)
44 #elif defined(CONFIG_ARCH_MPC8568)
45 #define QE_MURAM_SIZE 0x10000UL
47 #define QE_NUM_OF_SNUM 28
48 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
49 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
50 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
51 #define CONFIG_SYS_FSL_RMU
52 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
54 #elif defined(CONFIG_ARCH_MPC8569)
55 #define QE_MURAM_SIZE 0x20000UL
57 #define QE_NUM_OF_SNUM 46
58 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
59 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
60 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
61 #define CONFIG_SYS_FSL_RMU
62 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
64 #elif defined(CONFIG_ARCH_MPC8572)
66 #elif defined(CONFIG_ARCH_P1010)
67 #define CONFIG_FSL_SDHC_V2_3
69 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
70 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
71 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
72 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
73 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
74 #define CONFIG_ESDHC_HC_BLK_ADDR
76 /* P1011 is single core version of P1020 */
77 #elif defined(CONFIG_ARCH_P1011)
79 #define CONFIG_FSL_PCIE_DISABLE_ASPM
80 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
82 #elif defined(CONFIG_ARCH_P1020)
84 #define CONFIG_FSL_PCIE_DISABLE_ASPM
85 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
86 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
89 #elif defined(CONFIG_ARCH_P1021)
91 #define CONFIG_FSL_PCIE_DISABLE_ASPM
92 #define QE_MURAM_SIZE 0x6000UL
94 #define QE_NUM_OF_SNUM 28
95 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
97 #elif defined(CONFIG_ARCH_P1022)
99 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
101 #elif defined(CONFIG_ARCH_P1023)
102 #define CONFIG_SYS_NUM_FMAN 1
103 #define CONFIG_SYS_NUM_FM1_DTSEC 2
104 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
105 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
106 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
107 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
108 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
110 /* P1024 is lower end variant of P1020 */
111 #elif defined(CONFIG_ARCH_P1024)
112 #define CONFIG_TSECV2
113 #define CONFIG_FSL_PCIE_DISABLE_ASPM
114 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
116 /* P1025 is lower end variant of P1021 */
117 #elif defined(CONFIG_ARCH_P1025)
118 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
119 #define CONFIG_TSECV2
120 #define CONFIG_FSL_PCIE_DISABLE_ASPM
121 #define QE_MURAM_SIZE 0x6000UL
122 #define MAX_QE_RISC 1
123 #define QE_NUM_OF_SNUM 28
125 #elif defined(CONFIG_ARCH_P2020)
126 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
127 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
128 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
129 #define CONFIG_SYS_FSL_RMU
130 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
131 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
133 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
134 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
135 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
136 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
137 #define CONFIG_SYS_NUM_FMAN 1
138 #define CONFIG_SYS_NUM_FM1_DTSEC 5
139 #define CONFIG_SYS_NUM_FM1_10GEC 1
140 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
141 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
142 #define CONFIG_SYS_FSL_TBCLK_DIV 32
143 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
144 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
145 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
146 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
147 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
148 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
149 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
150 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
152 #elif defined(CONFIG_ARCH_P3041)
153 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
154 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
155 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
156 #define CONFIG_SYS_NUM_FMAN 1
157 #define CONFIG_SYS_NUM_FM1_DTSEC 5
158 #define CONFIG_SYS_NUM_FM1_10GEC 1
159 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5
160 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
161 #define CONFIG_SYS_FSL_TBCLK_DIV 32
162 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
163 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
164 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
165 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
166 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
167 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
168 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
169 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
170 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
172 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
173 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
174 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
175 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
176 #define CONFIG_SYS_NUM_FMAN 2
177 #define CONFIG_SYS_NUM_FM1_DTSEC 4
178 #define CONFIG_SYS_NUM_FM2_DTSEC 4
179 #define CONFIG_SYS_NUM_FM1_10GEC 1
180 #define CONFIG_SYS_NUM_FM2_10GEC 1
181 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
182 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
183 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
184 #define CONFIG_SYS_FSL_TBCLK_DIV 16
185 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
186 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
187 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
188 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
189 #define CONFIG_SYS_FSL_RMU
190 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
191 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
193 #elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */
194 #define CONFIG_SYS_PPC64 /* 64-bit core */
195 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
196 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
197 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
198 #define CONFIG_SYS_NUM_FMAN 1
199 #define CONFIG_SYS_NUM_FM1_DTSEC 5
200 #define CONFIG_SYS_NUM_FM1_10GEC 1
201 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
202 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
203 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
204 #define CONFIG_SYS_FSL_TBCLK_DIV 32
205 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
206 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
207 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
208 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
209 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
210 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
211 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
212 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
214 #elif defined(CONFIG_ARCH_P5040)
215 #define CONFIG_SYS_PPC64
216 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
217 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
218 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
219 #define CONFIG_SYS_NUM_FMAN 2
220 #define CONFIG_SYS_NUM_FM1_DTSEC 5
221 #define CONFIG_SYS_NUM_FM1_10GEC 1
222 #define CONFIG_SYS_NUM_FM2_DTSEC 5
223 #define CONFIG_SYS_NUM_FM2_10GEC 1
224 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
225 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
226 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
227 #define CONFIG_SYS_FSL_TBCLK_DIV 16
228 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
229 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
230 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
231 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
232 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
234 #elif defined(CONFIG_ARCH_BSC9131)
235 #define CONFIG_FSL_SDHC_V2_3
236 #define CONFIG_TSECV2
237 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
238 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
239 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
240 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
241 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
242 #define CONFIG_NAND_FSL_IFC
243 #define CONFIG_ESDHC_HC_BLK_ADDR
245 #elif defined(CONFIG_ARCH_BSC9132)
246 #define CONFIG_FSL_SDHC_V2_3
247 #define CONFIG_TSECV2
248 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
249 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
250 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
251 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
252 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
253 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
254 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
255 #define CONFIG_NAND_FSL_IFC
256 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
257 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
258 #define CONFIG_ESDHC_HC_BLK_ADDR
260 #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
262 #define CONFIG_SYS_PPC64 /* 64-bit core */
263 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
264 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
265 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
266 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
267 #ifdef CONFIG_ARCH_T4240
268 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
269 #define CONFIG_SYS_NUM_FM1_DTSEC 8
270 #define CONFIG_SYS_NUM_FM1_10GEC 2
271 #define CONFIG_SYS_NUM_FM2_DTSEC 8
272 #define CONFIG_SYS_NUM_FM2_10GEC 2
274 #define CONFIG_SYS_NUM_FM1_DTSEC 6
275 #define CONFIG_SYS_NUM_FM1_10GEC 1
276 #define CONFIG_SYS_NUM_FM2_DTSEC 8
277 #define CONFIG_SYS_NUM_FM2_10GEC 1
278 #if defined(CONFIG_ARCH_T4160)
279 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
282 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
283 #define CONFIG_SYS_FSL_SRDS_1
284 #define CONFIG_SYS_FSL_SRDS_2
285 #define CONFIG_SYS_FSL_SRDS_3
286 #define CONFIG_SYS_FSL_SRDS_4
287 #define CONFIG_SYS_NUM_FMAN 2
288 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
289 #define CONFIG_SYS_PME_CLK 0
290 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
291 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
292 #define CONFIG_SYS_FMAN_V3
293 #define CONFIG_SYS_FM1_CLK 3
294 #define CONFIG_SYS_FM2_CLK 3
295 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
296 #define CONFIG_SYS_FSL_TBCLK_DIV 16
297 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
298 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
299 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
300 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
301 #define CONFIG_SYS_FSL_SRIO_LIODN
302 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
303 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
304 #define CONFIG_SYS_FSL_SFP_VER_3_0
305 #define CONFIG_SYS_FSL_PCI_VER_3_X
307 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
309 #define CONFIG_SYS_PPC64 /* 64-bit core */
310 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
311 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
312 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
313 #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
314 #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
315 #define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/
316 #define CONFIG_SYS_FSL_SRDS_1
317 #define CONFIG_SYS_FSL_SRDS_2
318 #define CONFIG_SYS_MAPLE
319 #define CONFIG_SYS_CPRI
320 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
321 #define CONFIG_SYS_NUM_FMAN 1
322 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
323 #define CONFIG_SYS_FM1_CLK 0
324 #define CONFIG_SYS_CPRI_CLK 3
325 #define CONFIG_SYS_ULB_CLK 4
326 #define CONFIG_SYS_ETVPE_CLK 1
327 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
328 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
329 #define CONFIG_SYS_FMAN_V3
330 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
331 #define CONFIG_SYS_FSL_TBCLK_DIV 16
332 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
333 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
334 #define CONFIG_SYS_FSL_SFP_VER_3_0
336 #ifdef CONFIG_ARCH_B4860
337 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
338 #define CONFIG_MAX_DSP_CPUS 12
339 #define CONFIG_NUM_DSP_CPUS 6
340 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
341 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
342 #define CONFIG_SYS_NUM_FM1_DTSEC 6
343 #define CONFIG_SYS_NUM_FM1_10GEC 2
344 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
345 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
346 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
347 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
348 #define CONFIG_SYS_FSL_SRIO_LIODN
350 #define CONFIG_MAX_DSP_CPUS 2
351 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
352 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
353 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
354 #define CONFIG_SYS_NUM_FM1_DTSEC 4
355 #define CONFIG_SYS_NUM_FM1_10GEC 0
358 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
360 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
361 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
362 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
363 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
364 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
365 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
366 #define CONFIG_SYS_FSL_SRDS_1
367 #define CONFIG_SYS_NUM_FMAN 1
368 #define CONFIG_SYS_NUM_FM1_DTSEC 5
369 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
370 #define CONFIG_PME_PLAT_CLK_DIV 2
371 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
372 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
373 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
374 #define CONFIG_SYS_FMAN_V3
375 #define CONFIG_FM_PLAT_CLK_DIV 1
376 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
377 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
378 per rcw field value */
379 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
380 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
381 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
382 #define CONFIG_SYS_FSL_TBCLK_DIV 16
383 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
384 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
385 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
386 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
387 #define QE_MURAM_SIZE 0x6000UL
388 #define MAX_QE_RISC 1
389 #define QE_NUM_OF_SNUM 28
390 #define CONFIG_SYS_FSL_SFP_VER_3_0
392 #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
394 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
395 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
396 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
397 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
398 #define CONFIG_SYS_FMAN_V3
399 #define CONFIG_SYS_FSL_NUM_CC_PLL 2
400 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
401 #define CONFIG_SYS_FSL_SRDS_1
402 #define CONFIG_SYS_NUM_FMAN 1
403 #define CONFIG_SYS_NUM_FM1_DTSEC 4
404 #define CONFIG_SYS_NUM_FM1_10GEC 1
405 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
406 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
407 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
408 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
409 #define CONFIG_SYS_FM1_CLK 0
410 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
411 per rcw field value */
412 #define CONFIG_QBMAN_CLK_DIV 1
413 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
414 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
415 #define CONFIG_SYS_FSL_TBCLK_DIV 16
416 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
417 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
418 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
419 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
420 #define QE_MURAM_SIZE 0x6000UL
421 #define MAX_QE_RISC 1
422 #define QE_NUM_OF_SNUM 28
423 #define CONFIG_SYS_FSL_SFP_VER_3_0
425 #elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
427 #define CONFIG_SYS_PPC64 /* 64-bit core */
428 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
429 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
430 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
431 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
432 #define CONFIG_SYS_FSL_QMAN_V3
433 #define CONFIG_SYS_NUM_FMAN 1
434 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
435 #define CONFIG_SYS_FSL_SRDS_1
436 #define CONFIG_SYS_FSL_PCI_VER_3_X
437 #if defined(CONFIG_ARCH_T2080)
438 #define CONFIG_SYS_NUM_FM1_DTSEC 8
439 #define CONFIG_SYS_NUM_FM1_10GEC 4
440 #define CONFIG_SYS_FSL_SRDS_2
441 #define CONFIG_SYS_FSL_SRIO_LIODN
442 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
443 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
444 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
445 #elif defined(CONFIG_ARCH_T2081)
446 #define CONFIG_SYS_NUM_FM1_DTSEC 6
447 #define CONFIG_SYS_NUM_FM1_10GEC 2
449 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
450 #define CONFIG_PME_PLAT_CLK_DIV 1
451 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
452 #define CONFIG_SYS_FM1_CLK 0
453 #define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2
454 per rcw field value */
455 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
456 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
457 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
458 #define CONFIG_SYS_FMAN_V3
459 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
460 #define CONFIG_SYS_FSL_TBCLK_DIV 16
461 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
462 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
463 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
464 #define CONFIG_SYS_FSL_SFP_VER_3_0
465 #define CONFIG_SYS_FSL_ISBC_VER 2
466 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
467 #define CONFIG_SYS_FSL_SFP_VER_3_0
470 #elif defined(CONFIG_ARCH_C29X)
471 #define CONFIG_FSL_SDHC_V2_3
472 #define CONFIG_TSECV2_1
473 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
474 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
475 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
476 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
478 #elif defined(CONFIG_ARCH_QEMU_E500)
481 #error Processor type not defined for this platform
485 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2
487 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1
490 #if !defined(CONFIG_ARCH_C29X)
491 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
494 #endif /* _ASM_MPC85xx_CONFIG_H_ */