2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _ASM_MPC85xx_CONFIG_H_
8 #define _ASM_MPC85xx_CONFIG_H_
10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
13 * This macro should be removed when we no longer care about backwards
14 * compatibility with older operating systems.
16 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
18 #include <fsl_ddrc_version.h>
21 #define CONFIG_SYS_FSL_IFC_BE
22 #define CONFIG_SYS_FSL_SFP_BE
23 #define CONFIG_SYS_FSL_SEC_MON_BE
25 #if defined(CONFIG_ARCH_MPC8536)
27 #elif defined(CONFIG_ARCH_MPC8540)
29 #elif defined(CONFIG_ARCH_MPC8541)
31 #elif defined(CONFIG_ARCH_MPC8544)
33 #elif defined(CONFIG_ARCH_MPC8548)
34 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
35 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
36 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
37 #define CONFIG_SYS_FSL_RMU
38 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
40 #elif defined(CONFIG_ARCH_MPC8555)
42 #elif defined(CONFIG_ARCH_MPC8560)
44 #elif defined(CONFIG_ARCH_MPC8568)
45 #define QE_MURAM_SIZE 0x10000UL
47 #define QE_NUM_OF_SNUM 28
48 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
49 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
50 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
51 #define CONFIG_SYS_FSL_RMU
52 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
54 #elif defined(CONFIG_ARCH_MPC8569)
55 #define QE_MURAM_SIZE 0x20000UL
57 #define QE_NUM_OF_SNUM 46
58 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
59 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
60 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
61 #define CONFIG_SYS_FSL_RMU
62 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
64 #elif defined(CONFIG_ARCH_MPC8572)
66 #elif defined(CONFIG_ARCH_P1010)
67 #define CONFIG_FSL_SDHC_V2_3
69 #define CONFIG_NUM_DDR_CONTROLLERS 1
70 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
71 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
72 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
73 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
74 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
75 #define CONFIG_ESDHC_HC_BLK_ADDR
77 /* P1011 is single core version of P1020 */
78 #elif defined(CONFIG_ARCH_P1011)
80 #define CONFIG_FSL_PCIE_DISABLE_ASPM
81 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
83 #elif defined(CONFIG_ARCH_P1020)
85 #define CONFIG_FSL_PCIE_DISABLE_ASPM
86 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
87 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
90 #elif defined(CONFIG_ARCH_P1021)
92 #define CONFIG_FSL_PCIE_DISABLE_ASPM
93 #define QE_MURAM_SIZE 0x6000UL
95 #define QE_NUM_OF_SNUM 28
96 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
98 #elif defined(CONFIG_ARCH_P1022)
100 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
102 #elif defined(CONFIG_ARCH_P1023)
103 #define CONFIG_SYS_NUM_FMAN 1
104 #define CONFIG_SYS_NUM_FM1_DTSEC 2
105 #define CONFIG_NUM_DDR_CONTROLLERS 1
106 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
107 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
108 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
109 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
110 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
112 /* P1024 is lower end variant of P1020 */
113 #elif defined(CONFIG_ARCH_P1024)
114 #define CONFIG_TSECV2
115 #define CONFIG_FSL_PCIE_DISABLE_ASPM
116 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
118 /* P1025 is lower end variant of P1021 */
119 #elif defined(CONFIG_ARCH_P1025)
120 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
121 #define CONFIG_TSECV2
122 #define CONFIG_FSL_PCIE_DISABLE_ASPM
123 #define QE_MURAM_SIZE 0x6000UL
124 #define MAX_QE_RISC 1
125 #define QE_NUM_OF_SNUM 28
127 #elif defined(CONFIG_ARCH_P2020)
128 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
129 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
130 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
131 #define CONFIG_SYS_FSL_RMU
132 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
133 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
135 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
136 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
137 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
138 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
139 #define CONFIG_SYS_NUM_FMAN 1
140 #define CONFIG_SYS_NUM_FM1_DTSEC 5
141 #define CONFIG_SYS_NUM_FM1_10GEC 1
142 #define CONFIG_NUM_DDR_CONTROLLERS 1
143 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
144 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
145 #define CONFIG_SYS_FSL_TBCLK_DIV 32
146 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
147 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
148 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
149 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
150 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
151 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
152 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
153 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
155 #elif defined(CONFIG_ARCH_P3041)
156 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
157 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
158 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
159 #define CONFIG_SYS_NUM_FMAN 1
160 #define CONFIG_SYS_NUM_FM1_DTSEC 5
161 #define CONFIG_SYS_NUM_FM1_10GEC 1
162 #define CONFIG_NUM_DDR_CONTROLLERS 1
163 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5
164 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
165 #define CONFIG_SYS_FSL_TBCLK_DIV 32
166 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
167 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
168 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
169 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
170 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
171 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
172 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
173 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
174 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
176 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
177 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
178 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
179 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
180 #define CONFIG_SYS_NUM_FMAN 2
181 #define CONFIG_SYS_NUM_FM1_DTSEC 4
182 #define CONFIG_SYS_NUM_FM2_DTSEC 4
183 #define CONFIG_SYS_NUM_FM1_10GEC 1
184 #define CONFIG_SYS_NUM_FM2_10GEC 1
185 #define CONFIG_NUM_DDR_CONTROLLERS 2
186 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
187 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
188 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
189 #define CONFIG_SYS_FSL_TBCLK_DIV 16
190 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
191 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
192 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
193 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
194 #define CONFIG_SYS_FSL_RMU
195 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
196 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
198 #elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */
199 #define CONFIG_SYS_PPC64 /* 64-bit core */
200 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
201 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
202 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
203 #define CONFIG_SYS_NUM_FMAN 1
204 #define CONFIG_SYS_NUM_FM1_DTSEC 5
205 #define CONFIG_SYS_NUM_FM1_10GEC 1
206 #define CONFIG_NUM_DDR_CONTROLLERS 2
207 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
208 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
209 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
210 #define CONFIG_SYS_FSL_TBCLK_DIV 32
211 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
212 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
213 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
214 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
215 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
216 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
217 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
218 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
220 #elif defined(CONFIG_ARCH_P5040)
221 #define CONFIG_SYS_PPC64
222 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
223 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
224 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
225 #define CONFIG_SYS_NUM_FMAN 2
226 #define CONFIG_SYS_NUM_FM1_DTSEC 5
227 #define CONFIG_SYS_NUM_FM1_10GEC 1
228 #define CONFIG_SYS_NUM_FM2_DTSEC 5
229 #define CONFIG_SYS_NUM_FM2_10GEC 1
230 #define CONFIG_NUM_DDR_CONTROLLERS 2
231 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
232 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
233 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
234 #define CONFIG_SYS_FSL_TBCLK_DIV 16
235 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
236 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
237 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
238 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
239 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
241 #elif defined(CONFIG_ARCH_BSC9131)
242 #define CONFIG_FSL_SDHC_V2_3
243 #define CONFIG_TSECV2
244 #define CONFIG_NUM_DDR_CONTROLLERS 1
245 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
246 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
247 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
248 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
249 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
250 #define CONFIG_NAND_FSL_IFC
251 #define CONFIG_ESDHC_HC_BLK_ADDR
253 #elif defined(CONFIG_ARCH_BSC9132)
254 #define CONFIG_FSL_SDHC_V2_3
255 #define CONFIG_TSECV2
256 #define CONFIG_NUM_DDR_CONTROLLERS 2
257 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
258 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
259 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
260 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
261 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
262 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
263 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
264 #define CONFIG_NAND_FSL_IFC
265 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
266 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
267 #define CONFIG_ESDHC_HC_BLK_ADDR
269 #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
271 #define CONFIG_SYS_PPC64 /* 64-bit core */
272 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
273 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
274 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
275 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
276 #ifdef CONFIG_ARCH_T4240
277 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
278 #define CONFIG_SYS_NUM_FM1_DTSEC 8
279 #define CONFIG_SYS_NUM_FM1_10GEC 2
280 #define CONFIG_SYS_NUM_FM2_DTSEC 8
281 #define CONFIG_SYS_NUM_FM2_10GEC 2
282 #define CONFIG_NUM_DDR_CONTROLLERS 3
284 #define CONFIG_SYS_NUM_FM1_DTSEC 6
285 #define CONFIG_SYS_NUM_FM1_10GEC 1
286 #define CONFIG_SYS_NUM_FM2_DTSEC 8
287 #define CONFIG_SYS_NUM_FM2_10GEC 1
288 #define CONFIG_NUM_DDR_CONTROLLERS 2
289 #if defined(CONFIG_ARCH_T4160)
290 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
293 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
294 #define CONFIG_SYS_FSL_SRDS_1
295 #define CONFIG_SYS_FSL_SRDS_2
296 #define CONFIG_SYS_FSL_SRDS_3
297 #define CONFIG_SYS_FSL_SRDS_4
298 #define CONFIG_SYS_NUM_FMAN 2
299 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
300 #define CONFIG_SYS_PME_CLK 0
301 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
302 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
303 #define CONFIG_SYS_FMAN_V3
304 #define CONFIG_SYS_FM1_CLK 3
305 #define CONFIG_SYS_FM2_CLK 3
306 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
307 #define CONFIG_SYS_FSL_TBCLK_DIV 16
308 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
309 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
310 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
311 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
312 #define CONFIG_SYS_FSL_SRIO_LIODN
313 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
314 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
315 #define CONFIG_SYS_FSL_SFP_VER_3_0
316 #define CONFIG_SYS_FSL_PCI_VER_3_X
318 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
320 #define CONFIG_SYS_PPC64 /* 64-bit core */
321 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
322 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
323 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
324 #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
325 #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
326 #define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/
327 #define CONFIG_SYS_FSL_SRDS_1
328 #define CONFIG_SYS_FSL_SRDS_2
329 #define CONFIG_SYS_MAPLE
330 #define CONFIG_SYS_CPRI
331 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
332 #define CONFIG_SYS_NUM_FMAN 1
333 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
334 #define CONFIG_SYS_FM1_CLK 0
335 #define CONFIG_SYS_CPRI_CLK 3
336 #define CONFIG_SYS_ULB_CLK 4
337 #define CONFIG_SYS_ETVPE_CLK 1
338 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
339 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
340 #define CONFIG_SYS_FMAN_V3
341 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
342 #define CONFIG_SYS_FSL_TBCLK_DIV 16
343 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
344 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
345 #define CONFIG_SYS_FSL_SFP_VER_3_0
347 #ifdef CONFIG_ARCH_B4860
348 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
349 #define CONFIG_MAX_DSP_CPUS 12
350 #define CONFIG_NUM_DSP_CPUS 6
351 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
352 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
353 #define CONFIG_SYS_NUM_FM1_DTSEC 6
354 #define CONFIG_SYS_NUM_FM1_10GEC 2
355 #define CONFIG_NUM_DDR_CONTROLLERS 2
356 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
357 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
358 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
359 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
360 #define CONFIG_SYS_FSL_SRIO_LIODN
362 #define CONFIG_MAX_DSP_CPUS 2
363 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
364 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
365 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
366 #define CONFIG_SYS_NUM_FM1_DTSEC 4
367 #define CONFIG_SYS_NUM_FM1_10GEC 0
368 #define CONFIG_NUM_DDR_CONTROLLERS 1
371 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
373 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
374 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
375 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
376 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
377 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
378 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
379 #define CONFIG_SYS_FSL_SRDS_1
380 #define CONFIG_SYS_NUM_FMAN 1
381 #define CONFIG_SYS_NUM_FM1_DTSEC 5
382 #define CONFIG_NUM_DDR_CONTROLLERS 1
383 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
384 #define CONFIG_PME_PLAT_CLK_DIV 2
385 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
386 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
387 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
388 #define CONFIG_SYS_FMAN_V3
389 #define CONFIG_FM_PLAT_CLK_DIV 1
390 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
391 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
392 per rcw field value */
393 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
394 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
395 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
396 #define CONFIG_SYS_FSL_TBCLK_DIV 16
397 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
398 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
399 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
400 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
401 #define QE_MURAM_SIZE 0x6000UL
402 #define MAX_QE_RISC 1
403 #define QE_NUM_OF_SNUM 28
404 #define CONFIG_SYS_FSL_SFP_VER_3_0
406 #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
408 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
409 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
410 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
411 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
412 #define CONFIG_SYS_FMAN_V3
413 #define CONFIG_SYS_FSL_NUM_CC_PLL 2
414 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
415 #define CONFIG_SYS_FSL_SRDS_1
416 #define CONFIG_SYS_NUM_FMAN 1
417 #define CONFIG_SYS_NUM_FM1_DTSEC 4
418 #define CONFIG_SYS_NUM_FM1_10GEC 1
419 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
420 #define CONFIG_NUM_DDR_CONTROLLERS 1
421 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
422 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
423 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
424 #define CONFIG_SYS_FM1_CLK 0
425 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
426 per rcw field value */
427 #define CONFIG_QBMAN_CLK_DIV 1
428 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
429 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
430 #define CONFIG_SYS_FSL_TBCLK_DIV 16
431 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
432 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
433 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
434 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
435 #define QE_MURAM_SIZE 0x6000UL
436 #define MAX_QE_RISC 1
437 #define QE_NUM_OF_SNUM 28
438 #define CONFIG_SYS_FSL_SFP_VER_3_0
440 #elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
442 #define CONFIG_SYS_PPC64 /* 64-bit core */
443 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
444 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
445 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
446 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
447 #define CONFIG_SYS_FSL_QMAN_V3
448 #define CONFIG_SYS_NUM_FMAN 1
449 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
450 #define CONFIG_SYS_FSL_SRDS_1
451 #define CONFIG_SYS_FSL_PCI_VER_3_X
452 #if defined(CONFIG_ARCH_T2080)
453 #define CONFIG_SYS_NUM_FM1_DTSEC 8
454 #define CONFIG_SYS_NUM_FM1_10GEC 4
455 #define CONFIG_SYS_FSL_SRDS_2
456 #define CONFIG_SYS_FSL_SRIO_LIODN
457 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
458 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
459 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
460 #elif defined(CONFIG_ARCH_T2081)
461 #define CONFIG_SYS_NUM_FM1_DTSEC 6
462 #define CONFIG_SYS_NUM_FM1_10GEC 2
464 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
465 #define CONFIG_NUM_DDR_CONTROLLERS 1
466 #define CONFIG_PME_PLAT_CLK_DIV 1
467 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
468 #define CONFIG_SYS_FM1_CLK 0
469 #define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2
470 per rcw field value */
471 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
472 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
473 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
474 #define CONFIG_SYS_FMAN_V3
475 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
476 #define CONFIG_SYS_FSL_TBCLK_DIV 16
477 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
478 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
479 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
480 #define CONFIG_SYS_FSL_SFP_VER_3_0
481 #define CONFIG_SYS_FSL_ISBC_VER 2
482 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
483 #define CONFIG_SYS_FSL_SFP_VER_3_0
486 #elif defined(CONFIG_ARCH_C29X)
487 #define CONFIG_FSL_SDHC_V2_3
488 #define CONFIG_TSECV2_1
489 #define CONFIG_NUM_DDR_CONTROLLERS 1
490 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
491 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
492 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
493 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
495 #elif defined(CONFIG_ARCH_QEMU_E500)
498 #error Processor type not defined for this platform
502 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2
504 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1
507 #if !defined(CONFIG_ARCH_C29X)
508 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
511 #endif /* _ASM_MPC85xx_CONFIG_H_ */