1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
6 #ifndef _ASM_MPC85xx_CONFIG_H_
7 #define _ASM_MPC85xx_CONFIG_H_
9 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
12 * This macro should be removed when we no longer care about backwards
13 * compatibility with older operating systems.
15 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
17 #include <fsl_ddrc_version.h>
20 #define CONFIG_SYS_FSL_IFC_BE
21 #define CONFIG_SYS_FSL_SFP_BE
22 #define CONFIG_SYS_FSL_SEC_MON_BE
24 #if defined(CONFIG_ARCH_MPC8548)
25 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
26 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
27 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
28 #define CONFIG_SYS_FSL_RMU
29 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
31 #elif defined(CONFIG_ARCH_MPC8568)
32 #define QE_MURAM_SIZE 0x10000UL
34 #define QE_NUM_OF_SNUM 28
35 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
36 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
37 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
38 #define CONFIG_SYS_FSL_RMU
39 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
41 #elif defined(CONFIG_ARCH_P1010)
42 #define CONFIG_FSL_SDHC_V2_3
44 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
45 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
46 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
47 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
48 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
49 #define CONFIG_ESDHC_HC_BLK_ADDR
51 /* P1011 is single core version of P1020 */
52 #elif defined(CONFIG_ARCH_P1011)
54 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
56 #elif defined(CONFIG_ARCH_P1020)
58 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
59 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
62 #elif defined(CONFIG_ARCH_P1021)
64 #define QE_MURAM_SIZE 0x6000UL
66 #define QE_NUM_OF_SNUM 28
67 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
69 #elif defined(CONFIG_ARCH_P1023)
70 #define CONFIG_SYS_NUM_FMAN 1
71 #define CONFIG_SYS_NUM_FM1_DTSEC 2
72 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
73 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
74 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
75 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
76 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
78 /* P1024 is lower end variant of P1020 */
79 #elif defined(CONFIG_ARCH_P1024)
81 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
83 /* P1025 is lower end variant of P1021 */
84 #elif defined(CONFIG_ARCH_P1025)
85 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
87 #define QE_MURAM_SIZE 0x6000UL
89 #define QE_NUM_OF_SNUM 28
91 #elif defined(CONFIG_ARCH_P2020)
92 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
93 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
94 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
95 #define CONFIG_SYS_FSL_RMU
96 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
97 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
99 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
100 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
101 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
102 #define CONFIG_SYS_NUM_FMAN 1
103 #define CONFIG_SYS_NUM_FM1_DTSEC 5
104 #define CONFIG_SYS_NUM_FM1_10GEC 1
105 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
106 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
108 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
109 #define CONFIG_SYS_FSL_TBCLK_DIV 32
110 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
111 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
112 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
113 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
114 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
115 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
116 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
117 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
119 #elif defined(CONFIG_ARCH_P3041)
120 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
121 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
122 #define CONFIG_SYS_NUM_FMAN 1
123 #define CONFIG_SYS_NUM_FM1_DTSEC 5
124 #define CONFIG_SYS_NUM_FM1_10GEC 1
125 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
126 #define CONFIG_SYS_FSL_TBCLK_DIV 32
127 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
128 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
129 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
130 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
131 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
132 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
133 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
134 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
135 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
137 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
138 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
139 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
140 #define CONFIG_SYS_NUM_FMAN 2
141 #define CONFIG_SYS_NUM_FM1_DTSEC 4
142 #define CONFIG_SYS_NUM_FM2_DTSEC 4
143 #define CONFIG_SYS_NUM_FM1_10GEC 1
144 #define CONFIG_SYS_NUM_FM2_10GEC 1
145 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
146 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
147 #define CONFIG_SYS_FSL_TBCLK_DIV 16
148 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
149 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
150 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
151 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
152 #define CONFIG_SYS_FSL_RMU
153 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
154 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
156 #elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */
157 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
158 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
159 #define CONFIG_SYS_NUM_FMAN 1
160 #define CONFIG_SYS_NUM_FM1_DTSEC 5
161 #define CONFIG_SYS_NUM_FM1_10GEC 1
162 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
163 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
164 #define CONFIG_SYS_FSL_TBCLK_DIV 32
165 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
166 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
167 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
168 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
169 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
170 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
171 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
172 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
174 #elif defined(CONFIG_ARCH_P5040)
175 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
176 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
177 #define CONFIG_SYS_NUM_FMAN 2
178 #define CONFIG_SYS_NUM_FM1_DTSEC 5
179 #define CONFIG_SYS_NUM_FM1_10GEC 1
180 #define CONFIG_SYS_NUM_FM2_DTSEC 5
181 #define CONFIG_SYS_NUM_FM2_10GEC 1
182 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
183 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
184 #define CONFIG_SYS_FSL_TBCLK_DIV 16
185 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
186 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
187 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
188 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
189 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
191 #elif defined(CONFIG_ARCH_BSC9131)
192 #define CONFIG_FSL_SDHC_V2_3
193 #define CONFIG_TSECV2
194 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
195 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
196 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
197 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
198 #define CONFIG_NAND_FSL_IFC
199 #define CONFIG_ESDHC_HC_BLK_ADDR
201 #elif defined(CONFIG_ARCH_BSC9132)
202 #define CONFIG_FSL_SDHC_V2_3
203 #define CONFIG_TSECV2
204 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
205 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
206 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
207 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
208 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
209 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
210 #define CONFIG_NAND_FSL_IFC
211 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
212 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
213 #define CONFIG_ESDHC_HC_BLK_ADDR
215 #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
216 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
217 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
218 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
219 #ifdef CONFIG_ARCH_T4240
220 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
221 #define CONFIG_SYS_NUM_FM1_DTSEC 8
222 #define CONFIG_SYS_NUM_FM1_10GEC 2
223 #define CONFIG_SYS_NUM_FM2_DTSEC 8
224 #define CONFIG_SYS_NUM_FM2_10GEC 2
226 #define CONFIG_SYS_NUM_FM1_DTSEC 6
227 #define CONFIG_SYS_NUM_FM1_10GEC 1
228 #define CONFIG_SYS_NUM_FM2_DTSEC 8
229 #define CONFIG_SYS_NUM_FM2_10GEC 1
230 #if defined(CONFIG_ARCH_T4160)
231 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
234 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
235 #define CONFIG_SYS_FSL_SRDS_1
236 #define CONFIG_SYS_FSL_SRDS_2
237 #define CONFIG_SYS_FSL_SRDS_3
238 #define CONFIG_SYS_FSL_SRDS_4
239 #define CONFIG_SYS_NUM_FMAN 2
240 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
241 #define CONFIG_SYS_PME_CLK 0
242 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
243 #define CONFIG_SYS_FMAN_V3
244 #define CONFIG_SYS_FM1_CLK 3
245 #define CONFIG_SYS_FM2_CLK 3
246 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
247 #define CONFIG_SYS_FSL_TBCLK_DIV 16
248 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
249 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
250 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
251 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
252 #define CONFIG_SYS_FSL_SRIO_LIODN
253 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
254 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
255 #define CONFIG_SYS_FSL_SFP_VER_3_0
256 #define CONFIG_SYS_FSL_PCI_VER_3_X
258 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
259 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
260 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
261 #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
262 #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
263 #define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/
264 #define CONFIG_SYS_FSL_SRDS_1
265 #define CONFIG_SYS_FSL_SRDS_2
266 #define CONFIG_SYS_MAPLE
267 #define CONFIG_SYS_CPRI
268 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
269 #define CONFIG_SYS_NUM_FMAN 1
270 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
271 #define CONFIG_SYS_FM1_CLK 0
272 #define CONFIG_SYS_CPRI_CLK 3
273 #define CONFIG_SYS_ULB_CLK 4
274 #define CONFIG_SYS_ETVPE_CLK 1
275 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
276 #define CONFIG_SYS_FMAN_V3
277 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
278 #define CONFIG_SYS_FSL_TBCLK_DIV 16
279 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
280 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
281 #define CONFIG_SYS_FSL_SFP_VER_3_0
283 #ifdef CONFIG_ARCH_B4860
284 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
285 #define CONFIG_MAX_DSP_CPUS 12
286 #define CONFIG_NUM_DSP_CPUS 6
287 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
288 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
289 #define CONFIG_SYS_NUM_FM1_DTSEC 6
290 #define CONFIG_SYS_NUM_FM1_10GEC 2
291 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
292 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
293 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
294 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
295 #define CONFIG_SYS_FSL_SRIO_LIODN
297 #define CONFIG_MAX_DSP_CPUS 2
298 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
299 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
300 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
301 #define CONFIG_SYS_NUM_FM1_DTSEC 4
302 #define CONFIG_SYS_NUM_FM1_10GEC 0
305 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
307 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
308 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
309 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
310 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
311 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
312 #define CONFIG_SYS_FSL_SRDS_1
313 #define CONFIG_SYS_NUM_FMAN 1
314 #define CONFIG_SYS_NUM_FM1_DTSEC 5
315 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
316 #define CONFIG_PME_PLAT_CLK_DIV 2
317 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
318 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
319 #define CONFIG_SYS_FMAN_V3
320 #define CONFIG_FM_PLAT_CLK_DIV 1
321 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
322 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
323 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
324 #define CONFIG_SYS_FSL_TBCLK_DIV 16
325 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
326 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
327 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
328 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
329 #define QE_MURAM_SIZE 0x6000UL
330 #define MAX_QE_RISC 1
331 #define QE_NUM_OF_SNUM 28
332 #define CONFIG_SYS_FSL_SFP_VER_3_0
334 #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
336 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
337 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
338 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
339 #define CONFIG_SYS_FMAN_V3
340 #define CONFIG_SYS_FSL_NUM_CC_PLL 2
341 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
342 #define CONFIG_SYS_FSL_SRDS_1
343 #define CONFIG_SYS_NUM_FMAN 1
344 #define CONFIG_SYS_NUM_FM1_DTSEC 4
345 #define CONFIG_SYS_NUM_FM1_10GEC 1
346 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
347 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
348 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
349 #define CONFIG_SYS_FM1_CLK 0
350 #define CONFIG_QBMAN_CLK_DIV 1
351 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
352 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
353 #define CONFIG_SYS_FSL_TBCLK_DIV 16
354 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
355 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
356 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
357 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
358 #define QE_MURAM_SIZE 0x6000UL
359 #define MAX_QE_RISC 1
360 #define QE_NUM_OF_SNUM 28
361 #define CONFIG_SYS_FSL_SFP_VER_3_0
363 #elif defined(CONFIG_ARCH_T2080)
364 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
365 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
366 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
367 #define CONFIG_SYS_FSL_QMAN_V3
368 #define CONFIG_SYS_NUM_FMAN 1
369 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
370 #define CONFIG_SYS_FSL_SRDS_1
371 #define CONFIG_SYS_FSL_PCI_VER_3_X
372 #if defined(CONFIG_ARCH_T2080)
373 #define CONFIG_SYS_NUM_FM1_DTSEC 8
374 #define CONFIG_SYS_NUM_FM1_10GEC 4
375 #define CONFIG_SYS_FSL_SRDS_2
376 #define CONFIG_SYS_FSL_SRIO_LIODN
377 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
378 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
379 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
381 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
382 #define CONFIG_PME_PLAT_CLK_DIV 1
383 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
384 #define CONFIG_SYS_FM1_CLK 0
385 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
386 #define CONFIG_SYS_FMAN_V3
387 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
388 #define CONFIG_SYS_FSL_TBCLK_DIV 16
389 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
390 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
391 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
392 #define CONFIG_SYS_FSL_SFP_VER_3_0
393 #define CONFIG_SYS_FSL_ISBC_VER 2
394 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
395 #define CONFIG_SYS_FSL_SFP_VER_3_0
398 #elif defined(CONFIG_ARCH_C29X)
399 #define CONFIG_FSL_SDHC_V2_3
400 #define CONFIG_TSECV2_1
401 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
402 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
403 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
407 #if !defined(CONFIG_ARCH_C29X)
408 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
411 #endif /* _ASM_MPC85xx_CONFIG_H_ */