2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _ASM_MPC85xx_CONFIG_H_
8 #define _ASM_MPC85xx_CONFIG_H_
10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
12 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT
13 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
17 * This macro should be removed when we no longer care about backwards
18 * compatibility with older operating systems.
20 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
22 #include <fsl_ddrc_version.h>
23 #define CONFIG_SYS_FSL_DDR_BE
26 #define CONFIG_SYS_FSL_IFC_BE
27 #define CONFIG_SYS_FSL_SEC_BE
28 #define CONFIG_SYS_FSL_SFP_BE
29 #define CONFIG_SYS_FSL_SEC_MON_BE
31 /* Number of TLB CAM entries we have on FSL Book-E chips */
32 #if defined(CONFIG_E500MC)
33 #define CONFIG_SYS_NUM_TLBCAMS 64
34 #elif defined(CONFIG_E500)
35 #define CONFIG_SYS_NUM_TLBCAMS 16
38 #if defined(CONFIG_ARCH_MPC8536)
39 #define CONFIG_MAX_CPUS 1
40 #define CONFIG_SYS_FSL_NUM_LAWS 12
41 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
42 #define CONFIG_SYS_FSL_SEC_COMPAT 2
43 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
44 #define CONFIG_SYS_FSL_ERRATUM_A004508
45 #define CONFIG_SYS_FSL_ERRATUM_A005125
47 #elif defined(CONFIG_ARCH_MPC8540)
48 #define CONFIG_MAX_CPUS 1
49 #define CONFIG_SYS_FSL_NUM_LAWS 8
50 #define CONFIG_SYS_FSL_DDRC_GEN1
51 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
53 #elif defined(CONFIG_ARCH_MPC8541)
54 #define CONFIG_MAX_CPUS 1
55 #define CONFIG_SYS_FSL_NUM_LAWS 8
56 #define CONFIG_SYS_FSL_DDRC_GEN1
57 #define CONFIG_SYS_FSL_SEC_COMPAT 2
58 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
60 #elif defined(CONFIG_ARCH_MPC8544)
61 #define CONFIG_MAX_CPUS 1
62 #define CONFIG_SYS_FSL_NUM_LAWS 10
63 #define CONFIG_SYS_FSL_DDRC_GEN2
64 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
65 #define CONFIG_SYS_FSL_SEC_COMPAT 2
66 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
67 #define CONFIG_SYS_FSL_ERRATUM_A005125
69 #elif defined(CONFIG_ARCH_MPC8548)
70 #define CONFIG_MAX_CPUS 1
71 #define CONFIG_SYS_FSL_NUM_LAWS 10
72 #define CONFIG_SYS_FSL_DDRC_GEN2
73 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
74 #define CONFIG_SYS_FSL_SEC_COMPAT 2
75 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
76 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
77 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
78 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
79 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
80 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
81 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
82 #define CONFIG_SYS_FSL_RMU
83 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
84 #define CONFIG_SYS_FSL_ERRATUM_A005125
85 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
86 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
88 #elif defined(CONFIG_ARCH_MPC8555)
89 #define CONFIG_MAX_CPUS 1
90 #define CONFIG_SYS_FSL_NUM_LAWS 8
91 #define CONFIG_SYS_FSL_DDRC_GEN1
92 #define CONFIG_SYS_FSL_SEC_COMPAT 2
93 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
95 #elif defined(CONFIG_ARCH_MPC8560)
96 #define CONFIG_MAX_CPUS 1
97 #define CONFIG_SYS_FSL_NUM_LAWS 8
98 #define CONFIG_SYS_FSL_DDRC_GEN1
99 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
101 #elif defined(CONFIG_ARCH_MPC8568)
102 #define CONFIG_MAX_CPUS 1
103 #define CONFIG_SYS_FSL_NUM_LAWS 10
104 #define CONFIG_SYS_FSL_DDRC_GEN2
105 #define CONFIG_SYS_FSL_SEC_COMPAT 2
106 #define QE_MURAM_SIZE 0x10000UL
107 #define MAX_QE_RISC 2
108 #define QE_NUM_OF_SNUM 28
109 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
110 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
111 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
112 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
113 #define CONFIG_SYS_FSL_RMU
114 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
116 #elif defined(CONFIG_ARCH_MPC8569)
117 #define CONFIG_MAX_CPUS 1
118 #define CONFIG_SYS_FSL_NUM_LAWS 10
119 #define CONFIG_SYS_FSL_SEC_COMPAT 2
120 #define QE_MURAM_SIZE 0x20000UL
121 #define MAX_QE_RISC 4
122 #define QE_NUM_OF_SNUM 46
123 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
124 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
125 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
126 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
127 #define CONFIG_SYS_FSL_RMU
128 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
129 #define CONFIG_SYS_FSL_ERRATUM_A004508
130 #define CONFIG_SYS_FSL_ERRATUM_A005125
132 #elif defined(CONFIG_ARCH_MPC8572)
133 #define CONFIG_MAX_CPUS 2
134 #define CONFIG_SYS_FSL_NUM_LAWS 12
135 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
136 #define CONFIG_SYS_FSL_SEC_COMPAT 2
137 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
138 #define CONFIG_SYS_FSL_ERRATUM_DDR_115
139 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
140 #define CONFIG_SYS_FSL_ERRATUM_A004508
141 #define CONFIG_SYS_FSL_ERRATUM_A005125
143 #elif defined(CONFIG_ARCH_P1010)
144 #define CONFIG_MAX_CPUS 1
145 #define CONFIG_FSL_SDHC_V2_3
146 #define CONFIG_SYS_FSL_NUM_LAWS 12
147 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
148 #define CONFIG_TSECV2
149 #define CONFIG_SYS_FSL_SEC_COMPAT 4
150 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
151 #define CONFIG_NUM_DDR_CONTROLLERS 1
152 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
153 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
154 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
155 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
156 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
157 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
158 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
159 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
160 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
161 #define CONFIG_SYS_FSL_ERRATUM_A005125
162 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
163 #define CONFIG_SYS_FSL_ERRATUM_A004508
164 #define CONFIG_SYS_FSL_ERRATUM_A007075
165 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
166 #define CONFIG_SYS_FSL_ERRATUM_A006261
167 #define CONFIG_SYS_FSL_ERRATUM_A004477
168 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
169 #define CONFIG_ESDHC_HC_BLK_ADDR
171 /* P1011 is single core version of P1020 */
172 #elif defined(CONFIG_ARCH_P1011)
173 #define CONFIG_MAX_CPUS 1
174 #define CONFIG_SYS_FSL_NUM_LAWS 12
175 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
176 #define CONFIG_TSECV2
177 #define CONFIG_FSL_PCIE_DISABLE_ASPM
178 #define CONFIG_SYS_FSL_SEC_COMPAT 2
179 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
180 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
181 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
182 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
183 #define CONFIG_SYS_FSL_ERRATUM_A004508
184 #define CONFIG_SYS_FSL_ERRATUM_A005125
186 #elif defined(CONFIG_P1014)
187 #define CONFIG_MAX_CPUS 1
188 #define CONFIG_FSL_SDHC_V2_3
189 #define CONFIG_SYS_FSL_NUM_LAWS 12
190 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
191 #define CONFIG_TSECV2
192 #define CONFIG_SYS_FSL_SEC_COMPAT 4
193 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
194 #define CONFIG_NUM_DDR_CONTROLLERS 1
195 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
196 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
197 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
198 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
199 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
200 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
201 #define CONFIG_SYS_FSL_ERRATUM_A004508
203 /* P1017 is single core version of P1023 */
204 #elif defined(CONFIG_P1017)
205 #define CONFIG_MAX_CPUS 1
206 #define CONFIG_SYS_FSL_NUM_LAWS 12
207 #define CONFIG_SYS_FSL_SEC_COMPAT 4
208 #define CONFIG_SYS_NUM_FMAN 1
209 #define CONFIG_SYS_NUM_FM1_DTSEC 2
210 #define CONFIG_NUM_DDR_CONTROLLERS 1
211 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
212 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
213 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
214 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
215 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
216 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
217 #define CONFIG_SYS_FSL_ERRATUM_A004508
218 #define CONFIG_SYS_FSL_ERRATUM_A005125
220 #elif defined(CONFIG_P1020)
221 #define CONFIG_MAX_CPUS 2
222 #define CONFIG_SYS_FSL_NUM_LAWS 12
223 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
224 #define CONFIG_TSECV2
225 #define CONFIG_FSL_PCIE_DISABLE_ASPM
226 #define CONFIG_SYS_FSL_SEC_COMPAT 2
227 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
228 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
229 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
230 #define CONFIG_SYS_FSL_ERRATUM_A004508
231 #define CONFIG_SYS_FSL_ERRATUM_A005125
232 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
233 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
236 #elif defined(CONFIG_P1021)
237 #define CONFIG_MAX_CPUS 2
238 #define CONFIG_SYS_FSL_NUM_LAWS 12
239 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
240 #define CONFIG_TSECV2
241 #define CONFIG_FSL_PCIE_DISABLE_ASPM
242 #define CONFIG_SYS_FSL_SEC_COMPAT 2
243 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
244 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
245 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
246 #define QE_MURAM_SIZE 0x6000UL
247 #define MAX_QE_RISC 1
248 #define QE_NUM_OF_SNUM 28
249 #define CONFIG_SYS_FSL_ERRATUM_A004508
250 #define CONFIG_SYS_FSL_ERRATUM_A005125
251 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
253 #elif defined(CONFIG_ARCH_P1022)
254 #define CONFIG_MAX_CPUS 2
255 #define CONFIG_SYS_FSL_NUM_LAWS 12
256 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
257 #define CONFIG_TSECV2
258 #define CONFIG_SYS_FSL_SEC_COMPAT 2
259 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
260 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
261 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
262 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
263 #define CONFIG_FSL_SATA_ERRATUM_A001
264 #define CONFIG_SYS_FSL_ERRATUM_A004508
265 #define CONFIG_SYS_FSL_ERRATUM_A005125
266 #define CONFIG_SYS_FSL_ERRATUM_A004477
268 #elif defined(CONFIG_ARCH_P1023)
269 #define CONFIG_MAX_CPUS 2
270 #define CONFIG_SYS_FSL_NUM_LAWS 12
271 #define CONFIG_SYS_FSL_SEC_COMPAT 4
272 #define CONFIG_SYS_NUM_FMAN 1
273 #define CONFIG_SYS_NUM_FM1_DTSEC 2
274 #define CONFIG_NUM_DDR_CONTROLLERS 1
275 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
276 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
277 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
278 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
279 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
280 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
281 #define CONFIG_SYS_FSL_ERRATUM_A004508
282 #define CONFIG_SYS_FSL_ERRATUM_A005125
283 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
284 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
286 /* P1024 is lower end variant of P1020 */
287 #elif defined(CONFIG_P1024)
288 #define CONFIG_MAX_CPUS 2
289 #define CONFIG_SYS_FSL_NUM_LAWS 12
290 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
291 #define CONFIG_TSECV2
292 #define CONFIG_FSL_PCIE_DISABLE_ASPM
293 #define CONFIG_SYS_FSL_SEC_COMPAT 2
294 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
295 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
296 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
297 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
298 #define CONFIG_SYS_FSL_ERRATUM_A004508
299 #define CONFIG_SYS_FSL_ERRATUM_A005125
301 /* P1025 is lower end variant of P1021 */
302 #elif defined(CONFIG_P1025)
303 #define CONFIG_MAX_CPUS 2
304 #define CONFIG_SYS_FSL_NUM_LAWS 12
305 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
306 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
307 #define CONFIG_TSECV2
308 #define CONFIG_FSL_PCIE_DISABLE_ASPM
309 #define CONFIG_SYS_FSL_SEC_COMPAT 2
310 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
311 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
312 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
313 #define QE_MURAM_SIZE 0x6000UL
314 #define MAX_QE_RISC 1
315 #define QE_NUM_OF_SNUM 28
316 #define CONFIG_SYS_FSL_ERRATUM_A004508
317 #define CONFIG_SYS_FSL_ERRATUM_A005125
319 /* P2010 is single core version of P2020 */
320 #elif defined(CONFIG_P2010)
321 #define CONFIG_MAX_CPUS 1
322 #define CONFIG_SYS_FSL_NUM_LAWS 12
323 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
324 #define CONFIG_SYS_FSL_SEC_COMPAT 2
325 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
326 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
327 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
328 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
329 #define CONFIG_SYS_FSL_ERRATUM_A004508
330 #define CONFIG_SYS_FSL_ERRATUM_A005125
332 #elif defined(CONFIG_P2020)
333 #define CONFIG_MAX_CPUS 2
334 #define CONFIG_SYS_FSL_NUM_LAWS 12
335 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
336 #define CONFIG_SYS_FSL_SEC_COMPAT 2
337 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
338 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
339 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
340 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
341 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
342 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
343 #define CONFIG_SYS_FSL_RMU
344 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
345 #define CONFIG_SYS_FSL_ERRATUM_A004508
346 #define CONFIG_SYS_FSL_ERRATUM_A005125
347 #define CONFIG_SYS_FSL_ERRATUM_A004477
348 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
350 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
351 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
352 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
353 #define CONFIG_MAX_CPUS 4
354 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
355 #define CONFIG_SYS_FSL_NUM_LAWS 32
356 #define CONFIG_SYS_FSL_SEC_COMPAT 4
357 #define CONFIG_SYS_NUM_FMAN 1
358 #define CONFIG_SYS_NUM_FM1_DTSEC 5
359 #define CONFIG_SYS_NUM_FM1_10GEC 1
360 #define CONFIG_NUM_DDR_CONTROLLERS 1
361 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
362 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
363 #define CONFIG_SYS_FSL_TBCLK_DIV 32
364 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
365 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
366 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
367 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
368 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
369 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
370 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
371 #define CONFIG_SYS_FSL_ERRATUM_USB14
372 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
373 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
374 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
375 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
376 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
377 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
378 #define CONFIG_SYS_FSL_ERRATUM_A004510
379 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
380 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
381 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
382 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
383 #define CONFIG_SYS_FSL_ERRATUM_A004849
384 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
385 #define CONFIG_SYS_FSL_ERRATUM_A006261
386 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
388 #elif defined(CONFIG_PPC_P3041)
389 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
390 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
391 #define CONFIG_MAX_CPUS 4
392 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
393 #define CONFIG_SYS_FSL_NUM_LAWS 32
394 #define CONFIG_SYS_FSL_SEC_COMPAT 4
395 #define CONFIG_SYS_NUM_FMAN 1
396 #define CONFIG_SYS_NUM_FM1_DTSEC 5
397 #define CONFIG_SYS_NUM_FM1_10GEC 1
398 #define CONFIG_NUM_DDR_CONTROLLERS 1
399 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5
400 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
401 #define CONFIG_SYS_FSL_TBCLK_DIV 32
402 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
403 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
404 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
405 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
406 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
407 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
408 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
409 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
410 #define CONFIG_SYS_FSL_ERRATUM_USB14
411 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
412 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
413 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
414 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
415 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
416 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
417 #define CONFIG_SYS_FSL_ERRATUM_A004510
418 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
419 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
420 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
421 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
422 #define CONFIG_SYS_FSL_ERRATUM_A004849
423 #define CONFIG_SYS_FSL_ERRATUM_A005812
424 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
425 #define CONFIG_SYS_FSL_ERRATUM_A006261
426 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
428 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
429 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
430 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
431 #define CONFIG_MAX_CPUS 8
432 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
433 #define CONFIG_SYS_FSL_NUM_LAWS 32
434 #define CONFIG_SYS_FSL_SEC_COMPAT 4
435 #define CONFIG_SYS_NUM_FMAN 2
436 #define CONFIG_SYS_NUM_FM1_DTSEC 4
437 #define CONFIG_SYS_NUM_FM2_DTSEC 4
438 #define CONFIG_SYS_NUM_FM1_10GEC 1
439 #define CONFIG_SYS_NUM_FM2_10GEC 1
440 #define CONFIG_NUM_DDR_CONTROLLERS 2
441 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
442 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
443 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
444 #define CONFIG_SYS_FSL_TBCLK_DIV 16
445 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
446 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
447 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
448 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
449 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
450 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
451 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
452 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
453 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13
454 #define CONFIG_SYS_P4080_ERRATUM_CPU22
455 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
456 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
457 #define CONFIG_SYS_P4080_ERRATUM_SERDES9
458 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
459 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
460 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
461 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
462 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
463 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
464 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
465 #define CONFIG_SYS_FSL_RMU
466 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
467 #define CONFIG_SYS_FSL_ERRATUM_A004510
468 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
469 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
470 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
471 #define CONFIG_SYS_FSL_ERRATUM_A004849
472 #define CONFIG_SYS_FSL_ERRATUM_A004580
473 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
474 #define CONFIG_SYS_FSL_ERRATUM_A005812
475 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
476 #define CONFIG_SYS_FSL_ERRATUM_A007075
477 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
479 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
480 #define CONFIG_SYS_PPC64 /* 64-bit core */
481 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
482 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
483 #define CONFIG_MAX_CPUS 2
484 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
485 #define CONFIG_SYS_FSL_NUM_LAWS 32
486 #define CONFIG_SYS_FSL_SEC_COMPAT 4
487 #define CONFIG_SYS_NUM_FMAN 1
488 #define CONFIG_SYS_NUM_FM1_DTSEC 5
489 #define CONFIG_SYS_NUM_FM1_10GEC 1
490 #define CONFIG_NUM_DDR_CONTROLLERS 2
491 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
492 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
493 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
494 #define CONFIG_SYS_FSL_TBCLK_DIV 32
495 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
496 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
497 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
498 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
499 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
500 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
501 #define CONFIG_SYS_FSL_ERRATUM_USB14
502 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
503 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
504 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
505 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
506 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
507 #define CONFIG_SYS_FSL_ERRATUM_A004510
508 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
509 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
510 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
511 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
512 #define CONFIG_SYS_FSL_ERRATUM_A006261
513 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
515 #elif defined(CONFIG_PPC_P5040)
516 #define CONFIG_SYS_PPC64
517 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
518 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
519 #define CONFIG_MAX_CPUS 4
520 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
521 #define CONFIG_SYS_FSL_NUM_LAWS 32
522 #define CONFIG_SYS_FSL_SEC_COMPAT 4
523 #define CONFIG_SYS_NUM_FMAN 2
524 #define CONFIG_SYS_NUM_FM1_DTSEC 5
525 #define CONFIG_SYS_NUM_FM1_10GEC 1
526 #define CONFIG_SYS_NUM_FM2_DTSEC 5
527 #define CONFIG_SYS_NUM_FM2_10GEC 1
528 #define CONFIG_NUM_DDR_CONTROLLERS 2
529 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
530 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
531 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
532 #define CONFIG_SYS_FSL_TBCLK_DIV 16
533 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
534 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
535 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
536 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
537 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
538 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
539 #define CONFIG_SYS_FSL_ERRATUM_USB14
540 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
541 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
542 #define CONFIG_SYS_FSL_ERRATUM_A004699
543 #define CONFIG_SYS_FSL_ERRATUM_A004510
544 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
545 #define CONFIG_SYS_FSL_ERRATUM_A006261
546 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
547 #define CONFIG_SYS_FSL_ERRATUM_A005812
549 #elif defined(CONFIG_ARCH_BSC9131)
550 #define CONFIG_MAX_CPUS 1
551 #define CONFIG_FSL_SDHC_V2_3
552 #define CONFIG_SYS_FSL_NUM_LAWS 12
553 #define CONFIG_TSECV2
554 #define CONFIG_SYS_FSL_SEC_COMPAT 4
555 #define CONFIG_NUM_DDR_CONTROLLERS 1
556 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
557 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
558 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
559 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
560 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
561 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
562 #define CONFIG_NAND_FSL_IFC
563 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
564 #define CONFIG_SYS_FSL_ERRATUM_A005125
565 #define CONFIG_SYS_FSL_ERRATUM_A004477
566 #define CONFIG_ESDHC_HC_BLK_ADDR
568 #elif defined(CONFIG_ARCH_BSC9132)
569 #define CONFIG_MAX_CPUS 2
570 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
571 #define CONFIG_FSL_SDHC_V2_3
572 #define CONFIG_SYS_FSL_NUM_LAWS 12
573 #define CONFIG_TSECV2
574 #define CONFIG_SYS_FSL_SEC_COMPAT 4
575 #define CONFIG_NUM_DDR_CONTROLLERS 2
576 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
577 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
578 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
579 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
580 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
581 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
582 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
583 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
584 #define CONFIG_NAND_FSL_IFC
585 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
586 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
587 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
588 #define CONFIG_SYS_FSL_ERRATUM_A005125
589 #define CONFIG_SYS_FSL_ERRATUM_A005434
590 #define CONFIG_SYS_FSL_ERRATUM_A004477
591 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
592 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
593 #define CONFIG_ESDHC_HC_BLK_ADDR
595 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
596 defined(CONFIG_PPC_T4080)
598 #define CONFIG_SYS_PPC64 /* 64-bit core */
599 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
600 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
601 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
602 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
603 #ifdef CONFIG_PPC_T4240
604 #define CONFIG_MAX_CPUS 12
605 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
606 #define CONFIG_SYS_NUM_FM1_DTSEC 8
607 #define CONFIG_SYS_NUM_FM1_10GEC 2
608 #define CONFIG_SYS_NUM_FM2_DTSEC 8
609 #define CONFIG_SYS_NUM_FM2_10GEC 2
610 #define CONFIG_NUM_DDR_CONTROLLERS 3
611 #define CONFIG_SYS_FSL_ERRATUM_A006261
613 #define CONFIG_SYS_NUM_FM1_DTSEC 6
614 #define CONFIG_SYS_NUM_FM1_10GEC 1
615 #define CONFIG_SYS_NUM_FM2_DTSEC 8
616 #define CONFIG_SYS_NUM_FM2_10GEC 1
617 #define CONFIG_NUM_DDR_CONTROLLERS 2
618 #if defined(CONFIG_PPC_T4160)
619 #define CONFIG_MAX_CPUS 8
620 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
621 #elif defined(CONFIG_PPC_T4080)
622 #define CONFIG_MAX_CPUS 4
623 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 }
626 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
627 #define CONFIG_SYS_FSL_NUM_LAWS 32
628 #define CONFIG_SYS_FSL_SRDS_1
629 #define CONFIG_SYS_FSL_SRDS_2
630 #define CONFIG_SYS_FSL_SRDS_3
631 #define CONFIG_SYS_FSL_SRDS_4
632 #define CONFIG_SYS_FSL_SEC_COMPAT 4
633 #define CONFIG_SYS_NUM_FMAN 2
634 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
635 #define CONFIG_SYS_PME_CLK 0
636 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
637 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
638 #define CONFIG_SYS_FMAN_V3
639 #define CONFIG_SYS_FM1_CLK 3
640 #define CONFIG_SYS_FM2_CLK 3
641 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
642 #define CONFIG_SYS_FSL_TBCLK_DIV 16
643 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
644 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
645 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
646 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
647 #define CONFIG_SYS_FSL_SRIO_LIODN
648 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
649 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
650 #define CONFIG_SYS_FSL_ERRATUM_A004468
651 #define CONFIG_SYS_FSL_ERRATUM_A_004934
652 #define CONFIG_SYS_FSL_ERRATUM_A005871
653 #define CONFIG_SYS_FSL_ERRATUM_A006379
654 #define CONFIG_SYS_FSL_ERRATUM_A007186
655 #define CONFIG_SYS_FSL_ERRATUM_A006593
656 #define CONFIG_SYS_FSL_ERRATUM_A007798
657 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
658 #define CONFIG_SYS_FSL_SFP_VER_3_0
659 #define CONFIG_SYS_FSL_PCI_VER_3_X
661 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
663 #define CONFIG_SYS_PPC64 /* 64-bit core */
664 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
665 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
666 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
667 #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
668 #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
669 #define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/
670 #define CONFIG_SYS_FSL_NUM_LAWS 32
671 #define CONFIG_SYS_FSL_SRDS_1
672 #define CONFIG_SYS_FSL_SRDS_2
673 #define CONFIG_SYS_MAPLE
674 #define CONFIG_SYS_CPRI
675 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
676 #define CONFIG_SYS_FSL_SEC_COMPAT 4
677 #define CONFIG_SYS_NUM_FMAN 1
678 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
679 #define CONFIG_SYS_FM1_CLK 0
680 #define CONFIG_SYS_CPRI_CLK 3
681 #define CONFIG_SYS_ULB_CLK 4
682 #define CONFIG_SYS_ETVPE_CLK 1
683 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
684 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
685 #define CONFIG_SYS_FMAN_V3
686 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
687 #define CONFIG_SYS_FSL_TBCLK_DIV 16
688 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
689 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
690 #define CONFIG_SYS_FSL_ERRATUM_A_004934
691 #define CONFIG_SYS_FSL_ERRATUM_A005871
692 #define CONFIG_SYS_FSL_ERRATUM_A006379
693 #define CONFIG_SYS_FSL_ERRATUM_A007186
694 #define CONFIG_SYS_FSL_ERRATUM_A006593
695 #define CONFIG_SYS_FSL_ERRATUM_A007075
696 #define CONFIG_SYS_FSL_ERRATUM_A006475
697 #define CONFIG_SYS_FSL_ERRATUM_A006384
698 #define CONFIG_SYS_FSL_ERRATUM_A007212
699 #define CONFIG_SYS_FSL_ERRATUM_A004477
700 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
701 #define CONFIG_SYS_FSL_SFP_VER_3_0
703 #ifdef CONFIG_PPC_B4860
704 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
705 #define CONFIG_MAX_CPUS 4
706 #define CONFIG_MAX_DSP_CPUS 12
707 #define CONFIG_NUM_DSP_CPUS 6
708 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
709 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
710 #define CONFIG_SYS_NUM_FM1_DTSEC 6
711 #define CONFIG_SYS_NUM_FM1_10GEC 2
712 #define CONFIG_NUM_DDR_CONTROLLERS 2
713 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
714 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
715 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
716 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
717 #define CONFIG_SYS_FSL_SRIO_LIODN
719 #define CONFIG_MAX_CPUS 2
720 #define CONFIG_MAX_DSP_CPUS 2
721 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
722 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
723 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
724 #define CONFIG_SYS_NUM_FM1_DTSEC 4
725 #define CONFIG_SYS_NUM_FM1_10GEC 0
726 #define CONFIG_NUM_DDR_CONTROLLERS 1
729 #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
730 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
732 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
733 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
734 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
735 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
736 #ifdef CONFIG_SYS_FSL_DDR4
737 #define CONFIG_SYS_FSL_DDRC_GEN4
739 #if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042)
740 #define CONFIG_MAX_CPUS 4
741 #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
742 #define CONFIG_MAX_CPUS 2
744 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
745 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
746 #define CONFIG_SYS_FSL_NUM_LAWS 16
747 #define CONFIG_SYS_FSL_SRDS_1
748 #define CONFIG_SYS_FSL_SEC_COMPAT 5
749 #define CONFIG_SYS_NUM_FMAN 1
750 #define CONFIG_SYS_NUM_FM1_DTSEC 5
751 #define CONFIG_NUM_DDR_CONTROLLERS 1
752 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
753 #define CONFIG_PME_PLAT_CLK_DIV 2
754 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
755 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
756 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
757 #define CONFIG_SYS_FSL_ERRATUM_A008044
758 #define CONFIG_SYS_FMAN_V3
759 #define CONFIG_FM_PLAT_CLK_DIV 1
760 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
761 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
762 per rcw field value */
763 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
764 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
765 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
766 #define CONFIG_SYS_FSL_TBCLK_DIV 16
767 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
768 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
769 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
770 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
771 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
772 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
773 #define QE_MURAM_SIZE 0x6000UL
774 #define MAX_QE_RISC 1
775 #define QE_NUM_OF_SNUM 28
776 #define CONFIG_SYS_FSL_SFP_VER_3_0
777 #define CONFIG_SYS_FSL_ERRATUM_A008378
778 #define CONFIG_SYS_FSL_ERRATUM_A009663
780 #elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\
781 defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
783 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
784 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
785 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
786 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
787 #define CONFIG_SYS_FMAN_V3
788 #ifdef CONFIG_SYS_FSL_DDR4
789 #define CONFIG_SYS_FSL_DDRC_GEN4
791 #if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
792 #define CONFIG_MAX_CPUS 2
793 #elif defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
794 #define CONFIG_MAX_CPUS 1
796 #define CONFIG_SYS_FSL_NUM_CC_PLL 2
797 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
798 #define CONFIG_SYS_FSL_NUM_LAWS 16
799 #define CONFIG_SYS_FSL_SRDS_1
800 #define CONFIG_SYS_FSL_SEC_COMPAT 5
801 #define CONFIG_SYS_NUM_FMAN 1
802 #define CONFIG_SYS_NUM_FM1_DTSEC 4
803 #define CONFIG_SYS_NUM_FM1_10GEC 1
804 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
805 #define CONFIG_NUM_DDR_CONTROLLERS 1
806 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
807 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
808 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
809 #define CONFIG_SYS_FM1_CLK 0
810 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
811 per rcw field value */
812 #define CONFIG_QBMAN_CLK_DIV 1
813 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
814 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
815 #define CONFIG_SYS_FSL_TBCLK_DIV 16
816 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
817 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
818 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
819 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
820 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
821 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
822 #define QE_MURAM_SIZE 0x6000UL
823 #define MAX_QE_RISC 1
824 #define QE_NUM_OF_SNUM 28
825 #define CONFIG_SYS_FSL_SFP_VER_3_0
826 #define CONFIG_SYS_FSL_ERRATUM_A008378
827 #define CONFIG_SYS_FSL_ERRATUM_A009663
829 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
831 #define CONFIG_SYS_PPC64 /* 64-bit core */
832 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
833 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
834 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
835 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
836 #define CONFIG_SYS_FSL_QMAN_V3
837 #define CONFIG_MAX_CPUS 4
838 #define CONFIG_SYS_FSL_NUM_LAWS 32
839 #define CONFIG_SYS_FSL_SEC_COMPAT 4
840 #define CONFIG_SYS_NUM_FMAN 1
841 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
842 #define CONFIG_SYS_FSL_SRDS_1
843 #define CONFIG_SYS_FSL_PCI_VER_3_X
844 #if defined(CONFIG_PPC_T2080)
845 #define CONFIG_SYS_NUM_FM1_DTSEC 8
846 #define CONFIG_SYS_NUM_FM1_10GEC 4
847 #define CONFIG_SYS_FSL_SRDS_2
848 #define CONFIG_SYS_FSL_SRIO_LIODN
849 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
850 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
851 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
852 #elif defined(CONFIG_PPC_T2081)
853 #define CONFIG_SYS_NUM_FM1_DTSEC 6
854 #define CONFIG_SYS_NUM_FM1_10GEC 2
856 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
857 #define CONFIG_NUM_DDR_CONTROLLERS 1
858 #define CONFIG_PME_PLAT_CLK_DIV 1
859 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
860 #define CONFIG_SYS_FM1_CLK 0
861 #define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2
862 per rcw field value */
863 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
864 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
865 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
866 #define CONFIG_SYS_FMAN_V3
867 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
868 #define CONFIG_SYS_FSL_TBCLK_DIV 16
869 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
870 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
871 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
872 #define CONFIG_SYS_FSL_ERRATUM_A007212
873 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
874 #define CONFIG_SYS_FSL_SFP_VER_3_0
875 #define CONFIG_SYS_FSL_ISBC_VER 2
876 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
877 #define CONFIG_SYS_FSL_ERRATUM_A006593
878 #define CONFIG_SYS_FSL_ERRATUM_A007186
879 #define CONFIG_SYS_FSL_ERRATUM_A006379
880 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
881 #define CONFIG_SYS_FSL_SFP_VER_3_0
884 #elif defined(CONFIG_ARCH_C29X)
885 #define CONFIG_MAX_CPUS 1
886 #define CONFIG_FSL_SDHC_V2_3
887 #define CONFIG_SYS_FSL_NUM_LAWS 12
888 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
889 #define CONFIG_TSECV2_1
890 #define CONFIG_SYS_FSL_SEC_COMPAT 6
891 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
892 #define CONFIG_NUM_DDR_CONTROLLERS 1
893 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
894 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
895 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
896 #define CONFIG_SYS_FSL_ERRATUM_A005125
897 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
898 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
900 #elif defined(CONFIG_QEMU_E500)
901 #define CONFIG_MAX_CPUS 1
902 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000
905 #error Processor type not defined for this platform
908 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT
909 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
913 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2
915 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1
918 #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
919 !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
920 !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \
921 !defined(CONFIG_SYS_FSL_DDRC_GEN4)
922 #define CONFIG_SYS_FSL_DDRC_GEN3
925 #if !defined(CONFIG_ARCH_C29X)
926 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
929 #endif /* _ASM_MPC85xx_CONFIG_H_ */