2 * Copyright 2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 #ifndef _ASM_MPC85xx_CONFIG_H_
22 #define _ASM_MPC85xx_CONFIG_H_
24 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
26 /* Number of TLB CAM entries we have on FSL Book-E chips */
27 #if defined(CONFIG_E500MC)
28 #define CONFIG_SYS_NUM_TLBCAMS 64
29 #elif defined(CONFIG_E500)
30 #define CONFIG_SYS_NUM_TLBCAMS 16
33 #if defined(CONFIG_MPC8536)
34 #define CONFIG_MAX_CPUS 1
35 #define CONFIG_SYS_FSL_NUM_LAWS 12
36 #define CONFIG_SYS_FSL_SEC_COMPAT 2
38 #elif defined(CONFIG_MPC8540)
39 #define CONFIG_MAX_CPUS 1
40 #define CONFIG_SYS_FSL_NUM_LAWS 8
42 #elif defined(CONFIG_MPC8541)
43 #define CONFIG_MAX_CPUS 1
44 #define CONFIG_SYS_FSL_NUM_LAWS 8
45 #define CONFIG_SYS_FSL_SEC_COMPAT 2
47 #elif defined(CONFIG_MPC8544)
48 #define CONFIG_MAX_CPUS 1
49 #define CONFIG_SYS_FSL_NUM_LAWS 10
50 #define CONFIG_SYS_FSL_SEC_COMPAT 2
52 #elif defined(CONFIG_MPC8548)
53 #define CONFIG_MAX_CPUS 1
54 #define CONFIG_SYS_FSL_NUM_LAWS 10
55 #define CONFIG_SYS_FSL_SEC_COMPAT 2
57 #elif defined(CONFIG_MPC8555)
58 #define CONFIG_MAX_CPUS 1
59 #define CONFIG_SYS_FSL_NUM_LAWS 8
60 #define CONFIG_SYS_FSL_SEC_COMPAT 2
62 #elif defined(CONFIG_MPC8560)
63 #define CONFIG_MAX_CPUS 1
64 #define CONFIG_SYS_FSL_NUM_LAWS 8
66 #elif defined(CONFIG_MPC8568)
67 #define CONFIG_MAX_CPUS 1
68 #define CONFIG_SYS_FSL_NUM_LAWS 10
69 #define CONFIG_SYS_FSL_SEC_COMPAT 2
70 #define QE_MURAM_SIZE 0x10000UL
72 #define QE_NUM_OF_SNUM 28
74 #elif defined(CONFIG_MPC8569)
75 #define CONFIG_MAX_CPUS 1
76 #define CONFIG_SYS_FSL_NUM_LAWS 10
77 #define CONFIG_SYS_FSL_SEC_COMPAT 2
78 #define QE_MURAM_SIZE 0x20000UL
80 #define QE_NUM_OF_SNUM 46
82 #elif defined(CONFIG_MPC8572)
83 #define CONFIG_MAX_CPUS 2
84 #define CONFIG_SYS_FSL_NUM_LAWS 12
85 #define CONFIG_SYS_FSL_SEC_COMPAT 2
86 #define CONFIG_SYS_FSL_ERRATUM_DDR_115
87 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
89 #elif defined(CONFIG_P1010)
90 #define CONFIG_MAX_CPUS 1
91 #define CONFIG_SYS_FSL_NUM_LAWS 12
93 #define CONFIG_SYS_FSL_SEC_COMPAT 4
94 #define CONFIG_FSL_SATA_V2
95 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
96 #define CONFIG_NUM_DDR_CONTROLLERS 1
97 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
99 /* P1011 is single core version of P1020 */
100 #elif defined(CONFIG_P1011)
101 #define CONFIG_MAX_CPUS 1
102 #define CONFIG_SYS_FSL_NUM_LAWS 12
103 #define CONFIG_TSECV2
104 #define CONFIG_FSL_PCIE_DISABLE_ASPM
105 #define CONFIG_SYS_FSL_SEC_COMPAT 2
106 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
107 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
109 /* P1012 is single core version of P1021 */
110 #elif defined(CONFIG_P1012)
111 #define CONFIG_MAX_CPUS 1
112 #define CONFIG_SYS_FSL_NUM_LAWS 12
113 #define CONFIG_TSECV2
114 #define CONFIG_FSL_PCIE_DISABLE_ASPM
115 #define CONFIG_SYS_FSL_SEC_COMPAT 2
116 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
117 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
119 /* P1013 is single core version of P1022 */
120 #elif defined(CONFIG_P1013)
121 #define CONFIG_MAX_CPUS 1
122 #define CONFIG_SYS_FSL_NUM_LAWS 12
123 #define CONFIG_TSECV2
124 #define CONFIG_SYS_FSL_SEC_COMPAT 2
125 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
126 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
127 #define CONFIG_FSL_SATA_ERRATUM_A001
129 #elif defined(CONFIG_P1014)
130 #define CONFIG_MAX_CPUS 1
131 #define CONFIG_SYS_FSL_NUM_LAWS 12
132 #define CONFIG_TSECV2
133 #define CONFIG_SYS_FSL_SEC_COMPAT 4
134 #define CONFIG_FSL_SATA_V2
135 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
136 #define CONFIG_NUM_DDR_CONTROLLERS 1
137 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
139 /* P1015 is single core version of P1024 */
140 #elif defined(CONFIG_P1015)
141 #define CONFIG_MAX_CPUS 1
142 #define CONFIG_SYS_FSL_NUM_LAWS 12
143 #define CONFIG_TSECV2
144 #define CONFIG_FSL_PCIE_DISABLE_ASPM
145 #define CONFIG_SYS_FSL_SEC_COMPAT 2
146 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
147 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
149 /* P1016 is single core version of P1025 */
150 #elif defined(CONFIG_P1016)
151 #define CONFIG_MAX_CPUS 1
152 #define CONFIG_SYS_FSL_NUM_LAWS 12
153 #define CONFIG_TSECV2
154 #define CONFIG_FSL_PCIE_DISABLE_ASPM
155 #define CONFIG_SYS_FSL_SEC_COMPAT 2
156 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
157 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
159 /* P1017 is single core version of P1023 */
160 #elif defined(CONFIG_P1017)
161 #define CONFIG_MAX_CPUS 1
162 #define CONFIG_SYS_FSL_NUM_LAWS 12
163 #define CONFIG_SYS_FSL_SEC_COMPAT 4
164 #define CONFIG_SYS_NUM_FMAN 1
165 #define CONFIG_SYS_NUM_FM1_DTSEC 2
166 #define CONFIG_NUM_DDR_CONTROLLERS 1
167 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
168 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
170 #elif defined(CONFIG_P1020)
171 #define CONFIG_MAX_CPUS 2
172 #define CONFIG_SYS_FSL_NUM_LAWS 12
173 #define CONFIG_TSECV2
174 #define CONFIG_FSL_PCIE_DISABLE_ASPM
175 #define CONFIG_SYS_FSL_SEC_COMPAT 2
176 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
177 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
179 #elif defined(CONFIG_P1021)
180 #define CONFIG_MAX_CPUS 2
181 #define CONFIG_SYS_FSL_NUM_LAWS 12
182 #define CONFIG_TSECV2
183 #define CONFIG_FSL_PCIE_DISABLE_ASPM
184 #define CONFIG_SYS_FSL_SEC_COMPAT 2
185 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
186 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
188 #elif defined(CONFIG_P1022)
189 #define CONFIG_MAX_CPUS 2
190 #define CONFIG_SYS_FSL_NUM_LAWS 12
191 #define CONFIG_TSECV2
192 #define CONFIG_SYS_FSL_SEC_COMPAT 2
193 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
194 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
195 #define CONFIG_FSL_SATA_ERRATUM_A001
197 #elif defined(CONFIG_P1023)
198 #define CONFIG_MAX_CPUS 2
199 #define CONFIG_SYS_FSL_NUM_LAWS 12
200 #define CONFIG_SYS_FSL_SEC_COMPAT 4
201 #define CONFIG_SYS_NUM_FMAN 1
202 #define CONFIG_SYS_NUM_FM1_DTSEC 2
203 #define CONFIG_NUM_DDR_CONTROLLERS 1
204 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
205 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
207 /* P1024 is lower end variant of P1020 */
208 #elif defined(CONFIG_P1024)
209 #define CONFIG_MAX_CPUS 2
210 #define CONFIG_SYS_FSL_NUM_LAWS 12
211 #define CONFIG_TSECV2
212 #define CONFIG_FSL_PCIE_DISABLE_ASPM
213 #define CONFIG_SYS_FSL_SEC_COMPAT 2
214 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
215 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
217 /* P1025 is lower end variant of P1021 */
218 #elif defined(CONFIG_P1025)
219 #define CONFIG_MAX_CPUS 2
220 #define CONFIG_SYS_FSL_NUM_LAWS 12
221 #define CONFIG_TSECV2
222 #define CONFIG_FSL_PCIE_DISABLE_ASPM
223 #define CONFIG_SYS_FSL_SEC_COMPAT 2
224 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
225 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
227 /* P2010 is single core version of P2020 */
228 #elif defined(CONFIG_P2010)
229 #define CONFIG_MAX_CPUS 1
230 #define CONFIG_SYS_FSL_NUM_LAWS 12
231 #define CONFIG_SYS_FSL_SEC_COMPAT 2
232 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
233 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
235 #elif defined(CONFIG_P2020)
236 #define CONFIG_MAX_CPUS 2
237 #define CONFIG_SYS_FSL_NUM_LAWS 12
238 #define CONFIG_SYS_FSL_SEC_COMPAT 2
239 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
240 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
242 #elif defined(CONFIG_PPC_P2040)
243 #define CONFIG_MAX_CPUS 4
244 #define CONFIG_SYS_FSL_NUM_LAWS 32
245 #define CONFIG_SYS_FSL_SEC_COMPAT 4
246 #define CONFIG_SYS_NUM_FMAN 1
247 #define CONFIG_SYS_NUM_FM1_DTSEC 5
248 #define CONFIG_NUM_DDR_CONTROLLERS 1
250 #elif defined(CONFIG_PPC_P3041)
251 #define CONFIG_MAX_CPUS 4
252 #define CONFIG_SYS_FSL_NUM_LAWS 32
253 #define CONFIG_SYS_FSL_SEC_COMPAT 4
254 #define CONFIG_SYS_NUM_FMAN 1
255 #define CONFIG_SYS_NUM_FM1_DTSEC 5
256 #define CONFIG_SYS_NUM_FM1_10GEC 1
257 #define CONFIG_NUM_DDR_CONTROLLERS 1
259 #elif defined(CONFIG_PPC_P4040)
260 #define CONFIG_MAX_CPUS 4
261 #define CONFIG_SYS_FSL_NUM_LAWS 32
262 #define CONFIG_SYS_FSL_SEC_COMPAT 4
264 #elif defined(CONFIG_PPC_P4080)
265 #define CONFIG_MAX_CPUS 8
266 #define CONFIG_SYS_FSL_NUM_LAWS 32
267 #define CONFIG_SYS_FSL_SEC_COMPAT 4
268 #define CONFIG_SYS_NUM_FMAN 2
269 #define CONFIG_SYS_NUM_FM1_DTSEC 4
270 #define CONFIG_SYS_NUM_FM2_DTSEC 4
271 #define CONFIG_SYS_NUM_FM1_10GEC 1
272 #define CONFIG_SYS_NUM_FM2_10GEC 1
273 #define CONFIG_NUM_DDR_CONTROLLERS 2
274 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
275 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
276 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
277 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
278 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
279 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
280 #define CONFIG_SYS_FSL_ERRATUM_ESDHC136
281 #define CONFIG_SYS_P4080_ERRATUM_CPU22
282 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
284 /* P5010 is single core version of P5020 */
285 #elif defined(CONFIG_PPC_P5010)
286 #define CONFIG_MAX_CPUS 1
287 #define CONFIG_SYS_FSL_NUM_LAWS 32
288 #define CONFIG_SYS_FSL_SEC_COMPAT 4
289 #define CONFIG_SYS_NUM_FMAN 1
290 #define CONFIG_SYS_NUM_FM1_DTSEC 5
291 #define CONFIG_SYS_NUM_FM1_10GEC 1
292 #define CONFIG_NUM_DDR_CONTROLLERS 1
294 #elif defined(CONFIG_PPC_P5020)
295 #define CONFIG_MAX_CPUS 2
296 #define CONFIG_SYS_FSL_NUM_LAWS 32
297 #define CONFIG_SYS_FSL_SEC_COMPAT 4
298 #define CONFIG_SYS_NUM_FMAN 1
299 #define CONFIG_SYS_NUM_FM1_DTSEC 5
300 #define CONFIG_SYS_NUM_FM1_10GEC 1
301 #define CONFIG_NUM_DDR_CONTROLLERS 2
304 #error Processor type not defined for this platform
307 #endif /* _ASM_MPC85xx_CONFIG_H_ */