2 * Copyright 2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 #ifndef _ASM_MPC85xx_CONFIG_H_
22 #define _ASM_MPC85xx_CONFIG_H_
24 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
26 /* Number of TLB CAM entries we have on FSL Book-E chips */
27 #if defined(CONFIG_E500MC)
28 #define CONFIG_SYS_NUM_TLBCAMS 64
29 #elif defined(CONFIG_E500)
30 #define CONFIG_SYS_NUM_TLBCAMS 16
33 #if defined(CONFIG_MPC8536)
34 #define CONFIG_MAX_CPUS 1
35 #define CONFIG_SYS_FSL_NUM_LAWS 12
36 #define CONFIG_SYS_FSL_SEC_COMPAT 2
38 #elif defined(CONFIG_MPC8540)
39 #define CONFIG_MAX_CPUS 1
40 #define CONFIG_SYS_FSL_NUM_LAWS 8
42 #elif defined(CONFIG_MPC8541)
43 #define CONFIG_MAX_CPUS 1
44 #define CONFIG_SYS_FSL_NUM_LAWS 8
45 #define CONFIG_SYS_FSL_SEC_COMPAT 2
47 #elif defined(CONFIG_MPC8544)
48 #define CONFIG_MAX_CPUS 1
49 #define CONFIG_SYS_FSL_NUM_LAWS 10
50 #define CONFIG_SYS_FSL_SEC_COMPAT 2
52 #elif defined(CONFIG_MPC8548)
53 #define CONFIG_MAX_CPUS 1
54 #define CONFIG_SYS_FSL_NUM_LAWS 10
55 #define CONFIG_SYS_FSL_SEC_COMPAT 2
57 #elif defined(CONFIG_MPC8555)
58 #define CONFIG_MAX_CPUS 1
59 #define CONFIG_SYS_FSL_NUM_LAWS 8
60 #define CONFIG_SYS_FSL_SEC_COMPAT 2
62 #elif defined(CONFIG_MPC8560)
63 #define CONFIG_MAX_CPUS 1
64 #define CONFIG_SYS_FSL_NUM_LAWS 8
66 #elif defined(CONFIG_MPC8568)
67 #define CONFIG_MAX_CPUS 1
68 #define CONFIG_SYS_FSL_NUM_LAWS 10
69 #define CONFIG_SYS_FSL_SEC_COMPAT 2
70 #define QE_MURAM_SIZE 0x10000UL
72 #define QE_NUM_OF_SNUM 28
74 #elif defined(CONFIG_MPC8569)
75 #define CONFIG_MAX_CPUS 1
76 #define CONFIG_SYS_FSL_NUM_LAWS 10
77 #define CONFIG_SYS_FSL_SEC_COMPAT 2
78 #define QE_MURAM_SIZE 0x20000UL
80 #define QE_NUM_OF_SNUM 46
82 #elif defined(CONFIG_MPC8572)
83 #define CONFIG_MAX_CPUS 2
84 #define CONFIG_SYS_FSL_NUM_LAWS 12
85 #define CONFIG_SYS_FSL_SEC_COMPAT 2
86 #define CONFIG_SYS_FSL_ERRATUM_DDR_115
87 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
89 #elif defined(CONFIG_P1010)
90 #define CONFIG_MAX_CPUS 1
91 #define CONFIG_SYS_FSL_NUM_LAWS 12
93 #define CONFIG_SYS_FSL_SEC_COMPAT 4
95 /* P1011 is single core version of P1020 */
96 #elif defined(CONFIG_P1011)
97 #define CONFIG_MAX_CPUS 1
98 #define CONFIG_SYS_FSL_NUM_LAWS 12
100 #define CONFIG_FSL_PCIE_DISABLE_ASPM
101 #define CONFIG_SYS_FSL_SEC_COMPAT 2
102 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
103 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
105 /* P1012 is single core version of P1021 */
106 #elif defined(CONFIG_P1012)
107 #define CONFIG_MAX_CPUS 1
108 #define CONFIG_SYS_FSL_NUM_LAWS 12
109 #define CONFIG_TSECV2
110 #define CONFIG_FSL_PCIE_DISABLE_ASPM
111 #define CONFIG_SYS_FSL_SEC_COMPAT 2
112 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
113 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
115 /* P1013 is single core version of P1022 */
116 #elif defined(CONFIG_P1013)
117 #define CONFIG_MAX_CPUS 1
118 #define CONFIG_SYS_FSL_NUM_LAWS 12
119 #define CONFIG_TSECV2
120 #define CONFIG_SYS_FSL_SEC_COMPAT 2
121 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
122 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
123 #define CONFIG_FSL_SATA_ERRATUM_A001
125 #elif defined(CONFIG_P1014)
126 #define CONFIG_MAX_CPUS 1
127 #define CONFIG_SYS_FSL_NUM_LAWS 12
128 #define CONFIG_TSECV2
129 #define CONFIG_SYS_FSL_SEC_COMPAT 4
131 /* P1015 is single core version of P1024 */
132 #elif defined(CONFIG_P1015)
133 #define CONFIG_MAX_CPUS 1
134 #define CONFIG_SYS_FSL_NUM_LAWS 12
135 #define CONFIG_TSECV2
136 #define CONFIG_FSL_PCIE_DISABLE_ASPM
137 #define CONFIG_SYS_FSL_SEC_COMPAT 2
138 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
139 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
141 /* P1016 is single core version of P1025 */
142 #elif defined(CONFIG_P1016)
143 #define CONFIG_MAX_CPUS 1
144 #define CONFIG_SYS_FSL_NUM_LAWS 12
145 #define CONFIG_TSECV2
146 #define CONFIG_FSL_PCIE_DISABLE_ASPM
147 #define CONFIG_SYS_FSL_SEC_COMPAT 2
148 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
149 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
151 /* P1017 is single core version of P1023 */
152 #elif defined(CONFIG_P1017)
153 #define CONFIG_MAX_CPUS 1
154 #define CONFIG_SYS_FSL_NUM_LAWS 12
155 #define CONFIG_SYS_FSL_SEC_COMPAT 4
156 #define CONFIG_SYS_NUM_FMAN 1
157 #define CONFIG_SYS_NUM_FM1_DTSEC 2
158 #define CONFIG_NUM_DDR_CONTROLLERS 1
159 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
160 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
162 #elif defined(CONFIG_P1020)
163 #define CONFIG_MAX_CPUS 2
164 #define CONFIG_SYS_FSL_NUM_LAWS 12
165 #define CONFIG_TSECV2
166 #define CONFIG_FSL_PCIE_DISABLE_ASPM
167 #define CONFIG_SYS_FSL_SEC_COMPAT 2
168 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
169 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
171 #elif defined(CONFIG_P1021)
172 #define CONFIG_MAX_CPUS 2
173 #define CONFIG_SYS_FSL_NUM_LAWS 12
174 #define CONFIG_TSECV2
175 #define CONFIG_FSL_PCIE_DISABLE_ASPM
176 #define CONFIG_SYS_FSL_SEC_COMPAT 2
177 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
178 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
180 #elif defined(CONFIG_P1022)
181 #define CONFIG_MAX_CPUS 2
182 #define CONFIG_SYS_FSL_NUM_LAWS 12
183 #define CONFIG_TSECV2
184 #define CONFIG_SYS_FSL_SEC_COMPAT 2
185 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
186 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
187 #define CONFIG_FSL_SATA_ERRATUM_A001
189 #elif defined(CONFIG_P1023)
190 #define CONFIG_MAX_CPUS 2
191 #define CONFIG_SYS_FSL_NUM_LAWS 12
192 #define CONFIG_SYS_FSL_SEC_COMPAT 4
193 #define CONFIG_SYS_NUM_FMAN 1
194 #define CONFIG_SYS_NUM_FM1_DTSEC 2
195 #define CONFIG_NUM_DDR_CONTROLLERS 1
196 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
197 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
199 /* P1024 is lower end variant of P1020 */
200 #elif defined(CONFIG_P1024)
201 #define CONFIG_MAX_CPUS 2
202 #define CONFIG_SYS_FSL_NUM_LAWS 12
203 #define CONFIG_TSECV2
204 #define CONFIG_FSL_PCIE_DISABLE_ASPM
205 #define CONFIG_SYS_FSL_SEC_COMPAT 2
206 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
207 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
209 /* P1025 is lower end variant of P1021 */
210 #elif defined(CONFIG_P1025)
211 #define CONFIG_MAX_CPUS 2
212 #define CONFIG_SYS_FSL_NUM_LAWS 12
213 #define CONFIG_TSECV2
214 #define CONFIG_FSL_PCIE_DISABLE_ASPM
215 #define CONFIG_SYS_FSL_SEC_COMPAT 2
216 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
217 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
219 /* P2010 is single core version of P2020 */
220 #elif defined(CONFIG_P2010)
221 #define CONFIG_MAX_CPUS 1
222 #define CONFIG_SYS_FSL_NUM_LAWS 12
223 #define CONFIG_SYS_FSL_SEC_COMPAT 2
224 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
225 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
227 #elif defined(CONFIG_P2020)
228 #define CONFIG_MAX_CPUS 2
229 #define CONFIG_SYS_FSL_NUM_LAWS 12
230 #define CONFIG_SYS_FSL_SEC_COMPAT 2
231 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
232 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
234 #elif defined(CONFIG_PPC_P2040)
235 #define CONFIG_MAX_CPUS 4
236 #define CONFIG_SYS_FSL_NUM_LAWS 32
237 #define CONFIG_SYS_FSL_SEC_COMPAT 4
238 #define CONFIG_SYS_NUM_FMAN 1
239 #define CONFIG_SYS_NUM_FM1_DTSEC 5
240 #define CONFIG_NUM_DDR_CONTROLLERS 1
242 #elif defined(CONFIG_PPC_P3041)
243 #define CONFIG_MAX_CPUS 4
244 #define CONFIG_SYS_FSL_NUM_LAWS 32
245 #define CONFIG_SYS_FSL_SEC_COMPAT 4
246 #define CONFIG_SYS_NUM_FMAN 1
247 #define CONFIG_SYS_NUM_FM1_DTSEC 5
248 #define CONFIG_SYS_NUM_FM1_10GEC 1
249 #define CONFIG_NUM_DDR_CONTROLLERS 1
251 #elif defined(CONFIG_PPC_P4040)
252 #define CONFIG_MAX_CPUS 4
253 #define CONFIG_SYS_FSL_NUM_LAWS 32
254 #define CONFIG_SYS_FSL_SEC_COMPAT 4
256 #elif defined(CONFIG_PPC_P4080)
257 #define CONFIG_MAX_CPUS 8
258 #define CONFIG_SYS_FSL_NUM_LAWS 32
259 #define CONFIG_SYS_FSL_SEC_COMPAT 4
260 #define CONFIG_SYS_NUM_FMAN 2
261 #define CONFIG_SYS_NUM_FM1_DTSEC 4
262 #define CONFIG_SYS_NUM_FM2_DTSEC 4
263 #define CONFIG_SYS_NUM_FM1_10GEC 1
264 #define CONFIG_SYS_NUM_FM2_10GEC 1
265 #define CONFIG_NUM_DDR_CONTROLLERS 2
266 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
267 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
268 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
269 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
270 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
271 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
272 #define CONFIG_SYS_FSL_ERRATUM_ESDHC136
273 #define CONFIG_SYS_P4080_ERRATUM_CPU22
274 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
276 /* P5010 is single core version of P5020 */
277 #elif defined(CONFIG_PPC_P5010)
278 #define CONFIG_MAX_CPUS 1
279 #define CONFIG_SYS_FSL_NUM_LAWS 32
280 #define CONFIG_SYS_FSL_SEC_COMPAT 4
281 #define CONFIG_SYS_NUM_FMAN 1
282 #define CONFIG_SYS_NUM_FM1_DTSEC 5
283 #define CONFIG_SYS_NUM_FM1_10GEC 1
284 #define CONFIG_NUM_DDR_CONTROLLERS 1
286 #elif defined(CONFIG_PPC_P5020)
287 #define CONFIG_MAX_CPUS 2
288 #define CONFIG_SYS_FSL_NUM_LAWS 32
289 #define CONFIG_SYS_FSL_SEC_COMPAT 4
290 #define CONFIG_SYS_NUM_FMAN 1
291 #define CONFIG_SYS_NUM_FM1_DTSEC 5
292 #define CONFIG_SYS_NUM_FM1_10GEC 1
293 #define CONFIG_NUM_DDR_CONTROLLERS 2
296 #error Processor type not defined for this platform
299 #endif /* _ASM_MPC85xx_CONFIG_H_ */