1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
6 #ifndef _ASM_MPC85xx_CONFIG_H_
7 #define _ASM_MPC85xx_CONFIG_H_
9 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
12 * This macro should be removed when we no longer care about backwards
13 * compatibility with older operating systems.
15 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
17 #include <fsl_ddrc_version.h>
19 #if defined(CONFIG_ARCH_MPC8548)
20 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
21 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
22 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
23 #define CONFIG_SYS_FSL_RMU
24 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
26 #elif defined(CONFIG_ARCH_P1010)
27 #define CONFIG_FSL_SDHC_V2_3
29 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
30 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
31 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
33 /* P1011 is single core version of P1020 */
34 #elif defined(CONFIG_ARCH_P1011)
37 #elif defined(CONFIG_ARCH_P1020)
40 #elif defined(CONFIG_ARCH_P1021)
42 #define QE_MURAM_SIZE 0x6000UL
44 #define QE_NUM_OF_SNUM 28
46 #elif defined(CONFIG_ARCH_P1023)
47 #define CONFIG_SYS_NUM_FMAN 1
48 #define CONFIG_SYS_NUM_FM1_DTSEC 2
49 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
50 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
51 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
53 /* P1024 is lower end variant of P1020 */
54 #elif defined(CONFIG_ARCH_P1024)
57 /* P1025 is lower end variant of P1021 */
58 #elif defined(CONFIG_ARCH_P1025)
60 #define QE_MURAM_SIZE 0x6000UL
62 #define QE_NUM_OF_SNUM 28
64 #elif defined(CONFIG_ARCH_P2020)
65 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
66 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
67 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
68 #define CONFIG_SYS_FSL_RMU
69 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
71 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
72 #define CONFIG_SYS_NUM_FMAN 1
73 #define CONFIG_SYS_NUM_FM1_DTSEC 5
74 #define CONFIG_SYS_NUM_FM1_10GEC 1
75 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
76 #define CONFIG_SYS_FSL_TBCLK_DIV 32
77 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
78 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
79 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
80 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
81 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
82 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
83 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
85 #elif defined(CONFIG_ARCH_P3041)
86 #define CONFIG_SYS_NUM_FMAN 1
87 #define CONFIG_SYS_NUM_FM1_DTSEC 5
88 #define CONFIG_SYS_NUM_FM1_10GEC 1
89 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
90 #define CONFIG_SYS_FSL_TBCLK_DIV 32
91 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
92 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
93 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
94 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
95 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
96 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
97 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
99 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
100 #define CONFIG_SYS_NUM_FMAN 2
101 #define CONFIG_SYS_NUM_FM1_DTSEC 4
102 #define CONFIG_SYS_NUM_FM2_DTSEC 4
103 #define CONFIG_SYS_NUM_FM1_10GEC 1
104 #define CONFIG_SYS_NUM_FM2_10GEC 1
105 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
106 #define CONFIG_SYS_FSL_TBCLK_DIV 16
107 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
108 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
109 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
110 #define CONFIG_SYS_FSL_RMU
111 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
112 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
114 #elif defined(CONFIG_ARCH_P5040)
115 #define CONFIG_SYS_NUM_FMAN 2
116 #define CONFIG_SYS_NUM_FM1_DTSEC 5
117 #define CONFIG_SYS_NUM_FM1_10GEC 1
118 #define CONFIG_SYS_NUM_FM2_DTSEC 5
119 #define CONFIG_SYS_NUM_FM2_10GEC 1
120 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
121 #define CONFIG_SYS_FSL_TBCLK_DIV 16
122 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
123 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
124 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
125 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
127 #elif defined(CONFIG_ARCH_BSC9131)
128 #define CONFIG_FSL_SDHC_V2_3
129 #define CONFIG_TSECV2
130 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
132 #elif defined(CONFIG_ARCH_BSC9132)
133 #define CONFIG_FSL_SDHC_V2_3
134 #define CONFIG_TSECV2
135 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
137 #elif defined(CONFIG_ARCH_T4240)
138 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
139 #ifdef CONFIG_ARCH_T4240
140 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
141 #define CONFIG_SYS_NUM_FM1_DTSEC 8
142 #define CONFIG_SYS_NUM_FM1_10GEC 2
143 #define CONFIG_SYS_NUM_FM2_DTSEC 8
144 #define CONFIG_SYS_NUM_FM2_10GEC 2
146 #define CONFIG_SYS_NUM_FM1_DTSEC 6
147 #define CONFIG_SYS_NUM_FM1_10GEC 1
148 #define CONFIG_SYS_NUM_FM2_DTSEC 8
149 #define CONFIG_SYS_NUM_FM2_10GEC 1
151 #define CONFIG_SYS_FSL_SRDS_1
152 #define CONFIG_SYS_FSL_SRDS_2
153 #define CONFIG_SYS_FSL_SRDS_3
154 #define CONFIG_SYS_FSL_SRDS_4
155 #define CONFIG_SYS_NUM_FMAN 2
156 #define CONFIG_SYS_PME_CLK 0
157 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
158 #define CONFIG_SYS_FM1_CLK 3
159 #define CONFIG_SYS_FM2_CLK 3
160 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
161 #define CONFIG_SYS_FSL_TBCLK_DIV 16
162 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
163 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
164 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
165 #define CONFIG_SYS_FSL_SRIO_LIODN
166 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
167 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
169 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
170 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
171 #define CONFIG_SYS_FSL_SRDS_1
172 #define CONFIG_SYS_FSL_SRDS_2
173 #define CONFIG_SYS_NUM_FMAN 1
174 #define CONFIG_SYS_FM1_CLK 0
175 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
176 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
177 #define CONFIG_SYS_FSL_TBCLK_DIV 16
178 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
180 #ifdef CONFIG_ARCH_B4860
181 #define CONFIG_MAX_DSP_CPUS 12
182 #define CONFIG_NUM_DSP_CPUS 6
183 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
184 #define CONFIG_SYS_NUM_FM1_DTSEC 6
185 #define CONFIG_SYS_NUM_FM1_10GEC 2
186 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
187 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
188 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
189 #define CONFIG_SYS_FSL_SRIO_LIODN
191 #define CONFIG_MAX_DSP_CPUS 2
192 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
193 #define CONFIG_SYS_NUM_FM1_DTSEC 4
194 #define CONFIG_SYS_NUM_FM1_10GEC 0
197 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
198 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
199 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
200 #define CONFIG_SYS_FSL_SRDS_1
201 #define CONFIG_SYS_NUM_FMAN 1
202 #define CONFIG_SYS_NUM_FM1_DTSEC 5
203 #define CONFIG_PME_PLAT_CLK_DIV 2
204 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
205 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
206 #define CONFIG_FM_PLAT_CLK_DIV 1
207 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
208 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
209 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
210 #define CONFIG_SYS_FSL_TBCLK_DIV 16
211 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
212 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
213 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
214 #define QE_MURAM_SIZE 0x6000UL
215 #define MAX_QE_RISC 1
216 #define QE_NUM_OF_SNUM 28
218 #elif defined(CONFIG_ARCH_T1024)
219 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
220 #define CONFIG_SYS_FSL_NUM_CC_PLL 2
221 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
222 #define CONFIG_SYS_FSL_SRDS_1
223 #define CONFIG_SYS_NUM_FMAN 1
224 #define CONFIG_SYS_NUM_FM1_DTSEC 4
225 #define CONFIG_SYS_NUM_FM1_10GEC 1
226 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
227 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
228 #define CONFIG_SYS_FM1_CLK 0
229 #define CONFIG_QBMAN_CLK_DIV 1
230 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
231 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
232 #define CONFIG_SYS_FSL_TBCLK_DIV 16
233 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
234 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
235 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
236 #define QE_MURAM_SIZE 0x6000UL
237 #define MAX_QE_RISC 1
238 #define QE_NUM_OF_SNUM 28
240 #elif defined(CONFIG_ARCH_T2080)
241 #define CONFIG_SYS_FSL_QMAN_V3
242 #define CONFIG_SYS_NUM_FMAN 1
243 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
244 #define CONFIG_SYS_FSL_SRDS_1
245 #if defined(CONFIG_ARCH_T2080)
246 #define CONFIG_SYS_NUM_FM1_DTSEC 8
247 #define CONFIG_SYS_NUM_FM1_10GEC 4
248 #define CONFIG_SYS_FSL_SRDS_2
249 #define CONFIG_SYS_FSL_SRIO_LIODN
250 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
251 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
252 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
254 #define CONFIG_PME_PLAT_CLK_DIV 1
255 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
256 #define CONFIG_SYS_FM1_CLK 0
257 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
258 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
259 #define CONFIG_SYS_FSL_TBCLK_DIV 16
260 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
261 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
262 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
265 #elif defined(CONFIG_ARCH_C29X)
266 #define CONFIG_FSL_SDHC_V2_3
267 #define CONFIG_TSECV2_1
268 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
269 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
273 #endif /* _ASM_MPC85xx_CONFIG_H_ */