1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
6 #ifndef _ASM_MPC85xx_CONFIG_H_
7 #define _ASM_MPC85xx_CONFIG_H_
9 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
12 * This macro should be removed when we no longer care about backwards
13 * compatibility with older operating systems.
15 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
17 #include <fsl_ddrc_version.h>
20 #define CONFIG_SYS_FSL_IFC_BE
21 #define CONFIG_SYS_FSL_SFP_BE
22 #define CONFIG_SYS_FSL_SEC_MON_BE
24 #if defined(CONFIG_ARCH_MPC8548)
25 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
26 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
27 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
28 #define CONFIG_SYS_FSL_RMU
29 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
31 #elif defined(CONFIG_ARCH_MPC8568)
32 #define QE_MURAM_SIZE 0x10000UL
34 #define QE_NUM_OF_SNUM 28
35 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
36 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
37 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
38 #define CONFIG_SYS_FSL_RMU
39 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
41 #elif defined(CONFIG_ARCH_P1010)
42 #define CONFIG_FSL_SDHC_V2_3
44 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
45 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
46 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
47 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
48 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
49 #define CONFIG_ESDHC_HC_BLK_ADDR
51 /* P1011 is single core version of P1020 */
52 #elif defined(CONFIG_ARCH_P1011)
54 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
56 #elif defined(CONFIG_ARCH_P1020)
58 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
59 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
62 #elif defined(CONFIG_ARCH_P1021)
64 #define QE_MURAM_SIZE 0x6000UL
66 #define QE_NUM_OF_SNUM 28
67 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
69 #elif defined(CONFIG_ARCH_P1022)
71 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
73 #elif defined(CONFIG_ARCH_P1023)
74 #define CONFIG_SYS_NUM_FMAN 1
75 #define CONFIG_SYS_NUM_FM1_DTSEC 2
76 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
77 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
78 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
79 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
80 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
82 /* P1024 is lower end variant of P1020 */
83 #elif defined(CONFIG_ARCH_P1024)
85 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
87 /* P1025 is lower end variant of P1021 */
88 #elif defined(CONFIG_ARCH_P1025)
89 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
91 #define QE_MURAM_SIZE 0x6000UL
93 #define QE_NUM_OF_SNUM 28
95 #elif defined(CONFIG_ARCH_P2020)
96 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
97 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
98 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
99 #define CONFIG_SYS_FSL_RMU
100 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
101 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
103 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
104 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
105 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
106 #define CONFIG_SYS_NUM_FMAN 1
107 #define CONFIG_SYS_NUM_FM1_DTSEC 5
108 #define CONFIG_SYS_NUM_FM1_10GEC 1
109 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
110 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
112 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
113 #define CONFIG_SYS_FSL_TBCLK_DIV 32
114 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
115 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
116 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
117 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
118 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
119 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
120 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
121 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
123 #elif defined(CONFIG_ARCH_P3041)
124 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
125 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
126 #define CONFIG_SYS_NUM_FMAN 1
127 #define CONFIG_SYS_NUM_FM1_DTSEC 5
128 #define CONFIG_SYS_NUM_FM1_10GEC 1
129 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
130 #define CONFIG_SYS_FSL_TBCLK_DIV 32
131 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
132 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
133 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
134 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
135 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
136 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
137 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
138 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
139 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
141 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
142 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
143 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
144 #define CONFIG_SYS_NUM_FMAN 2
145 #define CONFIG_SYS_NUM_FM1_DTSEC 4
146 #define CONFIG_SYS_NUM_FM2_DTSEC 4
147 #define CONFIG_SYS_NUM_FM1_10GEC 1
148 #define CONFIG_SYS_NUM_FM2_10GEC 1
149 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
150 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
151 #define CONFIG_SYS_FSL_TBCLK_DIV 16
152 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
153 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
154 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
155 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
156 #define CONFIG_SYS_FSL_RMU
157 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
158 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
160 #elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */
161 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
162 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
163 #define CONFIG_SYS_NUM_FMAN 1
164 #define CONFIG_SYS_NUM_FM1_DTSEC 5
165 #define CONFIG_SYS_NUM_FM1_10GEC 1
166 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
167 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
168 #define CONFIG_SYS_FSL_TBCLK_DIV 32
169 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
170 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
171 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
172 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
173 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
174 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
175 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
176 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
178 #elif defined(CONFIG_ARCH_P5040)
179 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
180 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
181 #define CONFIG_SYS_NUM_FMAN 2
182 #define CONFIG_SYS_NUM_FM1_DTSEC 5
183 #define CONFIG_SYS_NUM_FM1_10GEC 1
184 #define CONFIG_SYS_NUM_FM2_DTSEC 5
185 #define CONFIG_SYS_NUM_FM2_10GEC 1
186 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
187 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
188 #define CONFIG_SYS_FSL_TBCLK_DIV 16
189 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
190 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
191 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
192 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
193 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
195 #elif defined(CONFIG_ARCH_BSC9131)
196 #define CONFIG_FSL_SDHC_V2_3
197 #define CONFIG_TSECV2
198 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
199 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
200 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
201 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
202 #define CONFIG_NAND_FSL_IFC
203 #define CONFIG_ESDHC_HC_BLK_ADDR
205 #elif defined(CONFIG_ARCH_BSC9132)
206 #define CONFIG_FSL_SDHC_V2_3
207 #define CONFIG_TSECV2
208 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
209 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
210 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
211 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
212 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
213 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
214 #define CONFIG_NAND_FSL_IFC
215 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
216 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
217 #define CONFIG_ESDHC_HC_BLK_ADDR
219 #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
220 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
221 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
222 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
223 #ifdef CONFIG_ARCH_T4240
224 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
225 #define CONFIG_SYS_NUM_FM1_DTSEC 8
226 #define CONFIG_SYS_NUM_FM1_10GEC 2
227 #define CONFIG_SYS_NUM_FM2_DTSEC 8
228 #define CONFIG_SYS_NUM_FM2_10GEC 2
230 #define CONFIG_SYS_NUM_FM1_DTSEC 6
231 #define CONFIG_SYS_NUM_FM1_10GEC 1
232 #define CONFIG_SYS_NUM_FM2_DTSEC 8
233 #define CONFIG_SYS_NUM_FM2_10GEC 1
234 #if defined(CONFIG_ARCH_T4160)
235 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
238 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
239 #define CONFIG_SYS_FSL_SRDS_1
240 #define CONFIG_SYS_FSL_SRDS_2
241 #define CONFIG_SYS_FSL_SRDS_3
242 #define CONFIG_SYS_FSL_SRDS_4
243 #define CONFIG_SYS_NUM_FMAN 2
244 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
245 #define CONFIG_SYS_PME_CLK 0
246 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
247 #define CONFIG_SYS_FMAN_V3
248 #define CONFIG_SYS_FM1_CLK 3
249 #define CONFIG_SYS_FM2_CLK 3
250 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
251 #define CONFIG_SYS_FSL_TBCLK_DIV 16
252 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
253 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
254 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
255 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
256 #define CONFIG_SYS_FSL_SRIO_LIODN
257 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
258 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
259 #define CONFIG_SYS_FSL_SFP_VER_3_0
260 #define CONFIG_SYS_FSL_PCI_VER_3_X
262 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
263 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
264 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
265 #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
266 #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
267 #define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/
268 #define CONFIG_SYS_FSL_SRDS_1
269 #define CONFIG_SYS_FSL_SRDS_2
270 #define CONFIG_SYS_MAPLE
271 #define CONFIG_SYS_CPRI
272 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
273 #define CONFIG_SYS_NUM_FMAN 1
274 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
275 #define CONFIG_SYS_FM1_CLK 0
276 #define CONFIG_SYS_CPRI_CLK 3
277 #define CONFIG_SYS_ULB_CLK 4
278 #define CONFIG_SYS_ETVPE_CLK 1
279 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
280 #define CONFIG_SYS_FMAN_V3
281 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
282 #define CONFIG_SYS_FSL_TBCLK_DIV 16
283 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
284 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
285 #define CONFIG_SYS_FSL_SFP_VER_3_0
287 #ifdef CONFIG_ARCH_B4860
288 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
289 #define CONFIG_MAX_DSP_CPUS 12
290 #define CONFIG_NUM_DSP_CPUS 6
291 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
292 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
293 #define CONFIG_SYS_NUM_FM1_DTSEC 6
294 #define CONFIG_SYS_NUM_FM1_10GEC 2
295 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
296 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
297 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
298 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
299 #define CONFIG_SYS_FSL_SRIO_LIODN
301 #define CONFIG_MAX_DSP_CPUS 2
302 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
303 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
304 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
305 #define CONFIG_SYS_NUM_FM1_DTSEC 4
306 #define CONFIG_SYS_NUM_FM1_10GEC 0
309 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
311 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
312 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
313 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
314 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
315 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
316 #define CONFIG_SYS_FSL_SRDS_1
317 #define CONFIG_SYS_NUM_FMAN 1
318 #define CONFIG_SYS_NUM_FM1_DTSEC 5
319 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
320 #define CONFIG_PME_PLAT_CLK_DIV 2
321 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
322 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
323 #define CONFIG_SYS_FMAN_V3
324 #define CONFIG_FM_PLAT_CLK_DIV 1
325 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
326 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
327 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
328 #define CONFIG_SYS_FSL_TBCLK_DIV 16
329 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
330 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
331 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
332 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
333 #define QE_MURAM_SIZE 0x6000UL
334 #define MAX_QE_RISC 1
335 #define QE_NUM_OF_SNUM 28
336 #define CONFIG_SYS_FSL_SFP_VER_3_0
338 #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
340 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
341 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
342 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
343 #define CONFIG_SYS_FMAN_V3
344 #define CONFIG_SYS_FSL_NUM_CC_PLL 2
345 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
346 #define CONFIG_SYS_FSL_SRDS_1
347 #define CONFIG_SYS_NUM_FMAN 1
348 #define CONFIG_SYS_NUM_FM1_DTSEC 4
349 #define CONFIG_SYS_NUM_FM1_10GEC 1
350 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
351 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
352 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
353 #define CONFIG_SYS_FM1_CLK 0
354 #define CONFIG_QBMAN_CLK_DIV 1
355 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
356 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
357 #define CONFIG_SYS_FSL_TBCLK_DIV 16
358 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
359 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
360 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
361 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
362 #define QE_MURAM_SIZE 0x6000UL
363 #define MAX_QE_RISC 1
364 #define QE_NUM_OF_SNUM 28
365 #define CONFIG_SYS_FSL_SFP_VER_3_0
367 #elif defined(CONFIG_ARCH_T2080)
368 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
369 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
370 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
371 #define CONFIG_SYS_FSL_QMAN_V3
372 #define CONFIG_SYS_NUM_FMAN 1
373 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
374 #define CONFIG_SYS_FSL_SRDS_1
375 #define CONFIG_SYS_FSL_PCI_VER_3_X
376 #if defined(CONFIG_ARCH_T2080)
377 #define CONFIG_SYS_NUM_FM1_DTSEC 8
378 #define CONFIG_SYS_NUM_FM1_10GEC 4
379 #define CONFIG_SYS_FSL_SRDS_2
380 #define CONFIG_SYS_FSL_SRIO_LIODN
381 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
382 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
383 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
385 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
386 #define CONFIG_PME_PLAT_CLK_DIV 1
387 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
388 #define CONFIG_SYS_FM1_CLK 0
389 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
390 #define CONFIG_SYS_FMAN_V3
391 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
392 #define CONFIG_SYS_FSL_TBCLK_DIV 16
393 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
394 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
395 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
396 #define CONFIG_SYS_FSL_SFP_VER_3_0
397 #define CONFIG_SYS_FSL_ISBC_VER 2
398 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
399 #define CONFIG_SYS_FSL_SFP_VER_3_0
402 #elif defined(CONFIG_ARCH_C29X)
403 #define CONFIG_FSL_SDHC_V2_3
404 #define CONFIG_TSECV2_1
405 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
406 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
407 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
411 #if !defined(CONFIG_ARCH_C29X)
412 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
415 #endif /* _ASM_MPC85xx_CONFIG_H_ */