1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
6 #ifndef _ASM_MPC85xx_CONFIG_H_
7 #define _ASM_MPC85xx_CONFIG_H_
9 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
12 * This macro should be removed when we no longer care about backwards
13 * compatibility with older operating systems.
15 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
17 #include <fsl_ddrc_version.h>
20 #define CONFIG_SYS_FSL_IFC_BE
21 #define CONFIG_SYS_FSL_SFP_BE
22 #define CONFIG_SYS_FSL_SEC_MON_BE
24 #if defined(CONFIG_ARCH_MPC8548)
25 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
26 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
27 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
28 #define CONFIG_SYS_FSL_RMU
29 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
31 #elif defined(CONFIG_ARCH_P1010)
32 #define CONFIG_FSL_SDHC_V2_3
34 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
35 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
36 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
37 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
38 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
39 #define CONFIG_ESDHC_HC_BLK_ADDR
41 /* P1011 is single core version of P1020 */
42 #elif defined(CONFIG_ARCH_P1011)
44 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
46 #elif defined(CONFIG_ARCH_P1020)
48 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
49 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
52 #elif defined(CONFIG_ARCH_P1021)
54 #define QE_MURAM_SIZE 0x6000UL
56 #define QE_NUM_OF_SNUM 28
57 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
59 #elif defined(CONFIG_ARCH_P1023)
60 #define CONFIG_SYS_NUM_FMAN 1
61 #define CONFIG_SYS_NUM_FM1_DTSEC 2
62 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
63 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
64 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
65 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
66 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
68 /* P1024 is lower end variant of P1020 */
69 #elif defined(CONFIG_ARCH_P1024)
71 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
73 /* P1025 is lower end variant of P1021 */
74 #elif defined(CONFIG_ARCH_P1025)
75 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
77 #define QE_MURAM_SIZE 0x6000UL
79 #define QE_NUM_OF_SNUM 28
81 #elif defined(CONFIG_ARCH_P2020)
82 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
83 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
84 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
85 #define CONFIG_SYS_FSL_RMU
86 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
87 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
89 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
90 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
91 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
92 #define CONFIG_SYS_NUM_FMAN 1
93 #define CONFIG_SYS_NUM_FM1_DTSEC 5
94 #define CONFIG_SYS_NUM_FM1_10GEC 1
95 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
96 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
98 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
99 #define CONFIG_SYS_FSL_TBCLK_DIV 32
100 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
101 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
102 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
103 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
104 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
105 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
106 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
107 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
109 #elif defined(CONFIG_ARCH_P3041)
110 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
111 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
112 #define CONFIG_SYS_NUM_FMAN 1
113 #define CONFIG_SYS_NUM_FM1_DTSEC 5
114 #define CONFIG_SYS_NUM_FM1_10GEC 1
115 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
116 #define CONFIG_SYS_FSL_TBCLK_DIV 32
117 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
118 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
119 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
120 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
121 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
122 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
123 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
124 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
125 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
127 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
128 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
129 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
130 #define CONFIG_SYS_NUM_FMAN 2
131 #define CONFIG_SYS_NUM_FM1_DTSEC 4
132 #define CONFIG_SYS_NUM_FM2_DTSEC 4
133 #define CONFIG_SYS_NUM_FM1_10GEC 1
134 #define CONFIG_SYS_NUM_FM2_10GEC 1
135 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
136 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
137 #define CONFIG_SYS_FSL_TBCLK_DIV 16
138 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
139 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
140 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
141 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
142 #define CONFIG_SYS_FSL_RMU
143 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
144 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
146 #elif defined(CONFIG_ARCH_P5040)
147 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
148 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
149 #define CONFIG_SYS_NUM_FMAN 2
150 #define CONFIG_SYS_NUM_FM1_DTSEC 5
151 #define CONFIG_SYS_NUM_FM1_10GEC 1
152 #define CONFIG_SYS_NUM_FM2_DTSEC 5
153 #define CONFIG_SYS_NUM_FM2_10GEC 1
154 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
155 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
156 #define CONFIG_SYS_FSL_TBCLK_DIV 16
157 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
158 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
159 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
160 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
161 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
163 #elif defined(CONFIG_ARCH_BSC9131)
164 #define CONFIG_FSL_SDHC_V2_3
165 #define CONFIG_TSECV2
166 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
167 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
168 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
169 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
170 #define CONFIG_NAND_FSL_IFC
171 #define CONFIG_ESDHC_HC_BLK_ADDR
173 #elif defined(CONFIG_ARCH_BSC9132)
174 #define CONFIG_FSL_SDHC_V2_3
175 #define CONFIG_TSECV2
176 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
177 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
178 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
179 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
180 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
181 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
182 #define CONFIG_NAND_FSL_IFC
183 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
184 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
185 #define CONFIG_ESDHC_HC_BLK_ADDR
187 #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
188 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
189 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
190 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
191 #ifdef CONFIG_ARCH_T4240
192 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
193 #define CONFIG_SYS_NUM_FM1_DTSEC 8
194 #define CONFIG_SYS_NUM_FM1_10GEC 2
195 #define CONFIG_SYS_NUM_FM2_DTSEC 8
196 #define CONFIG_SYS_NUM_FM2_10GEC 2
198 #define CONFIG_SYS_NUM_FM1_DTSEC 6
199 #define CONFIG_SYS_NUM_FM1_10GEC 1
200 #define CONFIG_SYS_NUM_FM2_DTSEC 8
201 #define CONFIG_SYS_NUM_FM2_10GEC 1
202 #if defined(CONFIG_ARCH_T4160)
203 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
206 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
207 #define CONFIG_SYS_FSL_SRDS_1
208 #define CONFIG_SYS_FSL_SRDS_2
209 #define CONFIG_SYS_FSL_SRDS_3
210 #define CONFIG_SYS_FSL_SRDS_4
211 #define CONFIG_SYS_NUM_FMAN 2
212 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
213 #define CONFIG_SYS_PME_CLK 0
214 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
215 #define CONFIG_SYS_FMAN_V3
216 #define CONFIG_SYS_FM1_CLK 3
217 #define CONFIG_SYS_FM2_CLK 3
218 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
219 #define CONFIG_SYS_FSL_TBCLK_DIV 16
220 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
221 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
222 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
223 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
224 #define CONFIG_SYS_FSL_SRIO_LIODN
225 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
226 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
227 #define CONFIG_SYS_FSL_SFP_VER_3_0
228 #define CONFIG_SYS_FSL_PCI_VER_3_X
230 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
231 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
232 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
233 #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
234 #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
235 #define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/
236 #define CONFIG_SYS_FSL_SRDS_1
237 #define CONFIG_SYS_FSL_SRDS_2
238 #define CONFIG_SYS_MAPLE
239 #define CONFIG_SYS_CPRI
240 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
241 #define CONFIG_SYS_NUM_FMAN 1
242 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
243 #define CONFIG_SYS_FM1_CLK 0
244 #define CONFIG_SYS_CPRI_CLK 3
245 #define CONFIG_SYS_ULB_CLK 4
246 #define CONFIG_SYS_ETVPE_CLK 1
247 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
248 #define CONFIG_SYS_FMAN_V3
249 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
250 #define CONFIG_SYS_FSL_TBCLK_DIV 16
251 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
252 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
253 #define CONFIG_SYS_FSL_SFP_VER_3_0
255 #ifdef CONFIG_ARCH_B4860
256 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
257 #define CONFIG_MAX_DSP_CPUS 12
258 #define CONFIG_NUM_DSP_CPUS 6
259 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
260 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
261 #define CONFIG_SYS_NUM_FM1_DTSEC 6
262 #define CONFIG_SYS_NUM_FM1_10GEC 2
263 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
264 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
265 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
266 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
267 #define CONFIG_SYS_FSL_SRIO_LIODN
269 #define CONFIG_MAX_DSP_CPUS 2
270 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
271 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
272 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
273 #define CONFIG_SYS_NUM_FM1_DTSEC 4
274 #define CONFIG_SYS_NUM_FM1_10GEC 0
277 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
279 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
280 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
281 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
282 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
283 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
284 #define CONFIG_SYS_FSL_SRDS_1
285 #define CONFIG_SYS_NUM_FMAN 1
286 #define CONFIG_SYS_NUM_FM1_DTSEC 5
287 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
288 #define CONFIG_PME_PLAT_CLK_DIV 2
289 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
290 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
291 #define CONFIG_SYS_FMAN_V3
292 #define CONFIG_FM_PLAT_CLK_DIV 1
293 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
294 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
295 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
296 #define CONFIG_SYS_FSL_TBCLK_DIV 16
297 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
298 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
299 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
300 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
301 #define QE_MURAM_SIZE 0x6000UL
302 #define MAX_QE_RISC 1
303 #define QE_NUM_OF_SNUM 28
304 #define CONFIG_SYS_FSL_SFP_VER_3_0
306 #elif defined(CONFIG_ARCH_T1024)
308 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
309 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
310 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
311 #define CONFIG_SYS_FMAN_V3
312 #define CONFIG_SYS_FSL_NUM_CC_PLL 2
313 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
314 #define CONFIG_SYS_FSL_SRDS_1
315 #define CONFIG_SYS_NUM_FMAN 1
316 #define CONFIG_SYS_NUM_FM1_DTSEC 4
317 #define CONFIG_SYS_NUM_FM1_10GEC 1
318 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
319 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
320 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
321 #define CONFIG_SYS_FM1_CLK 0
322 #define CONFIG_QBMAN_CLK_DIV 1
323 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
324 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
325 #define CONFIG_SYS_FSL_TBCLK_DIV 16
326 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
327 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
328 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
329 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
330 #define QE_MURAM_SIZE 0x6000UL
331 #define MAX_QE_RISC 1
332 #define QE_NUM_OF_SNUM 28
333 #define CONFIG_SYS_FSL_SFP_VER_3_0
335 #elif defined(CONFIG_ARCH_T2080)
336 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
337 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
338 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
339 #define CONFIG_SYS_FSL_QMAN_V3
340 #define CONFIG_SYS_NUM_FMAN 1
341 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
342 #define CONFIG_SYS_FSL_SRDS_1
343 #define CONFIG_SYS_FSL_PCI_VER_3_X
344 #if defined(CONFIG_ARCH_T2080)
345 #define CONFIG_SYS_NUM_FM1_DTSEC 8
346 #define CONFIG_SYS_NUM_FM1_10GEC 4
347 #define CONFIG_SYS_FSL_SRDS_2
348 #define CONFIG_SYS_FSL_SRIO_LIODN
349 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
350 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
351 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
353 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
354 #define CONFIG_PME_PLAT_CLK_DIV 1
355 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
356 #define CONFIG_SYS_FM1_CLK 0
357 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
358 #define CONFIG_SYS_FMAN_V3
359 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
360 #define CONFIG_SYS_FSL_TBCLK_DIV 16
361 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
362 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
363 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
364 #define CONFIG_SYS_FSL_SFP_VER_3_0
365 #define CONFIG_SYS_FSL_ISBC_VER 2
366 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
367 #define CONFIG_SYS_FSL_SFP_VER_3_0
370 #elif defined(CONFIG_ARCH_C29X)
371 #define CONFIG_FSL_SDHC_V2_3
372 #define CONFIG_TSECV2_1
373 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
374 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
375 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
379 #if !defined(CONFIG_ARCH_C29X)
380 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
383 #endif /* _ASM_MPC85xx_CONFIG_H_ */