1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
6 #ifndef _ASM_MPC85xx_CONFIG_H_
7 #define _ASM_MPC85xx_CONFIG_H_
9 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
12 * This macro should be removed when we no longer care about backwards
13 * compatibility with older operating systems.
15 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
17 #include <fsl_ddrc_version.h>
19 #if defined(CONFIG_ARCH_MPC8548)
20 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
21 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
22 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
23 #define CONFIG_SYS_FSL_RMU
24 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
26 #elif defined(CONFIG_ARCH_P1010)
27 #define CONFIG_FSL_SDHC_V2_3
29 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
30 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
31 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
32 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
34 /* P1011 is single core version of P1020 */
35 #elif defined(CONFIG_ARCH_P1011)
38 #elif defined(CONFIG_ARCH_P1020)
41 #elif defined(CONFIG_ARCH_P1021)
43 #define QE_MURAM_SIZE 0x6000UL
45 #define QE_NUM_OF_SNUM 28
47 #elif defined(CONFIG_ARCH_P1023)
48 #define CONFIG_SYS_NUM_FMAN 1
49 #define CONFIG_SYS_NUM_FM1_DTSEC 2
50 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
51 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
52 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
53 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
55 /* P1024 is lower end variant of P1020 */
56 #elif defined(CONFIG_ARCH_P1024)
59 /* P1025 is lower end variant of P1021 */
60 #elif defined(CONFIG_ARCH_P1025)
62 #define QE_MURAM_SIZE 0x6000UL
64 #define QE_NUM_OF_SNUM 28
66 #elif defined(CONFIG_ARCH_P2020)
67 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
68 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
69 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
70 #define CONFIG_SYS_FSL_RMU
71 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
73 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
74 #define CONFIG_SYS_NUM_FMAN 1
75 #define CONFIG_SYS_NUM_FM1_DTSEC 5
76 #define CONFIG_SYS_NUM_FM1_10GEC 1
77 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
78 #define CONFIG_SYS_FSL_TBCLK_DIV 32
79 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
80 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
81 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
82 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
83 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
84 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
85 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
86 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
88 #elif defined(CONFIG_ARCH_P3041)
89 #define CONFIG_SYS_NUM_FMAN 1
90 #define CONFIG_SYS_NUM_FM1_DTSEC 5
91 #define CONFIG_SYS_NUM_FM1_10GEC 1
92 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
93 #define CONFIG_SYS_FSL_TBCLK_DIV 32
94 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
95 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
96 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
97 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
98 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
99 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
100 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
101 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
103 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
104 #define CONFIG_SYS_NUM_FMAN 2
105 #define CONFIG_SYS_NUM_FM1_DTSEC 4
106 #define CONFIG_SYS_NUM_FM2_DTSEC 4
107 #define CONFIG_SYS_NUM_FM1_10GEC 1
108 #define CONFIG_SYS_NUM_FM2_10GEC 1
109 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
110 #define CONFIG_SYS_FSL_TBCLK_DIV 16
111 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
112 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
113 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
114 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
115 #define CONFIG_SYS_FSL_RMU
116 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
117 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
119 #elif defined(CONFIG_ARCH_P5040)
120 #define CONFIG_SYS_NUM_FMAN 2
121 #define CONFIG_SYS_NUM_FM1_DTSEC 5
122 #define CONFIG_SYS_NUM_FM1_10GEC 1
123 #define CONFIG_SYS_NUM_FM2_DTSEC 5
124 #define CONFIG_SYS_NUM_FM2_10GEC 1
125 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
126 #define CONFIG_SYS_FSL_TBCLK_DIV 16
127 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
128 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
129 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
130 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
131 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
133 #elif defined(CONFIG_ARCH_BSC9131)
134 #define CONFIG_FSL_SDHC_V2_3
135 #define CONFIG_TSECV2
136 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
138 #elif defined(CONFIG_ARCH_BSC9132)
139 #define CONFIG_FSL_SDHC_V2_3
140 #define CONFIG_TSECV2
141 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
142 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
144 #elif defined(CONFIG_ARCH_T4240)
145 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
146 #ifdef CONFIG_ARCH_T4240
147 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
148 #define CONFIG_SYS_NUM_FM1_DTSEC 8
149 #define CONFIG_SYS_NUM_FM1_10GEC 2
150 #define CONFIG_SYS_NUM_FM2_DTSEC 8
151 #define CONFIG_SYS_NUM_FM2_10GEC 2
153 #define CONFIG_SYS_NUM_FM1_DTSEC 6
154 #define CONFIG_SYS_NUM_FM1_10GEC 1
155 #define CONFIG_SYS_NUM_FM2_DTSEC 8
156 #define CONFIG_SYS_NUM_FM2_10GEC 1
158 #define CONFIG_SYS_FSL_SRDS_1
159 #define CONFIG_SYS_FSL_SRDS_2
160 #define CONFIG_SYS_FSL_SRDS_3
161 #define CONFIG_SYS_FSL_SRDS_4
162 #define CONFIG_SYS_NUM_FMAN 2
163 #define CONFIG_SYS_PME_CLK 0
164 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
165 #define CONFIG_SYS_FM1_CLK 3
166 #define CONFIG_SYS_FM2_CLK 3
167 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
168 #define CONFIG_SYS_FSL_TBCLK_DIV 16
169 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
170 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
171 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
172 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
173 #define CONFIG_SYS_FSL_SRIO_LIODN
174 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
175 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
177 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
178 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
179 #define CONFIG_SYS_FSL_SRDS_1
180 #define CONFIG_SYS_FSL_SRDS_2
181 #define CONFIG_SYS_NUM_FMAN 1
182 #define CONFIG_SYS_FM1_CLK 0
183 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
184 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
185 #define CONFIG_SYS_FSL_TBCLK_DIV 16
186 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
187 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
189 #ifdef CONFIG_ARCH_B4860
190 #define CONFIG_MAX_DSP_CPUS 12
191 #define CONFIG_NUM_DSP_CPUS 6
192 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
193 #define CONFIG_SYS_NUM_FM1_DTSEC 6
194 #define CONFIG_SYS_NUM_FM1_10GEC 2
195 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
196 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
197 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
198 #define CONFIG_SYS_FSL_SRIO_LIODN
200 #define CONFIG_MAX_DSP_CPUS 2
201 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
202 #define CONFIG_SYS_NUM_FM1_DTSEC 4
203 #define CONFIG_SYS_NUM_FM1_10GEC 0
206 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
207 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
208 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
209 #define CONFIG_SYS_FSL_SRDS_1
210 #define CONFIG_SYS_NUM_FMAN 1
211 #define CONFIG_SYS_NUM_FM1_DTSEC 5
212 #define CONFIG_PME_PLAT_CLK_DIV 2
213 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
214 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
215 #define CONFIG_FM_PLAT_CLK_DIV 1
216 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
217 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
218 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
219 #define CONFIG_SYS_FSL_TBCLK_DIV 16
220 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
221 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
222 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
223 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
224 #define QE_MURAM_SIZE 0x6000UL
225 #define MAX_QE_RISC 1
226 #define QE_NUM_OF_SNUM 28
228 #elif defined(CONFIG_ARCH_T1024)
229 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
230 #define CONFIG_SYS_FSL_NUM_CC_PLL 2
231 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
232 #define CONFIG_SYS_FSL_SRDS_1
233 #define CONFIG_SYS_NUM_FMAN 1
234 #define CONFIG_SYS_NUM_FM1_DTSEC 4
235 #define CONFIG_SYS_NUM_FM1_10GEC 1
236 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
237 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
238 #define CONFIG_SYS_FM1_CLK 0
239 #define CONFIG_QBMAN_CLK_DIV 1
240 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
241 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
242 #define CONFIG_SYS_FSL_TBCLK_DIV 16
243 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
244 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
245 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
246 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
247 #define QE_MURAM_SIZE 0x6000UL
248 #define MAX_QE_RISC 1
249 #define QE_NUM_OF_SNUM 28
251 #elif defined(CONFIG_ARCH_T2080)
252 #define CONFIG_SYS_FSL_QMAN_V3
253 #define CONFIG_SYS_NUM_FMAN 1
254 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
255 #define CONFIG_SYS_FSL_SRDS_1
256 #if defined(CONFIG_ARCH_T2080)
257 #define CONFIG_SYS_NUM_FM1_DTSEC 8
258 #define CONFIG_SYS_NUM_FM1_10GEC 4
259 #define CONFIG_SYS_FSL_SRDS_2
260 #define CONFIG_SYS_FSL_SRIO_LIODN
261 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
262 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
263 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
265 #define CONFIG_PME_PLAT_CLK_DIV 1
266 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
267 #define CONFIG_SYS_FM1_CLK 0
268 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
269 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
270 #define CONFIG_SYS_FSL_TBCLK_DIV 16
271 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
272 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
273 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
274 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
277 #elif defined(CONFIG_ARCH_C29X)
278 #define CONFIG_FSL_SDHC_V2_3
279 #define CONFIG_TSECV2_1
280 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
281 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
285 #endif /* _ASM_MPC85xx_CONFIG_H_ */