1 #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
2 #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
5 * Common bits between hash and Radix page table
7 #define _PAGE_BIT_SWAP_TYPE 0
11 #define _PAGE_EXEC 0x00001 /* execute permission */
12 #define _PAGE_WRITE 0x00002 /* write access allowed */
13 #define _PAGE_READ 0x00004 /* read access allowed */
14 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE)
15 #define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)
16 #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */
17 #define _PAGE_SAO 0x00010 /* Strong access order */
18 #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */
19 #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */
20 #define _PAGE_DIRTY 0x00080 /* C: page changed */
21 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */
25 #define _RPAGE_SW0 0x2000000000000000UL
26 #define _RPAGE_SW1 0x00800
27 #define _RPAGE_SW2 0x00400
28 #define _RPAGE_SW3 0x00200
29 #define _RPAGE_RSV1 0x1000000000000000UL
30 #define _RPAGE_RSV2 0x0800000000000000UL
31 #define _RPAGE_RSV3 0x0400000000000000UL
32 #define _RPAGE_RSV4 0x0200000000000000UL
34 #ifdef CONFIG_MEM_SOFT_DIRTY
35 #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */
37 #define _PAGE_SOFT_DIRTY 0x00000
39 #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */
42 * For P9 DD1 only, we need to track whether the pte's huge.
44 #define _PAGE_LARGE _RPAGE_RSV1
47 #define _PAGE_PTE (1ul << 62) /* distinguishes PTEs from pointers */
48 #define _PAGE_PRESENT (1ul << 63) /* pte contains a translation */
50 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE
51 * Instead of fixing all of them, add an alternate define which
52 * maps CI pte mapping.
54 #define _PAGE_NO_CACHE _PAGE_TOLERANT
56 * We support 57 bit real address in pte. Clear everything above 57, and
57 * every thing below PAGE_SHIFT;
59 #define PTE_RPN_MASK (((1UL << 57) - 1) & (PAGE_MASK))
61 * set of bits not changed in pmd_modify. Even though we have hash specific bits
62 * in here, on radix we expect them to be zero.
64 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
65 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \
68 * user access blocked by key
70 #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY)
71 #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ)
72 #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \
73 _PAGE_RW | _PAGE_EXEC)
75 * No page size encoding in the linux PTE
79 * _PAGE_CHG_MASK masks of bits that are to be preserved across
82 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
83 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \
86 * Mask of bits returned by pte_pgprot()
88 #define PAGE_PROT_BITS (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT | \
89 H_PAGE_4K_PFN | _PAGE_PRIVILEGED | _PAGE_ACCESSED | \
90 _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_EXEC | \
93 * We define 2 sets of base prot bits, one for basic pages (ie,
94 * cacheable kernel and user pages) and one for non cacheable
95 * pages. We always set _PAGE_COHERENT when SMP is enabled or
96 * the processor might need it for DMA coherency.
98 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE)
99 #define _PAGE_BASE (_PAGE_BASE_NC)
101 /* Permission masks used to generate the __P and __S table,
103 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h
105 * Write permissions imply read permissions for now (we could make write-only
106 * pages on BookE but we don't bother for now). Execute permission control is
107 * possible on platforms that define _PAGE_EXEC
109 * Note due to the way vm flags are laid out, the bits are XWR
111 #define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED)
112 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW)
113 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC)
114 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ)
115 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
116 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ)
117 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
119 #define __P000 PAGE_NONE
120 #define __P001 PAGE_READONLY
121 #define __P010 PAGE_COPY
122 #define __P011 PAGE_COPY
123 #define __P100 PAGE_READONLY_X
124 #define __P101 PAGE_READONLY_X
125 #define __P110 PAGE_COPY_X
126 #define __P111 PAGE_COPY_X
128 #define __S000 PAGE_NONE
129 #define __S001 PAGE_READONLY
130 #define __S010 PAGE_SHARED
131 #define __S011 PAGE_SHARED
132 #define __S100 PAGE_READONLY_X
133 #define __S101 PAGE_READONLY_X
134 #define __S110 PAGE_SHARED_X
135 #define __S111 PAGE_SHARED_X
137 /* Permission masks used for kernel mappings */
138 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
139 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
141 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
142 _PAGE_NON_IDEMPOTENT)
143 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)
144 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
145 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
148 * Protection used for kernel text. We want the debuggers to be able to
149 * set breakpoints anywhere, so don't write protect the kernel text
150 * on platforms where such control is possible.
152 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \
153 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE)
154 #define PAGE_KERNEL_TEXT PAGE_KERNEL_X
156 #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX
159 /* Make modules code happy. We don't set RO yet */
160 #define PAGE_KERNEL_EXEC PAGE_KERNEL_X
161 #define PAGE_AGP (PAGE_KERNEL_NC)
167 extern unsigned long __pte_index_size;
168 extern unsigned long __pmd_index_size;
169 extern unsigned long __pud_index_size;
170 extern unsigned long __pgd_index_size;
171 extern unsigned long __pmd_cache_index;
172 #define PTE_INDEX_SIZE __pte_index_size
173 #define PMD_INDEX_SIZE __pmd_index_size
174 #define PUD_INDEX_SIZE __pud_index_size
175 #define PGD_INDEX_SIZE __pgd_index_size
176 #define PMD_CACHE_INDEX __pmd_cache_index
178 * Because of use of pte fragments and THP, size of page table
179 * are not always derived out of index size above.
181 extern unsigned long __pte_table_size;
182 extern unsigned long __pmd_table_size;
183 extern unsigned long __pud_table_size;
184 extern unsigned long __pgd_table_size;
185 #define PTE_TABLE_SIZE __pte_table_size
186 #define PMD_TABLE_SIZE __pmd_table_size
187 #define PUD_TABLE_SIZE __pud_table_size
188 #define PGD_TABLE_SIZE __pgd_table_size
190 extern unsigned long __pmd_val_bits;
191 extern unsigned long __pud_val_bits;
192 extern unsigned long __pgd_val_bits;
193 #define PMD_VAL_BITS __pmd_val_bits
194 #define PUD_VAL_BITS __pud_val_bits
195 #define PGD_VAL_BITS __pgd_val_bits
197 extern unsigned long __pte_frag_nr;
198 #define PTE_FRAG_NR __pte_frag_nr
199 extern unsigned long __pte_frag_size_shift;
200 #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift
201 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT)
203 * Pgtable size used by swapper, init in asm code
205 #define MAX_PGD_TABLE_SIZE (sizeof(pgd_t) << RADIX_PGD_INDEX_SIZE)
207 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
208 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
209 #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE)
210 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
212 /* PMD_SHIFT determines what a second-level page table entry can map */
213 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
214 #define PMD_SIZE (1UL << PMD_SHIFT)
215 #define PMD_MASK (~(PMD_SIZE-1))
217 /* PUD_SHIFT determines what a third-level page table entry can map */
218 #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
219 #define PUD_SIZE (1UL << PUD_SHIFT)
220 #define PUD_MASK (~(PUD_SIZE-1))
222 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */
223 #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE)
224 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
225 #define PGDIR_MASK (~(PGDIR_SIZE-1))
227 /* Bits to mask out from a PMD to get to the PTE page */
228 #define PMD_MASKED_BITS 0xc0000000000000ffUL
229 /* Bits to mask out from a PUD to get to the PMD page */
230 #define PUD_MASKED_BITS 0xc0000000000000ffUL
231 /* Bits to mask out from a PGD to get to the PUD page */
232 #define PGD_MASKED_BITS 0xc0000000000000ffUL
234 extern unsigned long __vmalloc_start;
235 extern unsigned long __vmalloc_end;
236 #define VMALLOC_START __vmalloc_start
237 #define VMALLOC_END __vmalloc_end
239 extern unsigned long __kernel_virt_start;
240 extern unsigned long __kernel_virt_size;
241 #define KERN_VIRT_START __kernel_virt_start
242 #define KERN_VIRT_SIZE __kernel_virt_size
243 extern struct page *vmemmap;
244 extern unsigned long ioremap_bot;
245 extern unsigned long pci_io_base;
246 #endif /* __ASSEMBLY__ */
248 #include <asm/book3s/64/hash.h>
249 #include <asm/book3s/64/radix.h>
251 #ifdef CONFIG_PPC_64K_PAGES
252 #include <asm/book3s/64/pgtable-64k.h>
254 #include <asm/book3s/64/pgtable-4k.h>
257 #include <asm/barrier.h>
259 * The second half of the kernel virtual space is used for IO mappings,
260 * it's itself carved into the PIO region (ISA and PHB IO space) and
263 * ISA_IO_BASE = KERN_IO_START, 64K reserved area
264 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
265 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
267 #define KERN_IO_START (KERN_VIRT_START + (KERN_VIRT_SIZE >> 1))
268 #define FULL_IO_SIZE 0x80000000ul
269 #define ISA_IO_BASE (KERN_IO_START)
270 #define ISA_IO_END (KERN_IO_START + 0x10000ul)
271 #define PHB_IO_BASE (ISA_IO_END)
272 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE)
273 #define IOREMAP_BASE (PHB_IO_END)
274 #define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE)
276 /* Advertise special mapping type for AGP */
277 #define HAVE_PAGE_AGP
279 /* Advertise support for _PAGE_SPECIAL */
280 #define __HAVE_ARCH_PTE_SPECIAL
285 * This is the default implementation of various PTE accessors, it's
286 * used in all cases except Book3S with 64K pages where we have a
287 * concept of sub-pages
291 #define __real_pte(e,p) ((real_pte_t){(e)})
292 #define __rpte_to_pte(r) ((r).pte)
293 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT)
295 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
298 shift = mmu_psize_defs[psize].shift; \
300 #define pte_iterate_hashed_end() } while(0)
303 * We expect this to be called only for user addresses or kernel virtual
304 * addresses other than the linear mapping.
306 #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K
308 #endif /* __real_pte */
310 static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr,
311 pte_t *ptep, unsigned long clr,
312 unsigned long set, int huge)
315 return radix__pte_update(mm, addr, ptep, clr, set, huge);
316 return hash__pte_update(mm, addr, ptep, clr, set, huge);
319 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update.
320 * We currently remove entries from the hashtable regardless of whether
321 * the entry was young or dirty.
323 * We should be more intelligent about this but for the moment we override
324 * these functions and force a tlb flush unconditionally
325 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same
326 * function for both hash and radix.
328 static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
329 unsigned long addr, pte_t *ptep)
333 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
335 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0);
336 return (old & _PAGE_ACCESSED) != 0;
339 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
340 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \
343 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
347 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
348 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
351 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_WRITE)) == 0)
354 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0);
357 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
358 unsigned long addr, pte_t *ptep)
360 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_WRITE)) == 0)
363 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1);
366 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
367 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
368 unsigned long addr, pte_t *ptep)
370 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0);
374 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
375 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
377 pte_t *ptep, int full)
379 if (full && radix_enabled()) {
381 * Let's skip the DD1 style pte update here. We know that
382 * this is a full mm pte clear and hence can be sure there is
383 * no parallel set_pte.
385 return radix__ptep_get_and_clear_full(mm, addr, ptep, full);
387 return ptep_get_and_clear(mm, addr, ptep);
391 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
394 pte_update(mm, addr, ptep, ~0UL, 0, 0);
397 static inline int pte_write(pte_t pte)
399 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE));
402 static inline int pte_dirty(pte_t pte)
404 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY));
407 static inline int pte_young(pte_t pte)
409 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED));
412 static inline int pte_special(pte_t pte)
414 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL));
417 static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }
419 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
420 static inline bool pte_soft_dirty(pte_t pte)
422 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY));
425 static inline pte_t pte_mksoft_dirty(pte_t pte)
427 return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
430 static inline pte_t pte_clear_soft_dirty(pte_t pte)
432 return __pte(pte_val(pte) & ~_PAGE_SOFT_DIRTY);
434 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
436 #ifdef CONFIG_NUMA_BALANCING
438 * These work without NUMA balancing but the kernel does not care. See the
439 * comment in include/asm-generic/pgtable.h . On powerpc, this will only
440 * work for user pages and always return true for kernel pages.
442 static inline int pte_protnone(pte_t pte)
444 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED)) ==
445 cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED);
447 #endif /* CONFIG_NUMA_BALANCING */
449 static inline int pte_present(pte_t pte)
451 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT));
454 * Conversion functions: convert a page and protection to a page entry,
455 * and a page entry and page directory to the page they refer to.
457 * Even if PTEs can be unsigned long long, a PFN is always an unsigned
460 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
462 return __pte((((pte_basic_t)(pfn) << PAGE_SHIFT) & PTE_RPN_MASK) |
466 static inline unsigned long pte_pfn(pte_t pte)
468 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT;
471 /* Generic modifiers for PTE bits */
472 static inline pte_t pte_wrprotect(pte_t pte)
474 return __pte(pte_val(pte) & ~_PAGE_WRITE);
477 static inline pte_t pte_mkclean(pte_t pte)
479 return __pte(pte_val(pte) & ~_PAGE_DIRTY);
482 static inline pte_t pte_mkold(pte_t pte)
484 return __pte(pte_val(pte) & ~_PAGE_ACCESSED);
487 static inline pte_t pte_mkwrite(pte_t pte)
490 * write implies read, hence set both
492 return __pte(pte_val(pte) | _PAGE_RW);
495 static inline pte_t pte_mkdirty(pte_t pte)
497 return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
500 static inline pte_t pte_mkyoung(pte_t pte)
502 return __pte(pte_val(pte) | _PAGE_ACCESSED);
505 static inline pte_t pte_mkspecial(pte_t pte)
507 return __pte(pte_val(pte) | _PAGE_SPECIAL);
510 static inline pte_t pte_mkhuge(pte_t pte)
515 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
517 /* FIXME!! check whether this need to be a conditional */
518 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
521 static inline bool pte_user(pte_t pte)
523 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED));
526 /* Encode and de-code a swap entry */
527 #define MAX_SWAPFILES_CHECK() do { \
528 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \
530 * Don't have overlapping bits with _PAGE_HPTEFLAGS \
531 * We filter HPTEFLAGS on set_pte. \
533 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \
534 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \
537 * on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT;
539 #define SWP_TYPE_BITS 5
540 #define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \
541 & ((1UL << SWP_TYPE_BITS) - 1))
542 #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT)
543 #define __swp_entry(type, offset) ((swp_entry_t) { \
544 ((type) << _PAGE_BIT_SWAP_TYPE) \
545 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)})
547 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from
548 * swap type and offset we get from swap and convert that to pte to find a
549 * matching pte in linux page table.
550 * Clear bits not found in swap entries here.
552 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE })
553 #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE)
555 #ifdef CONFIG_MEM_SOFT_DIRTY
556 #define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE))
558 #define _PAGE_SWP_SOFT_DIRTY 0UL
559 #endif /* CONFIG_MEM_SOFT_DIRTY */
561 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
562 static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
564 return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
567 static inline bool pte_swp_soft_dirty(pte_t pte)
569 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY));
572 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
574 return __pte(pte_val(pte) & ~_PAGE_SWP_SOFT_DIRTY);
576 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
578 static inline bool check_pte_access(unsigned long access, unsigned long ptev)
581 * This check for _PAGE_RWX and _PAGE_PRESENT bits
586 * This check for access to privilege space
588 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED))
594 * Generic functions with hash/radix callbacks
597 static inline void __ptep_set_access_flags(struct mm_struct *mm,
598 pte_t *ptep, pte_t entry,
599 unsigned long address)
602 return radix__ptep_set_access_flags(mm, ptep, entry, address);
603 return hash__ptep_set_access_flags(ptep, entry);
606 #define __HAVE_ARCH_PTE_SAME
607 static inline int pte_same(pte_t pte_a, pte_t pte_b)
610 return radix__pte_same(pte_a, pte_b);
611 return hash__pte_same(pte_a, pte_b);
614 static inline int pte_none(pte_t pte)
617 return radix__pte_none(pte);
618 return hash__pte_none(pte);
621 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
622 pte_t *ptep, pte_t pte, int percpu)
625 return radix__set_pte_at(mm, addr, ptep, pte, percpu);
626 return hash__set_pte_at(mm, addr, ptep, pte, percpu);
629 #define _PAGE_CACHE_CTL (_PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT)
631 #define pgprot_noncached pgprot_noncached
632 static inline pgprot_t pgprot_noncached(pgprot_t prot)
634 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
635 _PAGE_NON_IDEMPOTENT);
638 #define pgprot_noncached_wc pgprot_noncached_wc
639 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot)
641 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
645 #define pgprot_cached pgprot_cached
646 static inline pgprot_t pgprot_cached(pgprot_t prot)
648 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL));
651 #define pgprot_writecombine pgprot_writecombine
652 static inline pgprot_t pgprot_writecombine(pgprot_t prot)
654 return pgprot_noncached_wc(prot);
657 * check a pte mapping have cache inhibited property
659 static inline bool pte_ci(pte_t pte)
661 unsigned long pte_v = pte_val(pte);
663 if (((pte_v & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) ||
664 ((pte_v & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT))
669 static inline void pmd_set(pmd_t *pmdp, unsigned long val)
674 static inline void pmd_clear(pmd_t *pmdp)
679 static inline int pmd_none(pmd_t pmd)
681 return !pmd_raw(pmd);
684 static inline int pmd_present(pmd_t pmd)
687 return !pmd_none(pmd);
690 static inline int pmd_bad(pmd_t pmd)
693 return radix__pmd_bad(pmd);
694 return hash__pmd_bad(pmd);
697 static inline void pud_set(pud_t *pudp, unsigned long val)
702 static inline void pud_clear(pud_t *pudp)
707 static inline int pud_none(pud_t pud)
709 return !pud_raw(pud);
712 static inline int pud_present(pud_t pud)
714 return !pud_none(pud);
717 extern struct page *pud_page(pud_t pud);
718 extern struct page *pmd_page(pmd_t pmd);
719 static inline pte_t pud_pte(pud_t pud)
721 return __pte_raw(pud_raw(pud));
724 static inline pud_t pte_pud(pte_t pte)
726 return __pud_raw(pte_raw(pte));
728 #define pud_write(pud) pte_write(pud_pte(pud))
730 static inline int pud_bad(pud_t pud)
733 return radix__pud_bad(pud);
734 return hash__pud_bad(pud);
738 #define pgd_write(pgd) pte_write(pgd_pte(pgd))
739 static inline void pgd_set(pgd_t *pgdp, unsigned long val)
744 static inline void pgd_clear(pgd_t *pgdp)
749 static inline int pgd_none(pgd_t pgd)
751 return !pgd_raw(pgd);
754 static inline int pgd_present(pgd_t pgd)
756 return !pgd_none(pgd);
759 static inline pte_t pgd_pte(pgd_t pgd)
761 return __pte_raw(pgd_raw(pgd));
764 static inline pgd_t pte_pgd(pte_t pte)
766 return __pgd_raw(pte_raw(pte));
769 static inline int pgd_bad(pgd_t pgd)
772 return radix__pgd_bad(pgd);
773 return hash__pgd_bad(pgd);
776 extern struct page *pgd_page(pgd_t pgd);
778 /* Pointers in the page table tree are physical addresses */
779 #define __pgtable_ptr_val(ptr) __pa(ptr)
781 #define pmd_page_vaddr(pmd) __va(pmd_val(pmd) & ~PMD_MASKED_BITS)
782 #define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS)
783 #define pgd_page_vaddr(pgd) __va(pgd_val(pgd) & ~PGD_MASKED_BITS)
785 #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1))
786 #define pud_index(address) (((address) >> (PUD_SHIFT)) & (PTRS_PER_PUD - 1))
787 #define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1))
788 #define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1))
791 * Find an entry in a page-table-directory. We combine the address region
792 * (the high order N bits) and the pgd portion of the address.
795 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
797 #define pud_offset(pgdp, addr) \
798 (((pud_t *) pgd_page_vaddr(*(pgdp))) + pud_index(addr))
799 #define pmd_offset(pudp,addr) \
800 (((pmd_t *) pud_page_vaddr(*(pudp))) + pmd_index(addr))
801 #define pte_offset_kernel(dir,addr) \
802 (((pte_t *) pmd_page_vaddr(*(dir))) + pte_index(addr))
804 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
805 #define pte_unmap(pte) do { } while(0)
807 /* to find an entry in a kernel page-table-directory */
808 /* This now only contains the vmalloc pages */
809 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
811 #define pte_ERROR(e) \
812 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
813 #define pmd_ERROR(e) \
814 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
815 #define pud_ERROR(e) \
816 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
817 #define pgd_ERROR(e) \
818 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
820 static inline int map_kernel_page(unsigned long ea, unsigned long pa,
823 if (radix_enabled()) {
824 #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM)
825 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift;
826 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE");
828 return radix__map_kernel_page(ea, pa, __pgprot(flags), PAGE_SIZE);
830 return hash__map_kernel_page(ea, pa, flags);
833 static inline int __meminit vmemmap_create_mapping(unsigned long start,
834 unsigned long page_size,
838 return radix__vmemmap_create_mapping(start, page_size, phys);
839 return hash__vmemmap_create_mapping(start, page_size, phys);
842 #ifdef CONFIG_MEMORY_HOTPLUG
843 static inline void vmemmap_remove_mapping(unsigned long start,
844 unsigned long page_size)
847 return radix__vmemmap_remove_mapping(start, page_size);
848 return hash__vmemmap_remove_mapping(start, page_size);
851 struct page *realmode_pfn_to_page(unsigned long pfn);
853 static inline pte_t pmd_pte(pmd_t pmd)
855 return __pte_raw(pmd_raw(pmd));
858 static inline pmd_t pte_pmd(pte_t pte)
860 return __pmd_raw(pte_raw(pte));
863 static inline pte_t *pmdp_ptep(pmd_t *pmd)
867 #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd))
868 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
869 #define pmd_young(pmd) pte_young(pmd_pte(pmd))
870 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
871 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
872 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
873 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
874 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
875 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
877 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
878 #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd))
879 #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)))
880 #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)))
881 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
883 #ifdef CONFIG_NUMA_BALANCING
884 static inline int pmd_protnone(pmd_t pmd)
886 return pte_protnone(pmd_pte(pmd));
888 #endif /* CONFIG_NUMA_BALANCING */
890 #define __HAVE_ARCH_PMD_WRITE
891 #define pmd_write(pmd) pte_write(pmd_pte(pmd))
893 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
894 extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot);
895 extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot);
896 extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot);
897 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr,
898 pmd_t *pmdp, pmd_t pmd);
899 extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
901 extern int hash__has_transparent_hugepage(void);
902 static inline int has_transparent_hugepage(void)
905 return radix__has_transparent_hugepage();
906 return hash__has_transparent_hugepage();
908 #define has_transparent_hugepage has_transparent_hugepage
910 static inline unsigned long
911 pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp,
912 unsigned long clr, unsigned long set)
915 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set);
916 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set);
919 static inline int pmd_large(pmd_t pmd)
921 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE));
924 static inline pmd_t pmd_mknotpresent(pmd_t pmd)
926 return __pmd(pmd_val(pmd) & ~_PAGE_PRESENT);
929 * For radix we should always find H_PAGE_HASHPTE zero. Hence
930 * the below will work for radix too
932 static inline int __pmdp_test_and_clear_young(struct mm_struct *mm,
933 unsigned long addr, pmd_t *pmdp)
937 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
939 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0);
940 return ((old & _PAGE_ACCESSED) != 0);
943 #define __HAVE_ARCH_PMDP_SET_WRPROTECT
944 static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr,
948 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_WRITE)) == 0)
951 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0);
954 static inline int pmd_trans_huge(pmd_t pmd)
957 return radix__pmd_trans_huge(pmd);
958 return hash__pmd_trans_huge(pmd);
961 #define __HAVE_ARCH_PMD_SAME
962 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b)
965 return radix__pmd_same(pmd_a, pmd_b);
966 return hash__pmd_same(pmd_a, pmd_b);
969 static inline pmd_t pmd_mkhuge(pmd_t pmd)
972 return radix__pmd_mkhuge(pmd);
973 return hash__pmd_mkhuge(pmd);
976 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
977 extern int pmdp_set_access_flags(struct vm_area_struct *vma,
978 unsigned long address, pmd_t *pmdp,
979 pmd_t entry, int dirty);
981 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
982 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma,
983 unsigned long address, pmd_t *pmdp);
985 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
986 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
987 unsigned long addr, pmd_t *pmdp)
990 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp);
991 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp);
994 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
995 unsigned long address, pmd_t *pmdp)
998 return radix__pmdp_collapse_flush(vma, address, pmdp);
999 return hash__pmdp_collapse_flush(vma, address, pmdp);
1001 #define pmdp_collapse_flush pmdp_collapse_flush
1003 #define __HAVE_ARCH_PGTABLE_DEPOSIT
1004 static inline void pgtable_trans_huge_deposit(struct mm_struct *mm,
1005 pmd_t *pmdp, pgtable_t pgtable)
1007 if (radix_enabled())
1008 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable);
1009 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable);
1012 #define __HAVE_ARCH_PGTABLE_WITHDRAW
1013 static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm,
1016 if (radix_enabled())
1017 return radix__pgtable_trans_huge_withdraw(mm, pmdp);
1018 return hash__pgtable_trans_huge_withdraw(mm, pmdp);
1021 #define __HAVE_ARCH_PMDP_INVALIDATE
1022 extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
1025 #define __HAVE_ARCH_PMDP_HUGE_SPLIT_PREPARE
1026 static inline void pmdp_huge_split_prepare(struct vm_area_struct *vma,
1027 unsigned long address, pmd_t *pmdp)
1029 if (radix_enabled())
1030 return radix__pmdp_huge_split_prepare(vma, address, pmdp);
1031 return hash__pmdp_huge_split_prepare(vma, address, pmdp);
1034 #define pmd_move_must_withdraw pmd_move_must_withdraw
1036 static inline int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl,
1037 struct spinlock *old_pmd_ptl,
1038 struct vm_area_struct *vma)
1040 if (radix_enabled())
1043 * Archs like ppc64 use pgtable to store per pmd
1044 * specific information. So when we switch the pmd,
1045 * we should also withdraw and deposit the pgtable
1051 #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit
1052 static inline bool arch_needs_pgtable_deposit(void)
1054 if (radix_enabled())
1059 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1060 #endif /* __ASSEMBLY__ */
1061 #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */