arch/powerpc/dts/t1024rdb.dts

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * T1024RDB Device Tree Source
   4  *
   5  * Copyright 2013 - 2015 Freescale Semiconductor Inc.
   6  * Copyright 2019-2020 NXP
   7  */
   8
   9 /include/ "t102x.dtsi"
  10
  11 / {
  12         model = "fsl,T1024RDB";
  13         compatible = "fsl,T1024RDB";
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16         interrupt-parent = <&mpic>;
  17
  18         aliases {
  19                 sg_2500_aqr105_phy4 = &sg_2500_aqr105_phy4;
  20                 spi0 = &espi0;
  21         };
  22
  23         soc: soc@ffe000000 {
  24                 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  25                 reg = <0xf 0xfe000000 0 0x00001000>;
  26
  27                 fman@400000 {
  28                         fm1mac1: ethernet@e0000 {
  29                                 phy-handle = <&xg_aqr105_phy3>;
  30                                 phy-connection-type = "xgmii";
  31                         };
  32
  33                         fm1mac2: ethernet@e2000 {
  34                         };
  35
  36                         fm1mac3: ethernet@e4000 {
  37                                 phy-handle = <&rgmii_phy2>;
  38                                 phy-connection-type = "rgmii";
  39                         };
  40
  41                         fm1mac4: ethernet@e6000 {
  42                                 phy-handle = <&rgmii_phy1>;
  43                                 phy-connection-type = "rgmii";
  44                         };
  45
  46                         mdio0: mdio@fc000 {
  47                                 rgmii_phy1: ethernet-phy@2 {
  48                                         reg = <0x2>;
  49                                 };
  50                                 rgmii_phy2: ethernet-phy@6 {
  51                                         reg = <0x6>;
  52                                 };
  53                         };
  54
  55                         xmdio0: mdio@fd000 {
  56                                 xg_aqr105_phy3: ethernet-phy@1 {
  57                                         compatible = "ethernet-phy-ieee802.3-c45";
  58                                         reg = <0x1>;
  59                                 };
  60                                 sg_2500_aqr105_phy4: ethernet-phy@2 {
  61                                         compatible = "ethernet-phy-ieee802.3-c45";
  62                                         reg = <0x2>;
  63                                 };
  64                         };
  65                 };
  66         };
  67 };
  68
  69 &espi0 {
  70         status = "okay";
  71         flash@0 {
  72                 compatible = "jedec,spi-nor";
  73                 #address-cells = <1>;
  74                 #size-cells = <1>;
  75                 reg = <0>;
  76                 /* input clock */
  77                 spi-max-frequency = <10000000>;
  78         };
  79 };
  80
  81 #include "t1024si-post.dtsi"