arch/powerpc/dts/p5040ds.dts

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * P5040DS Device Tree Source
   4  *
   5  * Copyright 2012 - 2015 Freescale Semiconductor Inc.
   6  * Copyright 2019-2020 NXP
   7  */
   8
   9 /include/ "p5040.dtsi"
  10
  11 / {
  12         model = "fsl,P5040DS";
  13         compatible = "fsl,P5040DS";
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16         interrupt-parent = <&mpic>;
  17
  18         aliases{
  19                 phy_sgmii_slot2_1c = &phy_sgmii_slot2_1c;
  20                 phy_sgmii_slot2_1d = &phy_sgmii_slot2_1d;
  21                 phy_sgmii_slot2_1e = &phy_sgmii_slot2_1e;
  22                 phy_sgmii_slot2_1f = &phy_sgmii_slot2_1f;
  23                 phy_sgmii_slot3_1c = &phy_sgmii_slot3_1c;
  24                 phy_sgmii_slot3_1d = &phy_sgmii_slot3_1d;
  25                 phy_sgmii_slot3_1e = &phy_sgmii_slot3_1e;
  26                 phy_sgmii_slot3_1f = &phy_sgmii_slot3_1f;
  27                 phy_sgmii_slot5_1c = &phy_sgmii_slot5_1c;
  28                 phy_sgmii_slot5_1d = &phy_sgmii_slot5_1d;
  29                 phy_sgmii_slot5_1e = &phy_sgmii_slot5_1e;
  30                 phy_sgmii_slot5_1f = &phy_sgmii_slot5_1f;
  31                 phy_sgmii_slot6_1c = &phy_sgmii_slot6_1c;
  32                 phy_sgmii_slot6_1d = &phy_sgmii_slot6_1d;
  33                 phy_sgmii_slot6_1e = &phy_sgmii_slot6_1e;
  34                 phy_sgmii_slot6_1f = &phy_sgmii_slot6_1f;
  35                 hydra_rg = &hydra_rg;
  36                 hydra_sg_slot2 = &hydra_sg_slot2;
  37                 hydra_sg_slot3 = &hydra_sg_slot3;
  38                 hydra_sg_slot5 = &hydra_sg_slot5;
  39                 hydra_sg_slot6 = &hydra_sg_slot6;
  40                 hydra_xg_slot1 = &hydra_xg_slot1;
  41                 hydra_xg_slot2 = &hydra_xg_slot2;
  42                 spi0 = &espi0;
  43         };
  44
  45         soc: soc@ffe000000 {
  46                 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  47                 reg = <0xf 0xfe000000 0 0x00001000>;
  48
  49                 fman@400000 {
  50                         ethernet@e0000 {
  51                                 phy-connection-type = "sgmii";
  52                         };
  53
  54                         ethernet@e2000 {
  55                                 phy-connection-type = "sgmii";
  56                         };
  57
  58                         ethernet@e4000 {
  59                                 phy-connection-type = "sgmii";
  60                         };
  61
  62                         ethernet@e6000 {
  63                                 phy-connection-type = "sgmii";
  64                         };
  65
  66                         ethernet@e8000 {
  67                                 phy-handle = <&phy_rgmii_0>;
  68                                 phy-connection-type = "rgmii";
  69                         };
  70
  71                         ethernet@f0000 {
  72                                 phy-handle = <&phy_xgmii_slot_2>;
  73                                 phy-connection-type = "xgmii";
  74                         };
  75                 };
  76
  77                 fman@500000 {
  78                         ethernet@e0000 {
  79                                 phy-connection-type = "sgmii";
  80                         };
  81
  82                         ethernet@e2000 {
  83                                 phy-connection-type = "sgmii";
  84                         };
  85
  86                         ethernet@e4000 {
  87                                 phy-connection-type = "sgmii";
  88                         };
  89
  90                         ethernet@e6000 {
  91                                 phy-connection-type = "sgmii";
  92                         };
  93
  94                         ethernet@e8000 {
  95                                 phy-handle = <&phy_rgmii_1>;
  96                                 phy-connection-type = "rgmii";
  97                         };
  98
  99                         ethernet@f0000 {
 100                                 phy-handle = <&phy_xgmii_slot_1>;
 101                                 phy-connection-type = "xgmii";
 102                         };
 103                 };
 104         };
 105
 106         lbc: localbus@ffe124000 {
 107                 reg = <0xf 0xfe124000 0 0x1000>;
 108                 ranges = <0 0 0xf 0xe8000000 0x08000000
 109                           2 0 0xf 0xffa00000 0x00040000
 110                           3 0 0xf 0xffdf0000 0x00008000>;
 111
 112                 board-control@3,0 {
 113                         #address-cells = <1>;
 114                         #size-cells = <1>;
 115                         compatible = "fsl,p5040ds-fpga", "fsl,fpga-ngpixis";
 116                         reg = <3 0 0x40>;
 117                         ranges = <0 3 0 0x40>;
 118
 119                         mdio-mux-emi1 {
 120                                 #address-cells = <1>;
 121                                 #size-cells = <0>;
 122                                 compatible = "mdio-mux-mmioreg", "mdio-mux";
 123                                 mdio-parent-bus = <&mdio0>;
 124                                 reg = <9 1>;
 125                                 mux-mask = <0x78>;
 126
 127                                 hydra_rg:rgmii-mdio@8 {
 128                                         #address-cells = <1>;
 129                                         #size-cells = <0>;
 130                                         reg = <8>;
 131                                         status = "disabled";
 132
 133                                         phy_rgmii_0: ethernet-phy@0 {
 134                                                 reg = <0x0>;
 135                                         };
 136
 137                                         phy_rgmii_1: ethernet-phy@1 {
 138                                                 reg = <0x1>;
 139                                         };
 140                                 };
 141
 142                                 hydra_sg_slot2: sgmii-mdio@28 {
 143                                         #address-cells = <1>;
 144                                         #size-cells = <0>;
 145                                         reg = <0x28>;
 146                                         status = "disabled";
 147
 148                                         phy_sgmii_slot2_1c: ethernet-phy@1c {
 149                                                 reg = <0x1c>;
 150                                         };
 151
 152                                         phy_sgmii_slot2_1d: ethernet-phy@1d {
 153                                                 reg = <0x1d>;
 154                                         };
 155
 156                                         phy_sgmii_slot2_1e: ethernet-phy@1e {
 157                                                 reg = <0x1e>;
 158                                         };
 159
 160                                         phy_sgmii_slot2_1f: ethernet-phy@1f {
 161                                                 reg = <0x1f>;
 162                                         };
 163                                 };
 164
 165                                 hydra_sg_slot3: sgmii-mdio@68 {
 166                                         #address-cells = <1>;
 167                                         #size-cells = <0>;
 168                                         reg = <0x68>;
 169                                         status = "disabled";
 170
 171                                         phy_sgmii_slot3_1c: ethernet-phy@1c {
 172                                                 reg = <0x1c>;
 173                                         };
 174
 175                                         phy_sgmii_slot3_1d: ethernet-phy@1d {
 176                                                 reg = <0x1d>;
 177                                         };
 178
 179                                         phy_sgmii_slot3_1e: ethernet-phy@1e {
 180                                                 reg = <0x1e>;
 181                                         };
 182
 183                                         phy_sgmii_slot3_1f: ethernet-phy@1f {
 184                                                 reg = <0x1f>;
 185                                         };
 186                                 };
 187
 188                                 hydra_sg_slot5: sgmii-mdio@38 {
 189                                         #address-cells = <1>;
 190                                         #size-cells = <0>;
 191                                         reg = <0x38>;
 192                                         status = "disabled";
 193
 194                                         phy_sgmii_slot5_1c: ethernet-phy@1c {
 195                                                 reg = <0x1c>;
 196                                         };
 197
 198                                         phy_sgmii_slot5_1d: ethernet-phy@1d {
 199                                                 reg = <0x1d>;
 200                                         };
 201
 202                                         phy_sgmii_slot5_1e: ethernet-phy@1e {
 203                                                 reg = <0x1e>;
 204                                         };
 205
 206                                         phy_sgmii_slot5_1f: ethernet-phy@1f {
 207                                                 reg = <0x1f>;
 208                                         };
 209                                 };
 210                                 hydra_sg_slot6: sgmii-mdio@48 {
 211                                         #address-cells = <1>;
 212                                         #size-cells = <0>;
 213                                         reg = <0x48>;
 214                                         status = "disabled";
 215
 216                                         phy_sgmii_slot6_1c: ethernet-phy@1c {
 217                                                 reg = <0x1c>;
 218                                         };
 219
 220                                         phy_sgmii_slot6_1d: ethernet-phy@1d {
 221                                                 reg = <0x1d>;
 222                                         };
 223
 224                                         phy_sgmii_slot6_1e: ethernet-phy@1e {
 225                                                 reg = <0x1e>;
 226                                         };
 227
 228                                         phy_sgmii_slot6_1f: ethernet-phy@1f {
 229                                                 reg = <0x1f>;
 230                                         };
 231                                 };
 232                         };
 233
 234                         mdio-mux-emi2 {
 235                                 #address-cells = <1>;
 236                                 #size-cells = <0>;
 237                                 compatible = "mdio-mux-mmioreg", "mdio-mux";
 238                                 mdio-parent-bus = <&xmdio0>;
 239                                 reg = <9 1>;
 240                                 mux-mask = <0x06>;
 241
 242                                 hydra_xg_slot1: hydra-xg-slot1@0 {
 243                                         #address-cells = <1>;
 244                                         #size-cells = <0>;
 245                                         reg = <0>;
 246                                         status = "disabled";
 247
 248                                         phy_xgmii_slot_1: ethernet-phy@0 {
 249                                                 compatible = "ethernet-phy-ieee802.3-c45";
 250                                                 reg = <4>;
 251                                         };
 252                                 };
 253
 254                                 hydra_xg_slot2: hydra-xg-slot2@2 {
 255                                         #address-cells = <1>;
 256                                         #size-cells = <0>;
 257                                         reg = <2>;
 258
 259                                         phy_xgmii_slot_2: ethernet-phy@4 {
 260                                                 compatible = "ethernet-phy-ieee802.3-c45";
 261                                                 reg = <0>;
 262                                         };
 263                                 };
 264                         };
 265                 };
 266         };
 267 };
 268
 269 &espi0 {
 270         status = "okay";
 271         flash@0 {
 272                 compatible = "jedec,spi-nor";
 273                 #address-cells = <1>;
 274                 #size-cells = <1>;
 275                 reg = <0>;
 276                 /* input clock */
 277                 spi-max-frequency = <10000000>;
 278         };
 279 };
 280
 281 /include/ "p5040si-post.dtsi"