arch/powerpc/dts/p5040ds.dts

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * P5040DS Device Tree Source
   4  *
   5  * Copyright 2012 - 2015 Freescale Semiconductor Inc.
   6  * Copyright 2019-2020 NXP
   7  */
   8
   9 /include/ "p5040.dtsi"
  10
  11 / {
  12         model = "fsl,P5040DS";
  13         compatible = "fsl,P5040DS";
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16         interrupt-parent = <&mpic>;
  17
  18         aliases{
  19                 phy_sgmii_slot2_1c = &phy_sgmii_slot2_1c;
  20                 phy_sgmii_slot2_1d = &phy_sgmii_slot2_1d;
  21                 phy_sgmii_slot2_1e = &phy_sgmii_slot2_1e;
  22                 phy_sgmii_slot2_1f = &phy_sgmii_slot2_1f;
  23                 phy_sgmii_slot3_1c = &phy_sgmii_slot3_1c;
  24                 phy_sgmii_slot3_1d = &phy_sgmii_slot3_1d;
  25                 phy_sgmii_slot3_1e = &phy_sgmii_slot3_1e;
  26                 phy_sgmii_slot3_1f = &phy_sgmii_slot3_1f;
  27                 phy_sgmii_slot5_1c = &phy_sgmii_slot5_1c;
  28                 phy_sgmii_slot5_1d = &phy_sgmii_slot5_1d;
  29                 phy_sgmii_slot5_1e = &phy_sgmii_slot5_1e;
  30                 phy_sgmii_slot5_1f = &phy_sgmii_slot5_1f;
  31                 phy_sgmii_slot6_1c = &phy_sgmii_slot6_1c;
  32                 phy_sgmii_slot6_1d = &phy_sgmii_slot6_1d;
  33                 phy_sgmii_slot6_1e = &phy_sgmii_slot6_1e;
  34                 phy_sgmii_slot6_1f = &phy_sgmii_slot6_1f;
  35                 hydra_rg = &hydra_rg;
  36                 hydra_sg_slot2 = &hydra_sg_slot2;
  37                 hydra_sg_slot3 = &hydra_sg_slot3;
  38                 hydra_sg_slot5 = &hydra_sg_slot5;
  39                 hydra_sg_slot6 = &hydra_sg_slot6;
  40                 hydra_xg_slot1 = &hydra_xg_slot1;
  41                 hydra_xg_slot2 = &hydra_xg_slot2;
  42         };
  43
  44         soc: soc@ffe000000 {
  45                 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  46                 reg = <0xf 0xfe000000 0 0x00001000>;
  47
  48                 fman@400000 {
  49                         ethernet@e0000 {
  50                                 phy-connection-type = "sgmii";
  51                         };
  52
  53                         ethernet@e2000 {
  54                                 phy-connection-type = "sgmii";
  55                         };
  56
  57                         ethernet@e4000 {
  58                                 phy-connection-type = "sgmii";
  59                         };
  60
  61                         ethernet@e6000 {
  62                                 phy-connection-type = "sgmii";
  63                         };
  64
  65                         ethernet@e8000 {
  66                                 phy-handle = <&phy_rgmii_0>;
  67                                 phy-connection-type = "rgmii";
  68                         };
  69
  70                         ethernet@f0000 {
  71                                 phy-handle = <&phy_xgmii_slot_2>;
  72                                 phy-connection-type = "xgmii";
  73                         };
  74                 };
  75
  76                 fman@500000 {
  77                         ethernet@e0000 {
  78                                 phy-connection-type = "sgmii";
  79                         };
  80
  81                         ethernet@e2000 {
  82                                 phy-connection-type = "sgmii";
  83                         };
  84
  85                         ethernet@e4000 {
  86                                 phy-connection-type = "sgmii";
  87                         };
  88
  89                         ethernet@e6000 {
  90                                 phy-connection-type = "sgmii";
  91                         };
  92
  93                         ethernet@e8000 {
  94                                 phy-handle = <&phy_rgmii_1>;
  95                                 phy-connection-type = "rgmii";
  96                         };
  97
  98                         ethernet@f0000 {
  99                                 phy-handle = <&phy_xgmii_slot_1>;
 100                                 phy-connection-type = "xgmii";
 101                         };
 102                 };
 103         };
 104
 105         lbc: localbus@ffe124000 {
 106                 reg = <0xf 0xfe124000 0 0x1000>;
 107                 ranges = <0 0 0xf 0xe8000000 0x08000000
 108                           2 0 0xf 0xffa00000 0x00040000
 109                           3 0 0xf 0xffdf0000 0x00008000>;
 110
 111                 board-control@3,0 {
 112                         #address-cells = <1>;
 113                         #size-cells = <1>;
 114                         compatible = "fsl,p5040ds-fpga", "fsl,fpga-ngpixis";
 115                         reg = <3 0 0x40>;
 116                         ranges = <0 3 0 0x40>;
 117
 118                         mdio-mux-emi1 {
 119                                 #address-cells = <1>;
 120                                 #size-cells = <0>;
 121                                 compatible = "mdio-mux-mmioreg", "mdio-mux";
 122                                 mdio-parent-bus = <&mdio0>;
 123                                 reg = <9 1>;
 124                                 mux-mask = <0x78>;
 125
 126                                 hydra_rg:rgmii-mdio@8 {
 127                                         #address-cells = <1>;
 128                                         #size-cells = <0>;
 129                                         reg = <8>;
 130                                         status = "disabled";
 131
 132                                         phy_rgmii_0: ethernet-phy@0 {
 133                                                 reg = <0x0>;
 134                                         };
 135
 136                                         phy_rgmii_1: ethernet-phy@1 {
 137                                                 reg = <0x1>;
 138                                         };
 139                                 };
 140
 141                                 hydra_sg_slot2: sgmii-mdio@28 {
 142                                         #address-cells = <1>;
 143                                         #size-cells = <0>;
 144                                         reg = <0x28>;
 145                                         status = "disabled";
 146
 147                                         phy_sgmii_slot2_1c: ethernet-phy@1c {
 148                                                 reg = <0x1c>;
 149                                         };
 150
 151                                         phy_sgmii_slot2_1d: ethernet-phy@1d {
 152                                                 reg = <0x1d>;
 153                                         };
 154
 155                                         phy_sgmii_slot2_1e: ethernet-phy@1e {
 156                                                 reg = <0x1e>;
 157                                         };
 158
 159                                         phy_sgmii_slot2_1f: ethernet-phy@1f {
 160                                                 reg = <0x1f>;
 161                                         };
 162                                 };
 163
 164                                 hydra_sg_slot3: sgmii-mdio@68 {
 165                                         #address-cells = <1>;
 166                                         #size-cells = <0>;
 167                                         reg = <0x68>;
 168                                         status = "disabled";
 169
 170                                         phy_sgmii_slot3_1c: ethernet-phy@1c {
 171                                                 reg = <0x1c>;
 172                                         };
 173
 174                                         phy_sgmii_slot3_1d: ethernet-phy@1d {
 175                                                 reg = <0x1d>;
 176                                         };
 177
 178                                         phy_sgmii_slot3_1e: ethernet-phy@1e {
 179                                                 reg = <0x1e>;
 180                                         };
 181
 182                                         phy_sgmii_slot3_1f: ethernet-phy@1f {
 183                                                 reg = <0x1f>;
 184                                         };
 185                                 };
 186
 187                                 hydra_sg_slot5: sgmii-mdio@38 {
 188                                         #address-cells = <1>;
 189                                         #size-cells = <0>;
 190                                         reg = <0x38>;
 191                                         status = "disabled";
 192
 193                                         phy_sgmii_slot5_1c: ethernet-phy@1c {
 194                                                 reg = <0x1c>;
 195                                         };
 196
 197                                         phy_sgmii_slot5_1d: ethernet-phy@1d {
 198                                                 reg = <0x1d>;
 199                                         };
 200
 201                                         phy_sgmii_slot5_1e: ethernet-phy@1e {
 202                                                 reg = <0x1e>;
 203                                         };
 204
 205                                         phy_sgmii_slot5_1f: ethernet-phy@1f {
 206                                                 reg = <0x1f>;
 207                                         };
 208                                 };
 209                                 hydra_sg_slot6: sgmii-mdio@48 {
 210                                         #address-cells = <1>;
 211                                         #size-cells = <0>;
 212                                         reg = <0x48>;
 213                                         status = "disabled";
 214
 215                                         phy_sgmii_slot6_1c: ethernet-phy@1c {
 216                                                 reg = <0x1c>;
 217                                         };
 218
 219                                         phy_sgmii_slot6_1d: ethernet-phy@1d {
 220                                                 reg = <0x1d>;
 221                                         };
 222
 223                                         phy_sgmii_slot6_1e: ethernet-phy@1e {
 224                                                 reg = <0x1e>;
 225                                         };
 226
 227                                         phy_sgmii_slot6_1f: ethernet-phy@1f {
 228                                                 reg = <0x1f>;
 229                                         };
 230                                 };
 231                         };
 232
 233                         mdio-mux-emi2 {
 234                                 #address-cells = <1>;
 235                                 #size-cells = <0>;
 236                                 compatible = "mdio-mux-mmioreg", "mdio-mux";
 237                                 mdio-parent-bus = <&xmdio0>;
 238                                 reg = <9 1>;
 239                                 mux-mask = <0x06>;
 240
 241                                 hydra_xg_slot1: hydra-xg-slot1@0 {
 242                                         #address-cells = <1>;
 243                                         #size-cells = <0>;
 244                                         reg = <0>;
 245                                         status = "disabled";
 246
 247                                         phy_xgmii_slot_1: ethernet-phy@0 {
 248                                                 compatible = "ethernet-phy-ieee802.3-c45";
 249                                                 reg = <4>;
 250                                         };
 251                                 };
 252
 253                                 hydra_xg_slot2: hydra-xg-slot2@2 {
 254                                         #address-cells = <1>;
 255                                         #size-cells = <0>;
 256                                         reg = <2>;
 257
 258                                         phy_xgmii_slot_2: ethernet-phy@4 {
 259                                                 compatible = "ethernet-phy-ieee802.3-c45";
 260                                                 reg = <0>;
 261                                         };
 262                                 };
 263                         };
 264                 };
 265         };
 266 };
 267
 268 /include/ "p5040si-post.dtsi"