arch/powerpc/dts/p4080ds.dts

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * P4080DS Device Tree Source
   4  *
   5  * Copyright 2011 - 2015 Freescale Semiconductor Inc.
   6  * Copyright 2019-2020 NXP
   7  */
   8
   9 /include/ "p4080.dtsi"
  10
  11 / {
  12         model = "fsl,P4080DS";
  13         compatible = "fsl,P4080DS";
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16         interrupt-parent = <&mpic>;
  17
  18         aliases {
  19                 phy_rgmii = &phyrgmii;
  20                 phy5_slot3 = &phy5slot3;
  21                 phy6_slot3 = &phy6slot3;
  22                 phy7_slot3 = &phy7slot3;
  23                 phy8_slot3 = &phy8slot3;
  24                 emi1_slot3 = &p4080mdio2;
  25                 emi1_slot4 = &p4080mdio1;
  26                 emi1_slot5 = &p4080mdio3;
  27                 emi1_rgmii = &p4080mdio0;
  28                 emi2_slot4 = &p4080xmdio1;
  29                 emi2_slot5 = &p4080xmdio3;
  30         };
  31
  32         soc: soc@ffe000000 {
  33                 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  34                 reg = <0xf 0xfe000000 0 0x00001000>;
  35
  36                 fman@400000 {
  37                         ethernet@e0000 {
  38                                 phy-handle = <&phy0>;
  39                                 phy-connection-type = "sgmii";
  40                         };
  41
  42                         ethernet@e2000 {
  43                                 phy-handle = <&phy1>;
  44                                 phy-connection-type = "sgmii";
  45                         };
  46
  47                         ethernet@e4000 {
  48                                 phy-handle = <&phy2>;
  49                                 phy-connection-type = "sgmii";
  50                         };
  51
  52                         ethernet@e6000 {
  53                                 phy-handle = <&phy3>;
  54                                 phy-connection-type = "sgmii";
  55                         };
  56
  57                         ethernet@f0000 {
  58                                 phy-handle = <&phy10>;
  59                                 phy-connection-type = "xgmii";
  60                         };
  61                 };
  62
  63                 fman@500000 {
  64                         ethernet@e0000 {
  65                                 phy-handle = <&phy5>;
  66                                 phy-connection-type = "sgmii";
  67                         };
  68
  69                         ethernet@e2000 {
  70                                 phy-handle = <&phy6>;
  71                                 phy-connection-type = "sgmii";
  72                         };
  73
  74                         ethernet@e4000 {
  75                                 phy-handle = <&phy7>;
  76                                 phy-connection-type = "sgmii";
  77                         };
  78
  79                         ethernet@e6000 {
  80                                 phy-handle = <&phy8>;
  81                                 phy-connection-type = "sgmii";
  82                         };
  83
  84                         ethernet@f0000 {
  85                                 phy-handle = <&phy11>;
  86                                 phy-connection-type = "xgmii";
  87                         };
  88                 };
  89         };
  90
  91         mdio-mux-emi1 {
  92                 #address-cells = <1>;
  93                 #size-cells = <0>;
  94                 compatible = "mdio-mux-gpio", "mdio-mux";
  95                 mdio-parent-bus = <&mdio0>;
  96                 gpios = <&gpio0 1 0>, <&gpio0 0 0>;
  97
  98                 p4080mdio0: mdio@0 {
  99                         #address-cells = <1>;
 100                         #size-cells = <0>;
 101                         reg = <0>;
 102
 103                         phyrgmii: ethernet-phy@0 {
 104                                 reg = <0x0>;
 105                         };
 106                 };
 107
 108                 p4080mdio1: mdio@1 {
 109                         #address-cells = <1>;
 110                         #size-cells = <0>;
 111                         reg = <1>;
 112
 113                         phy5: ethernet-phy@1c {
 114                                 reg = <0x1c>;
 115                         };
 116
 117                         phy6: ethernet-phy@1d {
 118                                 reg = <0x1d>;
 119                         };
 120
 121                         phy7: ethernet-phy@1e {
 122                                 reg = <0x1e>;
 123                         };
 124
 125                         phy8: ethernet-phy@1f {
 126                                 reg = <0x1f>;
 127                         };
 128                 };
 129
 130                 p4080mdio2: mdio@2 {
 131                         #address-cells = <1>;
 132                         #size-cells = <0>;
 133                         reg = <2>;
 134                         status = "disabled";
 135
 136                         phy5slot3: ethernet-phy@1c {
 137                                 reg = <0x1c>;
 138                         };
 139
 140                         phy6slot3: ethernet-phy@1d {
 141                                 reg = <0x1d>;
 142                         };
 143
 144                         phy7slot3: ethernet-phy@1e {
 145                                 reg = <0x1e>;
 146                         };
 147
 148                         phy8slot3: ethernet-phy@1f {
 149                                 reg = <0x1f>;
 150                         };
 151                 };
 152
 153                 p4080mdio3: mdio@3 {
 154                         #address-cells = <1>;
 155                         #size-cells = <0>;
 156                         reg = <3>;
 157
 158                         phy0: ethernet-phy@1c {
 159                                 reg = <0x1c>;
 160                         };
 161
 162                         phy1: ethernet-phy@1d {
 163                                 reg = <0x1d>;
 164                         };
 165
 166                         phy2: ethernet-phy@1e {
 167                                 reg = <0x1e>;
 168                         };
 169
 170                         phy3: ethernet-phy@1f {
 171                                 reg = <0x1f>;
 172                         };
 173                 };
 174         };
 175
 176         mdio-mux-emi2 {
 177                 #address-cells = <1>;
 178                 #size-cells = <0>;
 179                 compatible = "mdio-mux-gpio", "mdio-mux";
 180                 mdio-parent-bus = <&xmdio0>;
 181                 gpios = <&gpio0 3 0>, <&gpio0 2 0>;
 182
 183                 p4080xmdio1: mdio@1 {
 184                         #address-cells = <1>;
 185                         #size-cells = <0>;
 186                         reg = <1>;
 187
 188                         phy11: ethernet-phy@0 {
 189                                 compatible = "ethernet-phy-ieee802.3-c45";
 190                                 reg = <0x0>;
 191                         };
 192                 };
 193
 194                 p4080xmdio3: mdio@3 {
 195                         #address-cells = <1>;
 196                         #size-cells = <0>;
 197                         reg = <3>;
 198
 199                         phy10: ethernet-phy@4 {
 200                                 compatible = "ethernet-phy-ieee802.3-c45";
 201                                 reg = <0x4>;
 202                         };
 203                 };
 204         };
 205 };
 206
 207 /include/ "p4080si-post.dtsi"