arch/powerpc/dts/p2041rdb.dts

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * P2041RDB Device Tree Source
   4  *
   5  * Copyright 2011 - 2015 Freescale Semiconductor Inc.
   6  * Copyright 2019-2020 NXP
   7  */
   8
   9 /include/ "p2041.dtsi"
  10
  11 / {
  12         model = "fsl,P2041RDB";
  13         compatible = "fsl,P2041RDB";
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16         interrupt-parent = <&mpic>;
  17
  18         aliases {
  19                 phy_rgmii_0 = &phy_rgmii_0;
  20                 phy_rgmii_1 = &phy_rgmii_1;
  21                 phy_sgmii_2 = &phy_sgmii_2;
  22                 phy_sgmii_3 = &phy_sgmii_3;
  23                 phy_sgmii_4 = &phy_sgmii_4;
  24                 phy_sgmii_1c = &phy_sgmii_1c;
  25                 phy_sgmii_1d = &phy_sgmii_1d;
  26                 phy_sgmii_1e = &phy_sgmii_1e;
  27                 phy_sgmii_1f = &phy_sgmii_1f;
  28                 phy_xgmii_2 = &phy_xgmii_2;
  29                 spi0 = &espi0;
  30         };
  31
  32         soc: soc@ffe000000 {
  33                 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  34                 reg = <0xf 0xfe000000 0 0x00001000>;
  35
  36                 fman@400000 {
  37                         ethernet@e0000 {
  38                                 phy-handle = <&phy_sgmii_2>;
  39                                 phy-connection-type = "sgmii";
  40                         };
  41
  42                         mdio@e1120 {
  43                                 phy_rgmii_0: ethernet-phy@0 {
  44                                         reg = <0x0>;
  45                                 };
  46
  47                                 phy_rgmii_1: ethernet-phy@1 {
  48                                         reg = <0x1>;
  49                                 };
  50
  51                                 phy_sgmii_2: ethernet-phy@2 {
  52                                         reg = <0x2>;
  53                                 };
  54
  55                                 phy_sgmii_3: ethernet-phy@3 {
  56                                         reg = <0x3>;
  57                                 };
  58
  59                                 phy_sgmii_4: ethernet-phy@4 {
  60                                         reg = <0x4>;
  61                                 };
  62
  63                                 phy_sgmii_1c: ethernet-phy@1c {
  64                                         reg = <0x1c>;
  65                                 };
  66
  67                                 phy_sgmii_1d: ethernet-phy@1d {
  68                                         reg = <0x1d>;
  69                                 };
  70
  71                                 phy_sgmii_1e: ethernet-phy@1e {
  72                                         reg = <0x1e>;
  73                                 };
  74
  75                                 phy_sgmii_1f: ethernet-phy@1f {
  76                                         reg = <0x1f>;
  77                                 };
  78                         };
  79
  80                         ethernet@e2000 {
  81                                 phy-handle = <&phy_sgmii_3>;
  82                                 phy-connection-type = "sgmii";
  83                         };
  84
  85                         ethernet@e4000 {
  86                                 phy-handle = <&phy_sgmii_4>;
  87                                 phy-connection-type = "sgmii";
  88                         };
  89
  90                         ethernet@e6000 {
  91                                 phy-handle = <&phy_rgmii_1>;
  92                                 phy-connection-type = "rgmii";
  93                         };
  94
  95                         ethernet@e8000 {
  96                                 phy-handle = <&phy_rgmii_0>;
  97                                 phy-connection-type = "rgmii";
  98                         };
  99
 100                         ethernet@f0000 {
 101                                 phy-handle = <&phy_xgmii_2>;
 102                                 phy-connection-type = "xgmii";
 103                         };
 104
 105                         mdio@f1000 {
 106                                 phy_xgmii_2: ethernet-phy@0 {
 107                                         compatible = "ethernet-phy-ieee802.3-c45";
 108                                         reg = <0x0>;
 109                                 };
 110                         };
 111                 };
 112         };
 113 };
 114
 115 &espi0 {
 116         status = "okay";
 117         flash@0 {
 118                 compatible = "jedec,spi-nor";
 119                 #address-cells = <1>;
 120                 #size-cells = <1>;
 121                 reg = <0>;
 122                 /* input clock */
 123                 spi-max-frequency = <10000000>;
 124         };
 125 };
 126
 127 /include/ "p2041si-post.dtsi"