arch/powerpc/dts/p2020rdb-pc_36b.dts

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * P2020RDB-PC (36-bit address map) Device Tree Source
   4  *
   5  * Copyright 2013 - 2015 Freescale Semiconductor Inc.
   6  * Copyright 2019 NXP
   7  */
   8
   9 /include/ "p2020.dtsi"
  10
  11 / {
  12         model = "fsl,P2020RDB-PC";
  13         compatible = "fsl,P2020RDB-PC";
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16         interrupt-parent = <&mpic>;
  17
  18         soc: soc@fffe00000 {
  19                 ranges = <0x0 0xf 0xffe00000 0x100000>;
  20         };
  21
  22         pci2: pcie@fffe08000 {
  23                 reg = <0xf 0xffe08000 0x0 0x1000>;      /* registers */
  24                 status = "disabled";
  25         };
  26
  27         pci1: pcie@fffe09000 {
  28                 reg = <0xf 0xffe09000 0x0 0x1000>;      /* registers */
  29                 ranges = <0x01000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000   /* downstream I/O */
  30                           0x02000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
  31         };
  32
  33         pci0: pcie@fffe0a000 {
  34                 reg = <0xf 0xffe0a000 0x0 0x1000>;      /* registers */
  35                 ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000   /* downstream I/O */
  36                           0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
  37         };
  38
  39         aliases {
  40                 spi0 = &espi0;
  41         };
  42 };
  43
  44 /include/ "p2020rdb-pc.dtsi"
  45 /include/ "p2020-post.dtsi"
  46
  47 &espi0 {
  48         status = "okay";
  49         flash@0 {
  50                 compatible = "jedec,spi-nor";
  51                 #address-cells = <1>;
  52                 #size-cells = <1>;
  53                 reg = <0>;
  54                 spi-max-frequency = <10000000>; /* input clock */
  55         };
  56 };