1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * P2020RDB-PC Device Tree Source
5 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
12 model = "fsl,P2020RDB-PC";
13 compatible = "fsl,P2020RDB-PC";
16 interrupt-parent = <&mpic>;
19 ranges = <0x0 0x0 0xffe00000 0x100000>;
23 reg = <0x0 0xffe08000 0x0 0x1000>; /* registers */
28 reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */
29 ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */
30 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
34 reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */
35 ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */
36 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
44 /include/ "p2020rdb-pc.dtsi"
45 /include/ "p2020-post.dtsi"
50 compatible = "jedec,spi-nor";
54 spi-max-frequency = <10000000>; /* input clock */