arch/powerpc/dts/p2020-post.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * P2020 Silicon/SoC Device Tree Source (post include)
   4  *
   5  * Copyright 2013 Freescale Semiconductor Inc.
   6  * Copyright 2019 NXP
   7  */
   8
   9 &soc {
  10         #address-cells = <1>;
  11         #size-cells = <1>;
  12         device_type = "soc";
  13         compatible = "fsl,p2020-immr", "simple-bus";
  14         bus-frequency = <0x0>;
  15
  16         usb@22000 {
  17                 compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
  18                 reg = <0x22000 0x1000>;
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21                 interrupts = <28 0x2 0 0>;
  22                 phy_type = "ulpi";
  23         };
  24
  25         mpic: pic@40000 {
  26                 interrupt-controller;
  27                 #address-cells = <0>;
  28                 #interrupt-cells = <4>;
  29                 reg = <0x40000 0x40000>;
  30                 compatible = "fsl,mpic";
  31                 device_type = "open-pic";
  32                 big-endian;
  33                 single-cpu-affinity;
  34                 last-interrupt-source = <255>;
  35         };
  36
  37         esdhc: sdhc@2e000 {
  38                 compatible = "fsl,p2020-esdhc", "fsl,esdhc";
  39                 reg = <0x2e000 0x1000>;
  40                 interrupts = <72 0x2 0 0>;
  41                 /* Filled in by U-Boot */
  42                 clock-frequency = <0>;
  43         };
  44
  45         espi0: spi@7000 {
  46                 compatible = "fsl,mpc8536-espi";
  47                 #address-cells = <1>;
  48                 #size-cells = <0>;
  49                 reg = <0x7000 0x1000>;
  50                 interrupts = < 0x3b 0x02 0x00 0x00 >;
  51                 fsl,espi-num-chipselects = <4>;
  52         };
  53
  54 /include/ "pq3-i2c-0.dtsi"
  55 /include/ "pq3-i2c-1.dtsi"
  56 /include/ "pq3-duart-0.dtsi"
  57 /include/ "pq3-gpio-0.dtsi"
  58
  59         L2: l2-cache-controller@20000 {
  60                 compatible = "fsl,p2020-l2-cache-controller";
  61                 reg = <0x20000 0x1000>;
  62                 cache-line-size = <32>; /* 32 bytes */
  63                 cache-size = <0x80000>; /* L2,512K */
  64                 interrupts = <16 2 0 0>;
  65         };
  66
  67 /include/ "pq3-etsec1-0.dtsi"
  68 /include/ "pq3-etsec1-timer-0.dtsi"
  69
  70         ptp_clock@24e00 {
  71                 interrupts = <68 2 0 0 69 2 0 0 70 2 0 0>;
  72         };
  73
  74 /include/ "pq3-etsec1-1.dtsi"
  75 /include/ "pq3-etsec1-2.dtsi"
  76
  77 /include/ "pq3-sec3.1-0.dtsi"
  78 /include/ "pq3-mpic.dtsi"
  79 /include/ "pq3-mpic-timer-B.dtsi"
  80 };
  81
  82 /* PCIe controller base address 0x8000 */
  83 &pci2 {
  84         compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq", "fsl,mpc8548-pcie";
  85         law_trgt_if = <0>;
  86         #address-cells = <3>;
  87         #size-cells = <2>;
  88         device_type = "pci";
  89         bus-range = <0x0 0xff>;
  90         clock-frequency = <33333333>;
  91         interrupts = <24 2 0 0>;
  92
  93         pcie@0 {
  94                 reg = <0 0 0 0 0>;
  95                 #interrupt-cells = <1>;
  96                 #size-cells = <2>;
  97                 #address-cells = <3>;
  98                 device_type = "pci";
  99                 interrupts = <24 2 0 0>;
 100                 interrupt-map-mask = <0xf800 0 0 7>;
 101
 102                 interrupt-map = <
 103                         /* IDSEL 0x0 */
 104                         0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
 105                         0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
 106                         0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
 107                         0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
 108                         >;
 109         };
 110 };
 111
 112 /* PCIe controller base address 0x9000 */
 113 &pci1 {
 114         compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq", "fsl,mpc8548-pcie";
 115         law_trgt_if = <1>;
 116         #address-cells = <3>;
 117         #size-cells = <2>;
 118         device_type = "pci";
 119         bus-range = <0x0 0xff>;
 120         clock-frequency = <33333333>;
 121         interrupts = <25 2 0 0>;
 122
 123         pcie@0 {
 124                 reg = <0 0 0 0 0>;
 125                 #interrupt-cells = <1>;
 126                 #size-cells = <2>;
 127                 #address-cells = <3>;
 128                 device_type = "pci";
 129                 interrupts = <25 2 0 0>;
 130                 interrupt-map-mask = <0xf800 0 0 7>;
 131
 132                 interrupt-map = <
 133                         /* IDSEL 0x0 */
 134                         0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
 135                         0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
 136                         0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
 137                         0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
 138                         >;
 139         };
 140 };
 141
 142 /* PCIe controller base address 0xa000 */
 143 &pci0 {
 144         compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq", "fsl,mpc8548-pcie";
 145         law_trgt_if = <2>;
 146         #address-cells = <3>;
 147         #size-cells = <2>;
 148         device_type = "pci";
 149         bus-range = <0x0 0xff>;
 150         clock-frequency = <33333333>;
 151         interrupts = <26 2 0 0>;
 152
 153         pcie@0 {
 154                 reg = <0 0 0 0 0>;
 155                 #interrupt-cells = <1>;
 156                 #size-cells = <2>;
 157                 #address-cells = <3>;
 158                 device_type = "pci";
 159                 interrupts = <26 2 0 0>;
 160                 interrupt-map-mask = <0xf800 0 0 7>;
 161                 interrupt-map = <
 162                         /* IDSEL 0x0 */
 163                         0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
 164                         0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
 165                         0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
 166                         0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
 167                         >;
 168         };
 169 };
 170
 171 &lbc {
 172         #address-cells = <2>;
 173         #size-cells = <1>;
 174         compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
 175         interrupts = <19 2 0 0>;
 176 };