1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * P2020 Silicon/SoC Device Tree Source (post include)
5 * Copyright 2013 Freescale Semiconductor Inc.
13 compatible = "fsl,p2020-immr", "simple-bus";
14 bus-frequency = <0x0>;
17 compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
18 reg = <0x22000 0x1000>;
21 interrupts = <28 0x2 0 0>;
28 #interrupt-cells = <4>;
29 reg = <0x40000 0x40000>;
30 compatible = "fsl,mpic";
31 device_type = "open-pic";
34 last-interrupt-source = <255>;
38 compatible = "fsl,p2020-esdhc", "fsl,esdhc";
39 reg = <0x2e000 0x1000>;
40 interrupts = <72 0x2 0 0>;
41 /* Filled in by U-Boot */
42 clock-frequency = <0>;
46 compatible = "fsl,mpc8536-espi";
49 reg = <0x7000 0x1000>;
50 interrupts = < 0x3b 0x02 0x00 0x00 >;
51 fsl,espi-num-chipselects = <4>;
54 /include/ "pq3-i2c-0.dtsi"
55 /include/ "pq3-i2c-1.dtsi"
56 /include/ "pq3-duart-0.dtsi"
57 /include/ "pq3-gpio-0.dtsi"
59 L2: l2-cache-controller@20000 {
60 compatible = "fsl,p2020-l2-cache-controller";
61 reg = <0x20000 0x1000>;
62 cache-line-size = <32>; /* 32 bytes */
63 cache-size = <0x80000>; /* L2,512K */
64 interrupts = <16 2 0 0>;
67 /include/ "pq3-etsec1-0.dtsi"
68 /include/ "pq3-etsec1-timer-0.dtsi"
71 interrupts = <68 2 0 0 69 2 0 0 70 2 0 0>;
74 /include/ "pq3-etsec1-1.dtsi"
75 /include/ "pq3-etsec1-2.dtsi"
77 /include/ "pq3-mpic.dtsi"
78 /include/ "pq3-mpic-timer-B.dtsi"
81 /* PCIe controller base address 0x8000 */
83 compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq", "fsl,mpc8548-pcie";
88 bus-range = <0x0 0xff>;
89 clock-frequency = <33333333>;
90 interrupts = <24 2 0 0>;
94 #interrupt-cells = <1>;
98 interrupts = <24 2 0 0>;
99 interrupt-map-mask = <0xf800 0 0 7>;
103 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
104 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
105 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
106 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
111 /* PCIe controller base address 0x9000 */
113 compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq", "fsl,mpc8548-pcie";
115 #address-cells = <3>;
118 bus-range = <0x0 0xff>;
119 clock-frequency = <33333333>;
120 interrupts = <25 2 0 0>;
124 #interrupt-cells = <1>;
126 #address-cells = <3>;
128 interrupts = <25 2 0 0>;
129 interrupt-map-mask = <0xf800 0 0 7>;
133 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
134 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
135 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
136 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
141 /* PCIe controller base address 0xa000 */
143 compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq", "fsl,mpc8548-pcie";
145 #address-cells = <3>;
148 bus-range = <0x0 0xff>;
149 clock-frequency = <33333333>;
150 interrupts = <26 2 0 0>;
154 #interrupt-cells = <1>;
156 #address-cells = <3>;
158 interrupts = <26 2 0 0>;
159 interrupt-map-mask = <0xf800 0 0 7>;
162 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
163 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
164 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
165 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
171 #address-cells = <2>;
173 compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
174 interrupts = <19 2 0 0>;