1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * P1020 Silicon/SoC Device Tree Source (post include)
5 * Copyright 2013 Freescale Semiconductor Inc.
13 compatible = "fsl,p1020-immr", "simple-bus";
14 bus-frequency = <0x0>;
17 compatible = "fsl-usb2-dr";
18 reg = <0x22000 0x1000>;
23 compatible = "fsl-usb2-dr";
24 reg = <0x23000 0x1000>;
31 #interrupt-cells = <4>;
32 reg = <0x40000 0x40000>;
33 compatible = "fsl,mpic";
34 device_type = "open-pic";
37 last-interrupt-source = <255>;
41 compatible = "fsl,esdhc";
42 reg = <0x2e000 0x1000>;
43 /* Filled in by U-Boot */
44 clock-frequency = <0>;
48 compatible = "fsl,mpc8536-espi";
51 reg = <0x7000 0x1000>;
52 fsl,espi-num-chipselects = <4>;
56 /include/ "pq3-i2c-0.dtsi"
57 /include/ "pq3-i2c-1.dtsi"
59 /include/ "pq3-etsec2-0.dtsi"
60 enet0: enet0_grp2: ethernet@b0000 {
63 /include/ "pq3-etsec2-1.dtsi"
64 enet1: enet1_grp2: ethernet@b1000 {
67 /include/ "pq3-etsec2-2.dtsi"
68 enet2: enet2_grp2: ethernet@b2000 {
72 /include/ "pq3-etsec2-grp2-0.dtsi"
73 /include/ "pq3-etsec2-grp2-1.dtsi"
74 /include/ "pq3-etsec2-grp2-2.dtsi"
76 /* PCIe controller base address 0x9000 */
78 compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
83 bus-range = <0x0 0xff>;
86 /* PCIe controller base address 0xa000 */
88 compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
93 bus-range = <0x0 0xff>;