arch/powerpc/dts/p1010si-post.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * P1010 Silicon/SoC Device Tree Source (post include)
   4  *
   5  * Copyright 2020 NXP
   6  */
   7
   8 &soc {
   9         #address-cells = <1>;
  10         #size-cells = <1>;
  11         device_type = "soc";
  12         compatible = "fsl,p1010-immr", "simple-bus";
  13         bus-frequency = <0>;
  14
  15         mpic: pic@40000 {
  16                 interrupt-controller;
  17                 #address-cells = <0>;
  18                 #interrupt-cells = <4>;
  19                 reg = <0x40000 0x40000>;
  20                 compatible = "fsl,mpic";
  21                 device_type = "open-pic";
  22                 big-endian;
  23                 single-cpu-affinity;
  24                 last-interrupt-source = <255>;
  25         };
  26 };
  27
  28 /* controller at 0x9000 */
  29 &pci1 {
  30         compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
  31         law_trgt_if = <1>;
  32         #address-cells = <3>;
  33         #size-cells = <2>;
  34         device_type = "pci";
  35         bus-range = <0x0 0xff>;
  36 };
  37
  38 /* controller at 0xa000 */
  39 &pci0 {
  40         compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
  41         law_trgt_if = <2>;
  42         #address-cells = <3>;
  43         #size-cells = <2>;
  44         device_type = "pci";
  45         bus-range = <0x0 0xff>;
  46 };