arch/powerpc/dts/kmtepr2.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * ABB PGGA TEPR2 Device Tree Source
   4  *
   5  * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
   6  *
   7  */
   8
   9 /dts-v1/;
  10
  11 #include "km8321.dtsi"
  12
  13 / {
  14         model = "KMTEPR2";
  15         compatible = "ABB,kmpbec8321";
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         aliases {
  20                 ethernet0 = &enet_piggy2;
  21                 serial0 = &serial0;
  22         };
  23 };
  24
  25 &i2c0 {
  26         mux@70 {
  27                 compatible = "nxp,pca9547";
  28                 reg = <0x70>;
  29                 #address-cells = <1>;
  30                 #size-cells = <0>;
  31
  32                 i2c@1 {
  33                         reg = <1>;
  34                         #address-cells = <1>;
  35                         #size-cells = <0>;
  36
  37                         /* Inventory EEPROM of the unit itself */
  38                         ivm@50 {
  39                                 label = "MAIN_CTRL";
  40                                 compatible = "dummy";
  41                                 reg = <0x50>;
  42                         };
  43                 };
  44
  45                 i2c@2 {
  46                         reg = <2>;
  47                         #address-cells = <1>;
  48                         #size-cells = <0>;
  49
  50                         /* Temperature sensors */
  51                         temp@49 {
  52                                 label = "board";
  53                                 compatible = "national,lm75";
  54                                 reg = <0x49>;
  55                         };
  56
  57                         temp@4a {
  58                                 label = "power";
  59                                 compatible = "national,lm75";
  60                                 reg = <0x4a>;
  61                         };
  62                 };
  63         };
  64 };
  65
  66 &par_io {
  67         /* UCC5 as HDLC controller for ICN */
  68         pio_ucc5: ucc_pin@04 {
  69                 pio-map = <
  70                         /* port  pin  dir  open_drain  assignment  has_irq */
  71                         2   0  1  0  2  0   /* TxD0 */
  72                         2   8  2  0  2  0   /* RxD0 */
  73                         2  29  2  0  2  0   /* CTS */
  74                         3  30  2  0  1  0   /* ICN CLK */
  75                         >;
  76         };
  77
  78         /* UCC4 Piggy Ethernet */
  79         pio_ucc4: ucc_pin@03 {
  80                 pio-map = <
  81                         /* port pin dir open_drain assignment has_irq */
  82                         3   4  3  0  2  0       /* MDIO */
  83                         3   5  1  0  2  0       /* MDC  */
  84
  85                         1 18  1  0  1  0        /* TxD0 */
  86                         1 19  1  0  1  0        /* TxD1 */
  87                         1 22  2  0  1  0        /* RxD0 */
  88                         1 23  2  0  1  0        /* RxD1 */
  89                         1 26  2  0  1  0        /* RX_ER */
  90                         1 28  2  0  1  0        /* RX_DV */
  91                         1 30  1  0  1  0        /* TX_EN */
  92                         1 31  2  0  1  0        /* CRS */
  93                         3 10  2  0  3  0        /* UCC4_RMII_CLK (CLK17) */
  94                 >;
  95         };
  96
  97         pio_spi: spi_pin@01 {
  98                 pio-map = <
  99                         /*
 100                          *port pin dir open_drain assignment has_irq
 101                          * SPI_MOSI (PD0, bi, f3)
 102                          */
 103                         3  0  3  0  1  0
 104                         /* SPI_MISO (PD1, bi, f3) */
 105                         3  1  3  0  1  0
 106                         /* SPI_CLK  (PD2, bi, f3) */
 107                         3  2  3  0  1  0
 108                 >;
 109         };
 110 };
 111
 112 &localbus {
 113         ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */
 114                 1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */
 115                 2 0 0xa0000000 0x10000000 /* LB 2 NVSRAM */
 116                 3 0 0xb0000000 0x10000000>; /* LB 3 TEP2 */
 117
 118         flash@0,0 {
 119                 compatible = "cfi-flash";
 120                 reg = <0 0x00000000 0x04000000>;
 121                 bank-width = <2>;
 122                 #address-cells = <1>;
 123                 #size-cells = <1>;
 124                 use-advanced-sector-protection;
 125                 partition@0 { /* 768KB */
 126                         label = "u-boot";
 127                         reg = <0 0xC0000>;
 128                 };
 129                 partition@c0000 { /* 128KB */
 130                         label = "env";
 131                         reg = <0xc0000 0x20000>;
 132                 };
 133                 partition@e0000 { /* 128KB */
 134                         label = "envred";
 135                         reg = <0xe0000 0x20000>;
 136                 };
 137                 partition@100000 { /* 64512KB */
 138                         label = "ubi0";
 139                         reg = <0x100000 0x3F00000>;
 140                 };
 141         };
 142 };