arch/powerpc/dts/kmtegr1.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * ABB PGGA TEGR1 Device Tree Source
   4  *
   5  * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
   6  *
   7  */
   8
   9 /dts-v1/;
  10
  11 / {
  12         model = "KMTEGR1";
  13         compatible = "ABB,kmpbec8309";
  14         #address-cells = <1>;
  15         #size-cells = <1>;
  16
  17         aliases {
  18                 ethernet0 = &enet_zynq;
  19                 ethernet1 = &enet_piggy2;
  20                 serial0 = &serial0;
  21         };
  22
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 PowerPC,8309@0 {
  28                         device_type = "cpu";
  29                         reg = <0x0>;
  30                         d-cache-line-size = <32>;       // 32 bytes
  31                         i-cache-line-size = <32>;       // 32 bytes
  32                         d-cache-size = <16384>;         // L1, 16K
  33                         i-cache-size = <16384>;         // L1, 16K
  34                         timebase-frequency = <66000000>;
  35                         bus-frequency = <264000000>;
  36                         clock-frequency = <264000000>;
  37                 };
  38         };
  39
  40         memory {
  41                 device_type = "memory";
  42                 reg = <0x00000000 0x10000000>;
  43         };
  44
  45         soc: soc8309@e0000000 {
  46                 #address-cells = <1>;
  47                 #size-cells = <1>;
  48                 device_type = "soc";
  49                 compatible = "simple-bus";
  50                 ranges = <0x0 0xe0000000 0x00100000>;
  51                 reg = <0xe0000000 0x00000200>;
  52                 bus-frequency = <264000000>;
  53
  54                 i2c@3000 {
  55                         #address-cells = <1>;
  56                         #size-cells = <0>;
  57                         cell-index = <0>;
  58                         compatible = "fsl,mpc8313-i2c","fsl-i2c";
  59                         reg = <0x3000 0x100>;
  60                         interrupts = <14 0x8>;
  61                         interrupt-parent = <&ipic>;
  62                         clock-frequency = <400000>;
  63
  64                         mux@70 {
  65                                 compatible = "nxp,pca9547";
  66                                 reg = <0x70>;
  67                                 #address-cells = <1>;
  68                                 #size-cells = <0>;
  69
  70                                 i2c@1 {
  71                                         reg = <1>;
  72                                         #address-cells = <1>;
  73                                         #size-cells = <0>;
  74
  75                                         /*
  76                                          * Inventory EEPROM of the
  77                                          * unit itself
  78                                          */
  79                                         ivm@50 {
  80                                                 label = "MAIN_CTRL";
  81                                                 compatible = "dummy";
  82                                                 reg = <0x50>;
  83                                         };
  84                                 };
  85
  86                                 i2c@2 {
  87                                         reg = <2>;
  88                                         #address-cells = <1>;
  89                                         #size-cells = <0>;
  90
  91                                         /* Temperature sensors */
  92                                         temp@48 {
  93                                                 label = "front";
  94                                                 compatible = "national,lm75";
  95                                                 reg = <0x48>;
  96                                         };
  97
  98                                         temp@49 {
  99                                                 label = "board";
 100                                                 compatible = "national,lm75";
 101                                                 reg = <0x49>;
 102                                         };
 103
 104                                         temp@4a {
 105                                                 label = "power";
 106                                                 compatible = "national,lm75";
 107                                                 reg = <0x4a>;
 108                                         };
 109
 110                                         temp@4b {
 111                                                 label = "bottom";
 112                                                 compatible = "national,lm75";
 113                                                 reg = <0x4b>;
 114                                         };
 115                                 };
 116
 117                                 i2c@6 {
 118                                         reg = <6>;
 119                                         #address-cells = <1>;
 120                                         #size-cells = <0>;
 121
 122                                 };
 123
 124                                 i2c@5 {
 125                                         reg = <5>;
 126                                         #address-cells = <1>;
 127                                         #size-cells = <0>;
 128
 129                                 };
 130
 131                                 i2c@7 {
 132                                         reg = <7>;
 133                                         #address-cells = <1>;
 134                                         #size-cells = <0>;
 135
 136                                 };
 137
 138                                 i2c@3 {
 139                                         reg = <3>;
 140                                         #address-cells = <1>;
 141                                         #size-cells = <0>;
 142
 143                                 };
 144                         };
 145                 };
 146
 147                 serial0: serial@4500 {
 148                         cell-index = <0>;
 149                         device_type = "serial";
 150                         compatible = "fsl,ns16550", "ns16550";
 151                         reg = <0x4500 0x100>;
 152                         clock-frequency = <264000000>;
 153                         interrupts = <9 0x8>;
 154                         interrupt-parent = <&ipic>;
 155                 };
 156
 157                 dma@82a8 {
 158                         #address-cells = <1>;
 159                         #size-cells = <1>;
 160                         compatible = "fsl,mpc8309-dma", "fsl,elo-dma";
 161                         reg = <0x82a8 4>;
 162                         ranges = <0 0x8100 0x1a8>;
 163                         interrupt-parent = <&ipic>;
 164                         interrupts = <71 8>;
 165                         cell-index = <0>;
 166                         dma-channel@0 {
 167                                 compatible = "fsl,mpc8309-dma-channel",
 168                                                 "fsl,elo-dma-channel";
 169                                 reg = <0 0x80>;
 170                                 interrupt-parent = <&ipic>;
 171                                 interrupts = <71 8>;
 172                         };
 173                         dma-channel@80 {
 174                                 compatible = "fsl,mpc8309-dma-channel",
 175                                                 "fsl,elo-dma-channel";
 176                                 reg = <0x80 0x80>;
 177                                 interrupt-parent = <&ipic>;
 178                                 interrupts = <71 8>;
 179                         };
 180                         dma-channel@100 {
 181                                 compatible = "fsl,mpc8309-dma-channel",
 182                                                 "fsl,elo-dma-channel";
 183                                 reg = <0x100 0x80>;
 184                                 interrupt-parent = <&ipic>;
 185                                 interrupts = <71 8>;
 186                         };
 187                         dma-channel@180 {
 188                                 compatible = "fsl,mpc8309-dma-channel",
 189                                                 "fsl,elo-dma-channel";
 190                                 reg = <0x180 0x28>;
 191                                 interrupt-parent = <&ipic>;
 192                                 interrupts = <71 8>;
 193                         };
 194                 };
 195
 196                 ipic: pic@700 {
 197                         #address-cells = <0>;
 198                         #interrupt-cells = <2>;
 199                         compatible = "fsl,pq2pro-pic", "fsl,ipic";
 200                         interrupt-controller;
 201                         reg = <0x700 0x100>;
 202                         device_type = "ipic";
 203                 };
 204
 205                 gpio1: gpio-controller@c00 {
 206                         #gpio-cells = <2>;
 207                         compatible = "fsl,mpc8309-gpio", "fsl,mpc8349-gpio";
 208                         reg = <0xc00 0x100>;
 209                         interrupts = <75 0x8>;
 210                         interrupt-parent = <&ipic>;
 211                         gpio-controller;
 212                         interrupt-controller;
 213                         #interrupt-cells = <2>;
 214                 };
 215
 216                 gpio2: gpio-controller@d00 {
 217                         #gpio-cells = <2>;
 218                         compatible = "fsl,mpc8309-gpio", "fsl,mpc8349-gpio";
 219                         reg = <0xd00 0x100>;
 220                         interrupts = <75 0x8>;
 221                         interrupt-parent = <&ipic>;
 222                         gpio-controller;
 223                         interrupt-controller;
 224                         #interrupt-cells = <2>;
 225                 };
 226
 227                 spi@7000 {
 228                         cell-index = <0>;
 229                         compatible = "fsl,spi";
 230                         reg = <0x7000 0x1000>;
 231                         interrupts = <16 0x8>;
 232                         interrupt-parent = <&ipic>;
 233                         mode = "cpu";
 234                         #address-cells = <1>;
 235                         #size-cells = <0>;
 236
 237                         /* GPIO_15 chipselect for ZYNQ flash */
 238                         gpios = <&gpio1 15 0>;
 239
 240                         zynq_flash@0 {
 241                                 #address-cells = <1>;
 242                                 #size-cells = <1>;
 243                                 compatible = "spansion,m25p80";
 244                                 reg = <0>;
 245                                 spi-max-frequency = <4000000>;
 246                                 m25p,fast-read;
 247                                 partition@0 {
 248                                         label = "bootloader";
 249                                         reg = <0x0 0x01000000>;
 250                                 };
 251                         };
 252                 };
 253         };
 254
 255         qe: qe@e0100000 {
 256                 #address-cells = <1>;
 257                 #size-cells = <1>;
 258                 device_type = "qe";
 259                 compatible = "fsl,qe";
 260                 ranges = <0x0 0xe0100000 0x00100000>;
 261                 reg = <0xe0100000 0x480>;
 262                 brg-frequency = <0>;
 263                 bus-frequency = <396000000>;
 264                 fsl,qe-num-snums = <32>;
 265
 266                 muram@10000 {
 267                         #address-cells = <1>;
 268                         #size-cells = <1>;
 269                         compatible = "fsl,qe-muram", "fsl,cpm-muram";
 270                         ranges = <0x0 0x00010000 0x00004000>;
 271
 272                         data-only@0 {
 273                                 compatible = "fsl,qe-muram-data",
 274                                              "fsl,cpm-muram-data";
 275                                 reg = <0x0 0x4000>;
 276                         };
 277                 };
 278
 279                 /* ZYNQ (UCC1, MDIO 0x10, MII) */
 280                 enet_zynq: ethernet@2000 {
 281                         device_type = "network";
 282                         compatible = "ucc_geth";
 283                         cell-index = <1>;
 284                         reg = <0x2000 0x200>;
 285                         interrupts = <32>;
 286                         interrupt-parent = <&qeic>;
 287                         local-mac-address = [ 00 00 00 00 00 00 ];
 288                         /*id=0, full-dup, 100M, no-pause, no-asym_p*/
 289                         fixed-link = <0 1 100 0 0>;
 290                         rx-clock-name = "clk9";
 291                         tx-clock-name = "clk10";
 292                         phy-connection-type = "mii";
 293                 };
 294
 295                 /* Piggy2 (UCC3, MDIO 0x00, RMII) */
 296                 enet_piggy2: ucc@2200 {
 297                         device_type = "network";
 298                         compatible = "ucc_geth";
 299                         cell-index = <3>;
 300                         reg = <0x2200 0x200>;
 301                         interrupts = <34>;
 302                         interrupt-parent = <&qeic>;
 303                         local-mac-address = [ 00 00 00 00 00 00 ];
 304                         rx-clock-name = "none";
 305                         tx-clock-name = "clk12";
 306                         phy-handle = <&phy_piggy2>;
 307                         phy-connection-type = "rmii";
 308                 };
 309
 310                 mdio@2320 {
 311                         #address-cells = <1>;
 312                         #size-cells = <0>;
 313                         reg = <0x2320 0x38>;
 314                         compatible = "fsl,ucc-mdio";
 315
 316                         /* Piggy2 (UCC3, MDIO 0x00, RMII) */
 317                         phy_piggy2: ethernet-phy@0 {
 318                                 reg = <0x0>;
 319                                 device_type = "ethernet-phy";
 320                         };
 321
 322                         /* Explicitly set the tbi-phy to a non-zero address
 323                          * so that it does not conflict with phy_piggy2 that
 324                          * is unfortunately at address 0
 325                          */
 326                         tbi1: tbi-phy@1 {
 327                                 reg = <0x1>;
 328                                 device_type = "tbi-phy";
 329                         };
 330                 };
 331
 332                 qeic: interrupt-controller@80 {
 333                         interrupt-controller;
 334                         compatible = "fsl,qe-ic";
 335                         #address-cells = <0>;
 336                         #interrupt-cells = <1>;
 337                         reg = <0x80 0x80>;
 338                         big-endian;
 339                         interrupts = <32 8 33 8>;
 340                         interrupt-parent = <&ipic>;
 341                 };
 342                 bootcount@0x13ff8 {
 343                         device_type = "bootcount";
 344                         compatible = "u-boot,bootcount";
 345                         reg = <0x13ff8 0x08>;
 346                 };
 347
 348         };
 349         localbus@e0005000 {
 350                 #address-cells = <2>;
 351                 #size-cells = <1>;
 352                 compatible = "fsl,mpc8309-localbus", "fsl,pq2pro-localbus",
 353                              "simple-bus";
 354                 reg = <0xe0005000 0xd8>;
 355                 ranges = <0 0 0xf0000000 0x04000000
 356                         1 0 0xe8000000 0x01000000
 357                         2 0 0xe0000000 0x10000000
 358                         3 0 0xb0000000 0x10000000>;
 359
 360                 flash@0,0 {
 361                         compatible = "cfi-flash";
 362                         reg = <0 0x00000000 0x04000000>;
 363                         bank-width = <2>;
 364                         nornand = "nor";
 365                         #address-cells = <1>;
 366                         #size-cells = <1>;
 367                         use-advanced-sector-protection;
 368                         partition@0 { /* 768KB */
 369                                 label = "u-boot";
 370                                 reg = <0 0xc0000>;
 371                         };
 372                         partition@c0000 { /* 256KB */
 373                                 label = "qe-fw";
 374                                 reg = <0xc0000 0x40000>;
 375                         };
 376                         partition@100000 { /* 128KB */
 377                                 label = "env";
 378                                 reg = <0x100000 0x20000>;
 379                         };
 380                         partition@120000 { /* 128KB */
 381                                 label = "envred";
 382                                 reg = <0x120000 0x20000>;
 383                         };
 384                         partition@140000 { /* 64256KB */
 385                                 label = "ubi0";
 386                                 reg = <0x140000 0x3EC0000>;
 387                         };
 388                 };
 389         };
 390 };
 391
 392 #include "km8309-uboot.dtsi"