arch/powerpc/dts/kmopti2.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * ABB PGGA OPTI2 Device Tree Source
   4  *
   5  * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
   6  *
   7  */
   8
   9 /dts-v1/;
  10
  11 #include "km8321.dtsi"
  12
  13 / {
  14         model = "KMOPTI2";
  15         compatible = "ABB,kmpbec8321";
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         aliases {
  20                 ethernet0 = &enet_piggy2;
  21                 serial0 = &serial0;
  22         };
  23 };
  24
  25 &i2c0 {
  26         mux@70 {
  27                 compatible = "nxp,pca9547";
  28                 reg = <0x70>;
  29                 #address-cells = <1>;
  30                 #size-cells = <0>;
  31
  32                 i2c@1 {
  33                         reg = <1>;
  34                         #address-cells = <1>;
  35                         #size-cells = <0>;
  36
  37                         /* Inventory EEPROM of the unit itself */
  38                         ivm@50 {
  39                                 label = "MAIN_CTRL";
  40                                 compatible = "dummy";
  41                                 reg = <0x50>;
  42                         };
  43                 };
  44
  45                 i2c@2 {
  46                         reg = <2>;
  47                         #address-cells = <1>;
  48                         #size-cells = <0>;
  49
  50                         /* Temperature sensors */
  51                         temp@49 {
  52                                 label = "board";
  53                                 compatible = "national,lm75";
  54                                 reg = <0x49>;
  55                         };
  56
  57                         temp@4a {
  58                                 label = "power";
  59                                 compatible = "national,lm75";
  60                                 reg = <0x4a>;
  61                         };
  62                 };
  63
  64                 i2c@6 {
  65                         reg = <6>;
  66                         #address-cells = <1>;
  67                         #size-cells = <0>;
  68                 };
  69
  70                 i2c@5 {
  71                         reg = <5>;
  72                         #address-cells = <1>;
  73                         #size-cells = <0>;
  74                 };
  75
  76                 i2c@4 {
  77                         reg = <4>;
  78                         #address-cells = <1>;
  79                         #size-cells = <0>;
  80                 };
  81
  82                 i2c@3 {
  83                         reg = <3>;
  84                         #address-cells = <1>;
  85                         #size-cells = <0>;
  86                 };
  87         };
  88 };
  89
  90 &par_io {
  91         /* UCC5 as HDLC controller for ICN */
  92         pio_ucc5: ucc_pin@04 {
  93                 pio-map = <
  94                         /* port  pin  dir  open_drain  assignment  has_irq */
  95                         2   0  1  0  2  0 /* TxD0 */
  96                         2   8  2  0  2  0 /* RxD0 */
  97                         2  29  2  0  2  0 /* CTS */
  98                         3  30  2  0  1  0 /* ICN CLK */
  99                         >;
 100         };
 101
 102         /* UCC4 Piggy Ethernet */
 103         pio_ucc4: ucc_pin@03 {
 104                 pio-map = <
 105                         /* port pin dir open_drain assignment has_irq */
 106                         3   4  3  0  2  0 /* MDIO */
 107                         3   5  1  0  2  0 /* MDC  */
 108
 109                         1 18  1  0  1  0 /* TxD0 */
 110                         1 19  1  0  1  0 /* TxD1 */
 111                         1 22  2  0  1  0 /* RxD0 */
 112                         1 23  2  0  1  0 /* RxD1 */
 113                         1 26  2  0  1  0 /* RX_ER */
 114                         1 28  2  0  1  0 /* RX_DV */
 115                         1 30  1  0  1  0 /* TX_EN */
 116                         1 31  2  0  1  0 /* CRS */
 117                         3 10  2  0  3  0 /* UCC4_RMII_CLK (CLK17) */
 118                 >;
 119         };
 120
 121         pio_spi: spi_pin@01 {
 122                 pio-map = <
 123                         /* port  pin  dir  open_drain  assignment  has_irq  */
 124                         3  0  3  0  1  0 /* SPI_MOSI (PD0, bi, f3)  */
 125                         3  1  3  0  1  0 /* SPI_MISO (PD1, bi, f3)  */
 126                         3  2  3  0  1  0 /* SPI_CLK  (PD2, bi, f3)  */
 127                 >;
 128         };
 129 };
 130
 131 &localbus {
 132         ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */
 133                 1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */
 134                 2 0 0xa0000000 0x10000000 /* LB 2 PAXE */
 135                 3 0 0xb0000000 0x10000000>; /* LB 3 OPI2 */
 136
 137         flash@0,0 {
 138                 compatible = "cfi-flash";
 139                 reg = <0 0x00000000 0x04000000>;
 140                 bank-width = <2>;
 141                 #address-cells = <1>;
 142                 #size-cells = <1>;
 143                 use-advanced-sector-protection;
 144                 partition@0 { /* 768KB */
 145                         label = "u-boot";
 146                         reg = <0 0xC0000>;
 147                 };
 148                 partition@c0000 { /* 128KB */
 149                         label = "env";
 150                         reg = <0xc0000 0x20000>;
 151                 };
 152                 partition@e0000 { /* 128KB */
 153                         label = "envred";
 154                         reg = <0xe0000 0x20000>;
 155                 };
 156                 partition@100000 { /* 64512KB */
 157                         label = "ubi0";
 158                         reg = <0x100000 0x3F00000>;
 159                 };
 160         };
 161 };