2 * linux/arch/powerpc/kernel/traps.c
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
6 * Modified by Cort Dougan (cort@cs.nmt.edu)
7 * and Paul Mackerras (paulus@cs.anu.edu.au)
10 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * This file handles the architecture-dependent parts of hardware exceptions
38 #include <asm/processor.h>
40 DECLARE_GLOBAL_DATA_PTR;
42 /* Returns 0 if exception not found and fixup otherwise. */
43 extern unsigned long search_exception_table(unsigned long);
45 /* THIS NEEDS CHANGING to use the board info structure.
47 #define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize)
49 static __inline__ void set_tsr(unsigned long val)
51 #if defined(CONFIG_440)
52 asm volatile("mtspr 0x150, %0" : : "r" (val));
54 asm volatile("mttsr %0" : : "r" (val));
58 static __inline__ unsigned long get_esr(void)
62 #if defined(CONFIG_440)
63 asm volatile("mfspr %0, 0x03e" : "=r" (val) :);
65 asm volatile("mfesr %0" : "=r" (val) :);
70 #define ESR_MCI 0x80000000
71 #define ESR_PIL 0x08000000
72 #define ESR_PPR 0x04000000
73 #define ESR_PTR 0x02000000
74 #define ESR_DST 0x00800000
75 #define ESR_DIZ 0x00400000
76 #define ESR_U0F 0x00008000
78 #if defined(CONFIG_CMD_BEDBUG)
79 extern void do_bedbug_breakpoint(struct pt_regs *);
83 * Trap & Exception support
87 print_backtrace(unsigned long *sp)
92 printf("Call backtrace: ");
94 if ((uint)sp > END_OF_MEM)
102 sp = (unsigned long *)*sp;
107 void show_regs(struct pt_regs * regs)
111 printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DEAR: %08lX\n",
112 regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
113 printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
114 regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
115 regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0,
116 regs->msr&MSR_IR ? 1 : 0,
117 regs->msr&MSR_DR ? 1 : 0);
120 for (i = 0; i < 32; i++) {
122 printf("GPR%02d: ", i);
125 printf("%08lX ", regs->gpr[i]);
134 _exception(int signr, struct pt_regs *regs)
137 print_backtrace((unsigned long *)regs->gpr[1]);
142 MachineCheckException(struct pt_regs *regs)
144 unsigned long fixup, val;
145 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
151 if ((fixup = search_exception_table(regs->nip)) != 0) {
155 mtspr(SPRN_MCSR, val);
159 #if defined(CONFIG_CMD_KGDB)
160 if (debugger_exception_handler && (*debugger_exception_handler)(regs))
164 printf("Machine Check Exception.\n");
165 printf("Caused by (from msr): ");
166 printf("regs %p ", regs);
170 #if !defined(CONFIG_440) && !defined(CONFIG_405EX)
172 printf("Instruction");
173 mtspr(ESR, val & ~ESR_IMCP);
177 printf(" machine check.\n");
179 #elif defined(CONFIG_440) || defined(CONFIG_405EX)
181 printf("Instruction Synchronous Machine Check exception\n");
182 mtspr(SPRN_ESR, val & ~ESR_IMCP);
186 printf("Instruction Read PLB Error\n");
187 #if defined(CONFIG_440)
189 printf("Data Read PLB Error\n");
191 printf("Data Write PLB Error\n");
194 printf("Data PLB Error\n");
197 printf("TLB Parity Error\n");
199 /*flush_instruction_cache(); */
200 printf("I-Cache Parity Error\n");
203 printf("D-Cache Search Parity Error\n");
205 printf("D-Cache Flush Parity Error\n");
207 printf("Machine Check exception is imprecise\n");
210 mtspr(SPRN_MCSR, val);
212 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
213 mfsdram(DDR0_00, val) ;
214 printf("DDR0: DDR0_00 %lx\n", val);
215 val = (val >> 16) & 0xff;
217 printf("DDR0: At least one interrupt active\n");
219 printf("DDR0: DRAM initialization complete.\n");
221 printf("DDR0: Multiple uncorrectable ECC events.\n");
225 printf("DDR0: Single uncorrectable ECC event.\n");
229 printf("DDR0: Multiple correctable ECC events.\n");
233 printf("DDR0: Single correctable ECC event.\n");
237 printf("Multiple accesses outside the defined"
238 " physical memory space detected\n");
240 printf("DDR0: Single access outside the defined"
241 " physical memory space detected.\n");
243 mfsdram(DDR0_01, val);
244 val = (val >> 8) & 0x7;
247 printf("DDR0: Write Out-of-Range command\n");
250 printf("DDR0: Read Out-of-Range command\n");
253 printf("DDR0: Masked write Out-of-Range command\n");
256 printf("DDR0: Wrap write Out-of-Range command\n");
259 printf("DDR0: Wrap read Out-of-Range command\n");
262 mfsdram(DDR0_01, value2);
263 printf("DDR0: No DDR0 error know 0x%lx %x\n", val, value2);
265 mfsdram(DDR0_23, val);
266 if (((val >> 16) & 0xff) && corr_ecc)
267 printf("DDR0: Syndrome for correctable ECC event 0x%lx\n",
269 mfsdram(DDR0_23, val);
270 if (((val >> 8) & 0xff) && uncorr_ecc)
271 printf("DDR0: Syndrome for uncorrectable ECC event 0x%lx\n",
273 mfsdram(DDR0_33, val);
275 printf("DDR0: Address of command that caused an "
276 "Out-of-Range interrupt %lx\n", val);
277 mfsdram(DDR0_34, val);
278 if (val && uncorr_ecc)
279 printf("DDR0: Address of uncorrectable ECC event %lx\n", val);
280 mfsdram(DDR0_35, val);
281 if (val && uncorr_ecc)
282 printf("DDR0: Address of uncorrectable ECC event %lx\n", val);
283 mfsdram(DDR0_36, val);
284 if (val && uncorr_ecc)
285 printf("DDR0: Data of uncorrectable ECC event 0x%08lx\n", val);
286 mfsdram(DDR0_37, val);
287 if (val && uncorr_ecc)
288 printf("DDR0: Data of uncorrectable ECC event 0x%08lx\n", val);
289 mfsdram(DDR0_38, val);
291 printf("DDR0: Address of correctable ECC event %lx\n", val);
292 mfsdram(DDR0_39, val);
294 printf("DDR0: Address of correctable ECC event %lx\n", val);
295 mfsdram(DDR0_40, val);
297 printf("DDR0: Data of correctable ECC event 0x%08lx\n", val);
298 mfsdram(DDR0_41, val);
300 printf("DDR0: Data of correctable ECC event 0x%08lx\n", val);
301 #endif /* CONFIG_440EPX */
302 #endif /* CONFIG_440 */
304 print_backtrace((unsigned long *)regs->gpr[1]);
305 panic("machine check");
309 AlignmentException(struct pt_regs *regs)
311 #if defined(CONFIG_CMD_KGDB)
312 if (debugger_exception_handler && (*debugger_exception_handler)(regs))
317 print_backtrace((unsigned long *)regs->gpr[1]);
318 panic("Alignment Exception");
322 ProgramCheckException(struct pt_regs *regs)
326 #if defined(CONFIG_CMD_KGDB)
327 if (debugger_exception_handler && (*debugger_exception_handler)(regs))
334 if( esr_val & ESR_PIL )
335 printf( "** Illegal Instruction **\n" );
336 else if( esr_val & ESR_PPR )
337 printf( "** Privileged Instruction **\n" );
338 else if( esr_val & ESR_PTR )
339 printf( "** Trap Instruction **\n" );
341 print_backtrace((unsigned long *)regs->gpr[1]);
342 panic("Program Check Exception");
346 DecrementerPITException(struct pt_regs *regs)
349 * Reset PIT interrupt
354 * Call timer_interrupt routine in interrupts.c
356 timer_interrupt(NULL);
361 UnknownException(struct pt_regs *regs)
363 #if defined(CONFIG_CMD_KGDB)
364 if (debugger_exception_handler && (*debugger_exception_handler)(regs))
368 printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
369 regs->nip, regs->msr, regs->trap);
374 DebugException(struct pt_regs *regs)
376 printf("Debugger trap at @ %lx\n", regs->nip );
378 #if defined(CONFIG_CMD_BEDBUG)
379 do_bedbug_breakpoint( regs );
383 /* Probe an address by reading. If not present, return -1, otherwise
387 addr_probe(uint *addr)
392 __asm__ __volatile__( \
393 "1: lwz %0,0(%1)\n" \
397 ".section .fixup,\"ax\"\n" \
400 ".section __ex_table,\"a\"\n" \
404 : "=r" (retval) : "r"(addr));