2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
6 * Copyright (c) 2008 Nuovation System Designs, LLC
7 * Grant Erickson <gerickson@nuovations.com>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 /*------------------------------------------------------------------------------+
28 * This source code is dual-licensed. You may use it under the terms of the
29 * GNU General Public License version 2, or under the license below.
31 * This source code has been made available to you by IBM on an AS-IS
32 * basis. Anyone receiving this source is licensed under IBM
33 * copyrights to use it in any way he or she deems fit, including
34 * copying it, modifying it, compiling it, and redistributing it either
35 * with or without modifications. No license under IBM patents or
36 * patent applications is to be implied by the copyright license.
38 * Any user of this software should understand that IBM cannot provide
39 * technical support for this software and will not be responsible for
40 * any consequences resulting from the use of this software.
42 * Any person who transfers this source code or any derivative work
43 * must include the IBM copyright notice, this paragraph, and the
44 * preceding two paragraphs in the transferred software.
46 * COPYRIGHT I B M CORPORATION 1995
47 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
48 *-------------------------------------------------------------------------------
52 * Startup code for IBM/AMCC PowerPC 4xx (PPC4xx) based boards
54 * The following description only applies to the NOR flash style booting.
55 * NAND booting is different. For more details about NAND booting on 4xx
56 * take a look at doc/README.nand-boot-ppc440.
58 * The CPU starts at address 0xfffffffc (last word in the address space).
59 * The U-Boot image therefore has to be located in the "upper" area of the
60 * flash (e.g. 512MiB - 0xfff80000 ... 0xffffffff). The default value for
61 * the boot chip-select (CS0) is quite big and covers this area. On the
62 * 405EX this is for example 0xffe00000 ... 0xffffffff. U-Boot will
63 * reconfigure this CS0 (and other chip-selects as well when configured
64 * this way) in the boot process to the "correct" values matching the
68 #include <asm-offsets.h>
70 #include <asm/ppc4xx.h>
71 #include <timestamp.h>
74 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
76 #include <ppc_asm.tmpl>
79 #include <asm/cache.h>
81 #include <asm/ppc4xx-isram.h>
83 #ifndef CONFIG_IDENT_STRING
84 #define CONFIG_IDENT_STRING ""
87 #ifdef CONFIG_SYS_INIT_DCACHE_CS
88 # if (CONFIG_SYS_INIT_DCACHE_CS == 0)
91 # if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
92 # define PBxAP_VAL CONFIG_SYS_EBC_PB0AP
93 # define PBxCR_VAL CONFIG_SYS_EBC_PB0CR
96 # if (CONFIG_SYS_INIT_DCACHE_CS == 1)
99 # if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR))
100 # define PBxAP_VAL CONFIG_SYS_EBC_PB1AP
101 # define PBxCR_VAL CONFIG_SYS_EBC_PB1CR
104 # if (CONFIG_SYS_INIT_DCACHE_CS == 2)
107 # if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR))
108 # define PBxAP_VAL CONFIG_SYS_EBC_PB2AP
109 # define PBxCR_VAL CONFIG_SYS_EBC_PB2CR
112 # if (CONFIG_SYS_INIT_DCACHE_CS == 3)
115 # if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR))
116 # define PBxAP_VAL CONFIG_SYS_EBC_PB3AP
117 # define PBxCR_VAL CONFIG_SYS_EBC_PB3CR
120 # if (CONFIG_SYS_INIT_DCACHE_CS == 4)
123 # if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR))
124 # define PBxAP_VAL CONFIG_SYS_EBC_PB4AP
125 # define PBxCR_VAL CONFIG_SYS_EBC_PB4CR
128 # if (CONFIG_SYS_INIT_DCACHE_CS == 5)
131 # if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR))
132 # define PBxAP_VAL CONFIG_SYS_EBC_PB5AP
133 # define PBxCR_VAL CONFIG_SYS_EBC_PB5CR
136 # if (CONFIG_SYS_INIT_DCACHE_CS == 6)
139 # if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR))
140 # define PBxAP_VAL CONFIG_SYS_EBC_PB6AP
141 # define PBxCR_VAL CONFIG_SYS_EBC_PB6CR
144 # if (CONFIG_SYS_INIT_DCACHE_CS == 7)
147 # if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR))
148 # define PBxAP_VAL CONFIG_SYS_EBC_PB7AP
149 # define PBxCR_VAL CONFIG_SYS_EBC_PB7CR
159 * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB
160 * used as temporary stack pointer for the primordial stack
162 # ifndef CONFIG_SYS_INIT_DCACHE_PBxAR
163 # define CONFIG_SYS_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \
164 EBC_BXAP_TWT_ENCODE(7) | \
165 EBC_BXAP_BCE_DISABLE | \
166 EBC_BXAP_BCT_2TRANS | \
167 EBC_BXAP_CSN_ENCODE(0) | \
168 EBC_BXAP_OEN_ENCODE(0) | \
169 EBC_BXAP_WBN_ENCODE(0) | \
170 EBC_BXAP_WBF_ENCODE(0) | \
171 EBC_BXAP_TH_ENCODE(2) | \
172 EBC_BXAP_RE_DISABLED | \
173 EBC_BXAP_SOR_NONDELAYED | \
174 EBC_BXAP_BEM_WRITEONLY | \
175 EBC_BXAP_PEN_DISABLED)
176 # endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */
177 # ifndef CONFIG_SYS_INIT_DCACHE_PBxCR
178 # define CONFIG_SYS_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR) | \
182 # endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */
183 # ifndef CONFIG_SYS_INIT_RAM_PATTERN
184 # define CONFIG_SYS_INIT_RAM_PATTERN 0xDEADDEAD
186 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
188 #if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_SIZE > (4 << 10)))
189 #error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_SIZE!
193 * Unless otherwise overriden, enable two 128MB cachable instruction regions
194 * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering
195 * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions.
197 #if !defined(CONFIG_SYS_FLASH_BASE)
198 /* If not already defined, set it to the "last" 128MByte region */
199 # define CONFIG_SYS_FLASH_BASE 0xf8000000
201 #if !defined(CONFIG_SYS_ICACHE_SACR_VALUE)
202 # define CONFIG_SYS_ICACHE_SACR_VALUE \
203 (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \
204 PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \
205 PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE))
206 #endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */
208 #if !defined(CONFIG_SYS_DCACHE_SACR_VALUE)
209 # define CONFIG_SYS_DCACHE_SACR_VALUE \
211 #endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */
213 #if !defined(CONFIG_SYS_TLB_FOR_BOOT_FLASH)
214 #define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0 /* use TLB 0 as default */
217 #define function_prolog(func_name) .text; \
221 #define function_epilog(func_name) .type func_name,@function; \
222 .size func_name,.-func_name
224 /* We don't want the MMU yet.
227 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
230 .extern ext_bus_cntlr_init
231 #ifdef CONFIG_NAND_U_BOOT
232 .extern reconfig_tlb0
236 * Set up GOT: Global Offset Table
238 * Use r12 to access the GOT
240 #if !defined(CONFIG_NAND_SPL)
242 GOT_ENTRY(_GOT2_TABLE_)
243 GOT_ENTRY(_FIXUP_TABLE_)
246 GOT_ENTRY(_start_of_vectors)
247 GOT_ENTRY(_end_of_vectors)
248 GOT_ENTRY(transfer_to_handler)
250 GOT_ENTRY(__init_end)
251 GOT_ENTRY(__bss_end__)
252 GOT_ENTRY(__bss_start)
254 #endif /* CONFIG_NAND_SPL */
256 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
258 * NAND U-Boot image is started from offset 0
261 #if defined(CONFIG_440)
265 #if defined(__pic__) && __pic__ == 1
266 /* Needed for upcoming -msingle-pic-base */
267 bl _GLOBAL_OFFSET_TABLE_@local-4
270 bl cpu_init_f /* run low-level CPU init code (from Flash) */
272 /* NOTREACHED - board_init_f() does not return */
275 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_BOOT_FROM_XMD)
277 * 4xx RAM-booting U-Boot image is started from offset 0
284 * 440 Startup -- on reset only the top 4k of the effective
285 * address space is mapped in by an entry in the instruction
286 * and data shadow TLB. The .bootpg section is located in the
287 * top 4k & does only what's necessary to map in the the rest
288 * of the boot rom. Once the boot rom is mapped in we can
289 * proceed with normal startup.
291 * NOTE: CS0 only covers the top 2MB of the effective address
295 #if defined(CONFIG_440)
296 #if !defined(CONFIG_NAND_SPL)
297 .section .bootpg,"ax"
301 /**************************************************************************/
303 /*--------------------------------------------------------------------+
304 | 440EPX BUP Change - Hardware team request
305 +--------------------------------------------------------------------*/
306 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
311 /*----------------------------------------------------------------+
312 | Core bug fix. Clear the esr
313 +-----------------------------------------------------------------*/
316 /*----------------------------------------------------------------*/
317 /* Clear and set up some registers. */
318 /*----------------------------------------------------------------*/
319 iccci r0,r0 /* NOTE: operands not used for 440 */
320 dccci r0,r0 /* NOTE: operands not used for 440 */
327 /* NOTE: 440GX adds machine check status regs */
328 #if defined(CONFIG_440) && !defined(CONFIG_440GP)
335 /*----------------------------------------------------------------*/
337 /*----------------------------------------------------------------*/
338 /* Disable store gathering & broadcast, guarantee inst/data
339 * cache block touch, force load/store alignment
340 * (see errata 1.12: 440_33)
342 lis r1,0x0030 /* store gathering & broadcast disable */
343 ori r1,r1,0x6000 /* cache touch */
346 /*----------------------------------------------------------------*/
347 /* Initialize debug */
348 /*----------------------------------------------------------------*/
350 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
351 bne skip_debug_init /* if set, don't clear debug register */
353 ori r1,r1,CCR0_DTB@l /* Disable Trace Broadcast */
367 mtspr SPRN_DBSR,r1 /* Clear all valid bits */
370 #if defined (CONFIG_440SPE)
371 /*----------------------------------------------------------------+
372 | Initialize Core Configuration Reg1.
373 | a. ICDPEI: Record even parity. Normal operation.
374 | b. ICTPEI: Record even parity. Normal operation.
375 | c. DCTPEI: Record even parity. Normal operation.
376 | d. DCDPEI: Record even parity. Normal operation.
377 | e. DCUPEI: Record even parity. Normal operation.
378 | f. DCMPEI: Record even parity. Normal operation.
379 | g. FCOM: Normal operation
380 | h. MMUPEI: Record even parity. Normal operation.
381 | i. FFF: Flush only as much data as necessary.
382 | j. TCS: Timebase increments from CPU clock.
383 +-----------------------------------------------------------------*/
387 /*----------------------------------------------------------------+
388 | Reset the timebase.
389 | The previous write to CCR1 sets the timebase source.
390 +-----------------------------------------------------------------*/
395 /*----------------------------------------------------------------*/
396 /* Setup interrupt vectors */
397 /*----------------------------------------------------------------*/
398 mtspr SPRN_IVPR,r0 /* Vectors start at 0x0000_0000 */
400 mtspr SPRN_IVOR0,r1 /* Critical input */
402 mtspr SPRN_IVOR1,r1 /* Machine check */
404 mtspr SPRN_IVOR2,r1 /* Data storage */
406 mtspr SPRN_IVOR3,r1 /* Instruction storage */
408 mtspr SPRN_IVOR4,r1 /* External interrupt */
410 mtspr SPRN_IVOR5,r1 /* Alignment */
412 mtspr SPRN_IVOR6,r1 /* Program check */
414 mtspr SPRN_IVOR7,r1 /* Floating point unavailable */
416 mtspr SPRN_IVOR8,r1 /* System call */
418 mtspr SPRN_IVOR9,r1 /* Auxiliary Processor unavailable */
420 mtspr SPRN_IVOR10,r1 /* Decrementer */
422 mtspr SPRN_IVOR13,r1 /* Data TLB error */
424 mtspr SPRN_IVOR14,r1 /* Instr TLB error */
426 mtspr SPRN_IVOR15,r1 /* Debug */
428 /*----------------------------------------------------------------*/
429 /* Configure cache regions */
430 /*----------------------------------------------------------------*/
448 /*----------------------------------------------------------------*/
449 /* Cache victim limits */
450 /*----------------------------------------------------------------*/
451 /* floors 0, ceiling max to use the entire cache -- nothing locked
458 /*----------------------------------------------------------------+
459 |Initialize MMUCR[STID] = 0.
460 +-----------------------------------------------------------------*/
467 /*----------------------------------------------------------------*/
468 /* Clear all TLB entries -- TID = 0, TS = 0 */
469 /*----------------------------------------------------------------*/
471 #ifdef CONFIG_SYS_RAMBOOT
472 li r4,0 /* Start with TLB #0 */
474 li r4,1 /* Start with TLB #1 */
476 li r1,64 /* 64 TLB entries */
477 sub r1,r1,r4 /* calculate last TLB # */
480 #ifdef CONFIG_SYS_RAMBOOT
481 tlbre r3,r4,0 /* Read contents from TLB word #0 to get EPN */
482 rlwinm. r3,r3,0,0xfffffc00 /* Mask EPN */
483 beq tlbnxt /* Skip EPN=0 TLB, this is the SDRAM TLB */
485 tlbwe r0,r4,0 /* Invalidate all entries (V=0)*/
488 tlbnxt: addi r4,r4,1 /* Next TLB */
491 /*----------------------------------------------------------------*/
492 /* TLB entry setup -- step thru tlbtab */
493 /*----------------------------------------------------------------*/
494 #if defined(CONFIG_440SPE_REVA)
495 /*----------------------------------------------------------------*/
496 /* We have different TLB tables for revA and rev B of 440SPe */
497 /*----------------------------------------------------------------*/
509 bl tlbtab /* Get tlbtab pointer */
512 li r1,0x003f /* 64 TLB entries max */
518 #ifdef CONFIG_SYS_RAMBOOT
519 tlbre r3,r4,0 /* Read contents from TLB word #0 */
520 rlwinm. r3,r3,0,0x00000200 /* Mask V (valid) bit */
521 bne tlbnx2 /* Skip V=1 TLB, this is the SDRAM TLB */
525 beq 2f /* 0 marks end */
528 tlbwe r0,r4,0 /* TLB Word 0 */
529 tlbwe r1,r4,1 /* TLB Word 1 */
530 tlbwe r2,r4,2 /* TLB Word 2 */
531 tlbnx2: addi r4,r4,1 /* Next TLB */
534 /*----------------------------------------------------------------*/
535 /* Continue from 'normal' start */
536 /*----------------------------------------------------------------*/
542 mtspr SPRN_SRR1,r0 /* Keep things disabled for now */
546 #endif /* CONFIG_440 */
549 * r3 - 1st arg to board_init(): IMMP pointer
550 * r4 - 2nd arg to board_init(): boot flag
552 #ifndef CONFIG_NAND_SPL
554 .long 0x27051956 /* U-Boot Magic Number */
555 .globl version_string
557 .ascii U_BOOT_VERSION
558 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
559 .ascii CONFIG_IDENT_STRING, "\0"
561 . = EXC_OFF_SYS_RESET
562 .globl _start_of_vectors
565 /* Critical input. */
566 CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
570 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
572 CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
573 #endif /* CONFIG_440 */
575 /* Data Storage exception. */
576 STD_EXCEPTION(0x300, DataStorage, UnknownException)
578 /* Instruction Storage exception. */
579 STD_EXCEPTION(0x400, InstStorage, UnknownException)
581 /* External Interrupt exception. */
582 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
584 /* Alignment exception. */
587 EXCEPTION_PROLOG(SRR0, SRR1)
592 addi r3,r1,STACK_FRAME_OVERHEAD
593 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
595 /* Program check exception */
598 EXCEPTION_PROLOG(SRR0, SRR1)
599 addi r3,r1,STACK_FRAME_OVERHEAD
600 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
604 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
605 STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
606 STD_EXCEPTION(0xa00, APU, UnknownException)
608 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
611 STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
612 STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
614 STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
615 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
616 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
618 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
620 .globl _end_of_vectors
627 /*****************************************************************************/
628 #if defined(CONFIG_440)
630 /*----------------------------------------------------------------*/
631 /* Clear and set up some registers. */
632 /*----------------------------------------------------------------*/
635 mtspr SPRN_DEC,r0 /* prevent dec exceptions */
636 mtspr SPRN_TBWL,r0 /* prevent fit & wdt exceptions */
638 mtspr SPRN_TSR,r1 /* clear all timer exception status */
639 mtspr SPRN_TCR,r0 /* disable all */
640 mtspr SPRN_ESR,r0 /* clear exception syndrome register */
641 mtxer r0 /* clear integer exception register */
643 /*----------------------------------------------------------------*/
644 /* Debug setup -- some (not very good) ice's need an event*/
645 /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */
646 /* value you need in this case 0x8cff 0000 should do the trick */
647 /*----------------------------------------------------------------*/
648 #if defined(CONFIG_SYS_INIT_DBCR)
651 mtspr SPRN_DBSR,r1 /* Clear all status bits */
652 lis r0,CONFIG_SYS_INIT_DBCR@h
653 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
658 /*----------------------------------------------------------------*/
659 /* Setup the internal SRAM */
660 /*----------------------------------------------------------------*/
663 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
664 /* Clear Dcache to use as RAM */
665 addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h
666 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
667 addis r4,r0,CONFIG_SYS_INIT_RAM_SIZE@h
668 ori r4,r4,CONFIG_SYS_INIT_RAM_SIZE@l
669 rlwinm. r5,r4,0,27,31
681 * Lock the init-ram/stack in d-cache, so that other regions
682 * may use d-cache as well
683 * Note, that this current implementation locks exactly 4k
684 * of d-cache, so please make sure that you don't define a
685 * bigger init-ram area. Take a look at the lwmon5 440EPx
686 * implementation as a reference.
690 /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
706 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
708 /* 440EP & 440GR are only 440er PPC's without internal SRAM */
709 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
710 /* not all PPC's have internal SRAM usable as L2-cache */
711 #if defined(CONFIG_440GX) || \
712 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
713 defined(CONFIG_460SX)
714 mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */
715 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
716 defined(CONFIG_APM821XX)
718 ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */
719 mtdcr L2_CACHE_CFG,r1
725 and r1,r1,r2 /* Disable parity check */
728 and r1,r1,r2 /* Disable pwr mgmt */
731 lis r1,0x8000 /* BAS = 8000_0000 */
732 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
733 ori r1,r1,0x0980 /* first 64k */
734 mtdcr ISRAM0_SB0CR,r1
736 ori r1,r1,0x0980 /* second 64k */
737 mtdcr ISRAM0_SB1CR,r1
739 ori r1,r1, 0x0980 /* third 64k */
740 mtdcr ISRAM0_SB2CR,r1
742 ori r1,r1, 0x0980 /* fourth 64k */
743 mtdcr ISRAM0_SB3CR,r1
744 #elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \
745 defined(CONFIG_460GT) || defined(CONFIG_APM821XX)
746 lis r1,0x0000 /* BAS = X_0000_0000 */
747 ori r1,r1,0x0984 /* first 64k */
748 mtdcr ISRAM0_SB0CR,r1
750 ori r1,r1,0x0984 /* second 64k */
751 mtdcr ISRAM0_SB1CR,r1
753 ori r1,r1, 0x0984 /* third 64k */
754 mtdcr ISRAM0_SB2CR,r1
756 ori r1,r1, 0x0984 /* fourth 64k */
757 mtdcr ISRAM0_SB3CR,r1
758 #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
759 defined(CONFIG_APM821XX)
763 and r1,r1,r2 /* Disable parity check */
766 and r1,r1,r2 /* Disable pwr mgmt */
769 lis r1,0x0004 /* BAS = 4_0004_0000 */
770 ori r1,r1,ISRAM1_SIZE /* ocm size */
771 mtdcr ISRAM1_SB0CR,r1
773 #elif defined(CONFIG_460SX)
774 lis r1,0x0000 /* BAS = 0000_0000 */
775 ori r1,r1,0x0B84 /* first 128k */
776 mtdcr ISRAM0_SB0CR,r1
778 ori r1,r1,0x0B84 /* second 128k */
779 mtdcr ISRAM0_SB1CR,r1
781 ori r1,r1, 0x0B84 /* third 128k */
782 mtdcr ISRAM0_SB2CR,r1
784 ori r1,r1, 0x0B84 /* fourth 128k */
785 mtdcr ISRAM0_SB3CR,r1
786 #elif defined(CONFIG_440GP)
787 ori r1,r1,0x0380 /* 8k rw */
788 mtdcr ISRAM0_SB0CR,r1
789 mtdcr ISRAM0_SB1CR,r0 /* Disable bank 1 */
791 #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
793 /*----------------------------------------------------------------*/
794 /* Setup the stack in internal SRAM */
795 /*----------------------------------------------------------------*/
796 lis r1,CONFIG_SYS_INIT_RAM_ADDR@h
797 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
800 stwu r0,-4(r1) /* Terminate call chain */
802 stwu r1,-8(r1) /* Save back chain and move SP */
803 lis r0,RESET_VECTOR@h /* Address of reset vector */
804 ori r0,r0, RESET_VECTOR@l
805 stwu r1,-8(r1) /* Save back chain and move SP */
806 stw r0,+12(r1) /* Save return addr (underflow vect) */
807 #if defined(__pic__) && __pic__ == 1
808 /* Needed for upcoming -msingle-pic-base */
809 bl _GLOBAL_OFFSET_TABLE_@local-4
812 #ifdef CONFIG_NAND_SPL
813 bl nand_boot_common /* will not return */
817 bl cpu_init_f /* run low-level CPU init code (from Flash) */
819 /* NOTREACHED - board_init_f() does not return */
822 #endif /* CONFIG_440 */
824 /*****************************************************************************/
826 /*----------------------------------------------------------------------- */
827 /* Set up some machine state registers. */
828 /*----------------------------------------------------------------------- */
829 addi r0,r0,0x0000 /* initialize r0 to zero */
830 mtspr SPRN_ESR,r0 /* clear Exception Syndrome Reg */
831 mttcr r0 /* timer control register */
832 mtexier r0 /* disable all interrupts */
833 addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
834 ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */
835 mtdbsr r4 /* clear/reset the dbsr */
836 mtexisr r4 /* clear all pending interrupts */
838 mtexier r4 /* enable critical exceptions */
839 addis r4,r0,0x0000 /* assume 403GCX - enable core clk */
840 ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */
841 mtiocr r4 /* since bit not used) & DRC to latch */
842 /* data bus on rising edge of CAS */
843 /*----------------------------------------------------------------------- */
845 /*----------------------------------------------------------------------- */
847 /*----------------------------------------------------------------------- */
848 /* Invalidate i-cache and d-cache TAG arrays. */
849 /*----------------------------------------------------------------------- */
850 addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */
851 addi r4,0,1024 /* 1/4 of I-cache */
856 addic. r3,r3,-16 /* move back one cache line */
857 bne ..cloop /* loop back to do rest until r3 = 0 */
860 /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
861 /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
864 /* first copy IOP480 register base address into r3 */
865 addis r3,0,0x5000 /* IOP480 register base address hi */
866 /* ori r3,r3,0x0000 / IOP480 register base address lo */
869 /* use r4 as the working variable */
870 /* turn on CS3 (LOCCTL.7) */
871 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
872 andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */
873 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
876 #ifdef CONFIG_DASA_SIM
877 /* use r4 as the working variable */
878 /* turn on MA17 (LOCCTL.7) */
879 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
880 ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */
881 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
884 /* turn on MA16..13 (LCS0BRD.12 = 0) */
885 lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
886 andi. r4,r4,0xefff /* make bit 12 = 0 */
887 stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
889 /* make sure above stores all comlete before going on */
892 /* last thing, set local init status done bit (DEVINIT.31) */
893 lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */
894 oris r4,r4,0x8000 /* make bit 31 = 1 */
895 stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */
897 /* clear all pending interrupts and disable all interrupts */
898 li r4,-1 /* set p1 to 0xffffffff */
899 stw r4,0x1b0(r3) /* clear all pending interrupts */
900 stw r4,0x1b8(r3) /* clear all pending interrupts */
901 li r4,0 /* set r4 to 0 */
902 stw r4,0x1b4(r3) /* disable all interrupts */
903 stw r4,0x1bc(r3) /* disable all interrupts */
905 /* make sure above stores all comlete before going on */
908 /* Set-up icache cacheability. */
909 lis r1, CONFIG_SYS_ICACHE_SACR_VALUE@h
910 ori r1, r1, CONFIG_SYS_ICACHE_SACR_VALUE@l
914 /* Set-up dcache cacheability. */
915 lis r1, CONFIG_SYS_DCACHE_SACR_VALUE@h
916 ori r1, r1, CONFIG_SYS_DCACHE_SACR_VALUE@l
919 addis r1,r0,CONFIG_SYS_INIT_RAM_ADDR@h
920 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack to SDRAM */
921 li r0, 0 /* Make room for stack frame header and */
922 stwu r0, -4(r1) /* clear final stack frame so that */
923 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
925 GET_GOT /* initialize GOT access */
926 #if defined(__pic__) && __pic__ == 1
927 /* Needed for upcoming -msingle-pic-base */
928 bl _GLOBAL_OFFSET_TABLE_@local-4
931 bl board_init_f /* run first part of init code (from Flash) */
932 /* NOTREACHED - board_init_f() does not return */
934 #endif /* CONFIG_IOP480 */
936 /*****************************************************************************/
937 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
938 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
939 defined(CONFIG_405EX) || defined(CONFIG_405)
940 /*----------------------------------------------------------------------- */
941 /* Clear and set up some registers. */
942 /*----------------------------------------------------------------------- */
944 #if !defined(CONFIG_405EX)
948 * On 405EX, completely clearing the SGR leads to PPC hangup
949 * upon PCIe configuration access. The PCIe memory regions
950 * need to be guarded!
957 mtesr r4 /* clear Exception Syndrome Reg */
958 mttcr r4 /* clear Timer Control Reg */
959 mtxer r4 /* clear Fixed-Point Exception Reg */
960 mtevpr r4 /* clear Exception Vector Prefix Reg */
961 addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
962 /* dbsr is cleared by setting bits to 1) */
963 mtdbsr r4 /* clear/reset the dbsr */
965 /* Invalidate the i- and d-caches. */
969 /* Set-up icache cacheability. */
970 lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h
971 ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l
975 /* Set-up dcache cacheability. */
976 lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h
977 ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l
980 #if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\
981 && !defined (CONFIG_XILINX_405)
982 /*----------------------------------------------------------------------- */
983 /* Tune the speed and size for flash CS0 */
984 /*----------------------------------------------------------------------- */
985 bl ext_bus_cntlr_init
988 #if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM))
990 * For boards that don't have OCM and can't use the data cache
991 * for their primordial stack, setup stack here directly after the
992 * SDRAM is initialized in ext_bus_cntlr_init.
994 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
995 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */
997 li r0, 0 /* Make room for stack frame header and */
998 stwu r0, -4(r1) /* clear final stack frame so that */
999 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
1001 * Set up a dummy frame to store reset vector as return address.
1002 * this causes stack underflow to reset board.
1004 stwu r1, -8(r1) /* Save back chain and move SP */
1005 lis r0, RESET_VECTOR@h /* Address of reset vector */
1006 ori r0, r0, RESET_VECTOR@l
1007 stwu r1, -8(r1) /* Save back chain and move SP */
1008 stw r0, +12(r1) /* Save return addr (underflow vect) */
1009 #endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */
1011 #if defined(CONFIG_405EP)
1012 /*----------------------------------------------------------------------- */
1013 /* DMA Status, clear to come up clean */
1014 /*----------------------------------------------------------------------- */
1015 addis r3,r0, 0xFFFF /* Clear all existing DMA status */
1019 bl ppc405ep_init /* do ppc405ep specific init */
1020 #endif /* CONFIG_405EP */
1022 #if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)
1023 #if defined(CONFIG_405EZ)
1024 /********************************************************************
1025 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
1026 *******************************************************************/
1028 * We can map the OCM on the PLB3, so map it at
1029 * CONFIG_SYS_OCM_DATA_ADDR + 0x8000
1031 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1032 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
1033 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
1034 mtdcr OCM0_PLBCR1,r3 /* Set PLB Access */
1035 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
1036 mtdcr OCM0_PLBCR2,r3 /* Set PLB Access */
1039 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1040 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
1041 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
1042 mtdcr OCM0_DSRC1, r3 /* Set Data Side */
1043 mtdcr OCM0_ISRC1, r3 /* Set Instruction Side */
1044 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
1045 mtdcr OCM0_DSRC2, r3 /* Set Data Side */
1046 mtdcr OCM0_ISRC2, r3 /* Set Instruction Side */
1047 addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
1048 mtdcr OCM0_DISDPC,r3
1051 #else /* CONFIG_405EZ */
1052 /********************************************************************
1053 * Setup OCM - On Chip Memory
1054 *******************************************************************/
1058 mfdcr r3, OCM0_ISCNTL /* get instr-side IRAM config */
1059 mfdcr r4, OCM0_DSCNTL /* get data-side IRAM config */
1060 and r3, r3, r0 /* disable data-side IRAM */
1061 and r4, r4, r0 /* disable data-side IRAM */
1062 mtdcr OCM0_ISCNTL, r3 /* set instr-side IRAM config */
1063 mtdcr OCM0_DSCNTL, r4 /* set data-side IRAM config */
1066 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1067 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
1068 mtdcr OCM0_DSARC, r3
1069 addis r4, 0, 0xC000 /* OCM data area enabled */
1070 mtdcr OCM0_DSCNTL, r4
1072 #endif /* CONFIG_405EZ */
1075 /*----------------------------------------------------------------------- */
1076 /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
1077 /*----------------------------------------------------------------------- */
1078 #ifdef CONFIG_SYS_INIT_DCACHE_CS
1080 mtdcr EBC0_CFGADDR, r4
1081 lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h
1082 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l
1083 mtdcr EBC0_CFGDATA, r4
1086 mtdcr EBC0_CFGADDR, r4
1087 lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h
1088 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l
1089 mtdcr EBC0_CFGDATA, r4
1092 * Enable the data cache for the 128MB storage access control region
1093 * at CONFIG_SYS_INIT_RAM_ADDR.
1096 oris r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1097 ori r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
1101 * Preallocate data cache lines to be used to avoid a subsequent
1102 * cache miss and an ensuing machine check exception when exceptions
1107 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1108 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1110 lis r4, CONFIG_SYS_INIT_RAM_SIZE@h
1111 ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
1114 * Convert the size, in bytes, to the number of cache lines/blocks
1117 clrlwi. r5, r4, (32 - L1_CACHE_SHIFT)
1118 srwi r5, r4, L1_CACHE_SHIFT
1124 /* Preallocate the computed number of cache blocks. */
1125 ..alloc_dcache_block:
1127 addi r3, r3, L1_CACHE_BYTES
1128 bdnz ..alloc_dcache_block
1132 * Load the initial stack pointer and data area and convert the size,
1133 * in bytes, to the number of words to initialize to a known value.
1135 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
1136 ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
1138 lis r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@h
1139 ori r4, r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@l
1142 lis r2, CONFIG_SYS_INIT_RAM_ADDR@h
1143 ori r2, r2, CONFIG_SYS_INIT_RAM_SIZE@l
1145 lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h
1146 ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l
1153 * Make room for stack frame header and clear final stack frame so
1154 * that stack backtraces terminate cleanly.
1160 * Set up a dummy frame to store reset vector as return address.
1161 * this causes stack underflow to reset board.
1163 stwu r1, -8(r1) /* Save back chain and move SP */
1164 addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
1165 ori r0, r0, RESET_VECTOR@l
1166 stwu r1, -8(r1) /* Save back chain and move SP */
1167 stw r0, +12(r1) /* Save return addr (underflow vect) */
1169 #elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \
1170 (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE))
1175 /* Set up Stack at top of OCM */
1176 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h
1177 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l
1179 /* Set up a zeroized stack frame so that backtrace works right */
1185 * Set up a dummy frame to store reset vector as return address.
1186 * this causes stack underflow to reset board.
1188 stwu r1, -8(r1) /* Save back chain and move SP */
1189 lis r0, RESET_VECTOR@h /* Address of reset vector */
1190 ori r0, r0, RESET_VECTOR@l
1191 stwu r1, -8(r1) /* Save back chain and move SP */
1192 stw r0, +12(r1) /* Save return addr (underflow vect) */
1193 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
1195 #if defined(__pic__) && __pic__ == 1
1196 /* Needed for upcoming -msingle-pic-base */
1197 bl _GLOBAL_OFFSET_TABLE_@local-4
1200 #ifdef CONFIG_NAND_SPL
1201 bl nand_boot_common /* will not return */
1203 GET_GOT /* initialize GOT access */
1205 bl cpu_init_f /* run low-level CPU init code (from Flash) */
1207 bl board_init_f /* run first part of init code (from Flash) */
1208 /* NOTREACHED - board_init_f() does not return */
1210 #endif /* CONFIG_NAND_SPL */
1212 #endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
1213 /*----------------------------------------------------------------------- */
1216 #ifndef CONFIG_NAND_SPL
1218 * This code finishes saving the registers to the exception frame
1219 * and jumps to the appropriate handler for the exception.
1220 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1222 .globl transfer_to_handler
1223 transfer_to_handler:
1233 andi. r24,r23,0x3f00 /* get vector offset */
1237 mtspr SPRG2,r22 /* r1 is now kernel sp */
1238 lwz r24,0(r23) /* virtual address of handler */
1239 lwz r23,4(r23) /* where to go when done */
1244 rfi /* jump to handler, enable MMU */
1247 mfmsr r28 /* Disable interrupts */
1251 SYNC /* Some chip revs need this... */
1266 lwz r2,_NIP(r1) /* Restore environment */
1277 mfmsr r28 /* Disable interrupts */
1281 SYNC /* Some chip revs need this... */
1296 lwz r2,_NIP(r1) /* Restore environment */
1308 mfmsr r28 /* Disable interrupts */
1312 SYNC /* Some chip revs need this... */
1327 lwz r2,_NIP(r1) /* Restore environment */
1329 mtspr SPRN_MCSRR0,r2
1330 mtspr SPRN_MCSRR1,r0
1336 #endif /* CONFIG_440 */
1344 /*------------------------------------------------------------------------------- */
1345 /* Function: out16 */
1346 /* Description: Output 16 bits */
1347 /*------------------------------------------------------------------------------- */
1353 /*------------------------------------------------------------------------------- */
1354 /* Function: out16r */
1355 /* Description: Byte reverse and output 16 bits */
1356 /*------------------------------------------------------------------------------- */
1362 /*------------------------------------------------------------------------------- */
1363 /* Function: out32r */
1364 /* Description: Byte reverse and output 32 bits */
1365 /*------------------------------------------------------------------------------- */
1371 /*------------------------------------------------------------------------------- */
1372 /* Function: in16 */
1373 /* Description: Input 16 bits */
1374 /*------------------------------------------------------------------------------- */
1380 /*------------------------------------------------------------------------------- */
1381 /* Function: in16r */
1382 /* Description: Input 16 bits and byte reverse */
1383 /*------------------------------------------------------------------------------- */
1389 /*------------------------------------------------------------------------------- */
1390 /* Function: in32r */
1391 /* Description: Input 32 bits and byte reverse */
1392 /*------------------------------------------------------------------------------- */
1399 * void relocate_code (addr_sp, gd, addr_moni)
1401 * This "function" does not return, instead it continues in RAM
1402 * after relocating the monitor code.
1404 * r3 = Relocated stack pointer
1405 * r4 = Relocated global data pointer
1406 * r5 = Relocated text pointer
1408 .globl relocate_code
1410 #if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS)
1412 * We need to flush the initial global data (gd_t) and bd_info
1413 * before the dcache will be invalidated.
1416 /* Save registers */
1422 * Flush complete dcache, this is faster than flushing the
1423 * ranges for global_data and bd_info instead.
1427 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
1429 * Undo the earlier data cache set-up for the primordial stack and
1430 * data area. First, invalidate the data cache and then disable data
1431 * cacheability for that area. Finally, restore the EBC values, if
1435 /* Invalidate the primordial stack and data area in cache */
1436 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1437 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1439 lis r4, CONFIG_SYS_INIT_RAM_SIZE@h
1440 ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
1443 bl invalidate_dcache_range
1445 /* Disable cacheability for the region */
1447 lis r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1448 ori r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
1452 /* Restore the EBC parameters */
1454 mtdcr EBC0_CFGADDR, r3
1456 ori r3, r3, PBxAP_VAL@l
1457 mtdcr EBC0_CFGDATA, r3
1460 mtdcr EBC0_CFGADDR, r3
1462 ori r3, r3, PBxCR_VAL@l
1463 mtdcr EBC0_CFGDATA, r3
1464 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
1466 /* Restore registers */
1470 #endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */
1472 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
1474 * Unlock the previously locked d-cache
1478 /* set TFLOOR/NFLOOR to 0 again */
1495 /* Invalidate data cache, now no longer our stack */
1499 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
1502 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1503 * to speed up the boot process. Now this cache needs to be disabled.
1505 #if defined(CONFIG_440)
1506 /* Clear all potential pending exceptions */
1509 addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */
1510 tlbre r0,r1,0x0002 /* Read contents */
1511 ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
1512 tlbwe r0,r1,0x0002 /* Save it out */
1515 #endif /* defined(CONFIG_440) */
1516 mr r1, r3 /* Set new stack pointer */
1517 mr r9, r4 /* Save copy of Init Data pointer */
1518 mr r10, r5 /* Save copy of Destination Address */
1521 mr r3, r5 /* Destination Address */
1522 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1523 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
1524 lwz r5, GOT(__init_end)
1526 li r6, L1_CACHE_BYTES /* Cache Line Size */
1531 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1537 /* First our own GOT */
1539 /* then the one used by the C code */
1549 beq cr1,4f /* In place copy is not necessary */
1550 beq 7f /* Protect against 0 count */
1569 * Now flush the cache: note that we must start from a cache aligned
1570 * address. Otherwise we might miss one cache line.
1574 beq 7f /* Always flush prefetch queue in any case */
1582 sync /* Wait for all dcbst to complete on bus */
1588 7: sync /* Wait for all icbi to complete on bus */
1592 * We are done. Do not return, instead branch to second part of board
1593 * initialization, now running from RAM.
1596 addi r0, r10, in_ram - _start + _START_OFFSET
1598 blr /* NEVER RETURNS! */
1603 * Relocation Function, r12 point to got2+0x8000
1605 * Adjust got2 pointers, no need to check for 0, this code
1606 * already puts a few entries in the table.
1608 li r0,__got2_entries@sectoff@l
1609 la r3,GOT(_GOT2_TABLE_)
1610 lwz r11,GOT(_GOT2_TABLE_)
1622 * Now adjust the fixups and the pointers to the fixups
1623 * in case we need to move ourselves again.
1625 li r0,__fixup_entries@sectoff@l
1626 lwz r3,GOT(_FIXUP_TABLE_)
1642 * Now clear BSS segment
1644 lwz r3,GOT(__bss_start)
1645 lwz r4,GOT(__bss_end__)
1667 mr r3, r9 /* Init Data pointer */
1668 mr r4, r10 /* Destination Address */
1672 * Copy exception vector code to low memory
1675 * r7: source address, r8: end address, r9: target address
1679 mflr r4 /* save link register */
1681 lwz r7, GOT(_start_of_vectors)
1682 lwz r8, GOT(_end_of_vectors)
1684 li r9, 0x100 /* reset vector always at 0x100 */
1687 bgelr /* return if r7>=r8 - just in case */
1697 * relocate `hdlr' and `int_return' entries
1699 li r7, .L_MachineCheck - _start + _START_OFFSET
1700 li r8, Alignment - _start + _START_OFFSET
1703 addi r7, r7, 0x100 /* next exception vector */
1707 li r7, .L_Alignment - _start + _START_OFFSET
1710 li r7, .L_ProgramCheck - _start + _START_OFFSET
1714 li r7, .L_FPUnavailable - _start + _START_OFFSET
1717 li r7, .L_Decrementer - _start + _START_OFFSET
1720 li r7, .L_APU - _start + _START_OFFSET
1723 li r7, .L_InstructionTLBError - _start + _START_OFFSET
1726 li r7, .L_DataTLBError - _start + _START_OFFSET
1728 #else /* CONFIG_440 */
1729 li r7, .L_PIT - _start + _START_OFFSET
1732 li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
1735 li r7, .L_DataTLBMiss - _start + _START_OFFSET
1737 #endif /* CONFIG_440 */
1739 li r7, .L_DebugBreakpoint - _start + _START_OFFSET
1742 #if !defined(CONFIG_440)
1743 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1744 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1745 mtmsr r7 /* change MSR */
1748 b __440_msr_continue
1751 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1752 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1760 mtlr r4 /* restore link register */
1763 #if defined(CONFIG_440)
1764 /*----------------------------------------------------------------------------+
1766 +----------------------------------------------------------------------------*/
1767 function_prolog(dcbz_area)
1768 rlwinm. r5,r4,0,27,31
1769 rlwinm r5,r4,27,5,31
1778 function_epilog(dcbz_area)
1779 #endif /* CONFIG_440 */
1780 #endif /* CONFIG_NAND_SPL */
1782 /*------------------------------------------------------------------------------- */
1784 /* Description: Input 8 bits */
1785 /*------------------------------------------------------------------------------- */
1791 /*------------------------------------------------------------------------------- */
1792 /* Function: out8 */
1793 /* Description: Output 8 bits */
1794 /*------------------------------------------------------------------------------- */
1800 /*------------------------------------------------------------------------------- */
1801 /* Function: out32 */
1802 /* Description: Output 32 bits */
1803 /*------------------------------------------------------------------------------- */
1809 /*------------------------------------------------------------------------------- */
1810 /* Function: in32 */
1811 /* Description: Input 32 bits */
1812 /*------------------------------------------------------------------------------- */
1818 /**************************************************************************/
1819 /* PPC405EP specific stuff */
1820 /**************************************************************************/
1824 #ifdef CONFIG_BUBINGA
1826 * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1827 * function) to support FPGA and NVRAM accesses below.
1830 lis r3,GPIO0_OSRH@h /* config GPIO output select */
1831 ori r3,r3,GPIO0_OSRH@l
1832 lis r4,CONFIG_SYS_GPIO0_OSRH@h
1833 ori r4,r4,CONFIG_SYS_GPIO0_OSRH@l
1836 ori r3,r3,GPIO0_OSRL@l
1837 lis r4,CONFIG_SYS_GPIO0_OSRL@h
1838 ori r4,r4,CONFIG_SYS_GPIO0_OSRL@l
1841 lis r3,GPIO0_ISR1H@h /* config GPIO input select */
1842 ori r3,r3,GPIO0_ISR1H@l
1843 lis r4,CONFIG_SYS_GPIO0_ISR1H@h
1844 ori r4,r4,CONFIG_SYS_GPIO0_ISR1H@l
1846 lis r3,GPIO0_ISR1L@h
1847 ori r3,r3,GPIO0_ISR1L@l
1848 lis r4,CONFIG_SYS_GPIO0_ISR1L@h
1849 ori r4,r4,CONFIG_SYS_GPIO0_ISR1L@l
1852 lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
1853 ori r3,r3,GPIO0_TSRH@l
1854 lis r4,CONFIG_SYS_GPIO0_TSRH@h
1855 ori r4,r4,CONFIG_SYS_GPIO0_TSRH@l
1858 ori r3,r3,GPIO0_TSRL@l
1859 lis r4,CONFIG_SYS_GPIO0_TSRL@h
1860 ori r4,r4,CONFIG_SYS_GPIO0_TSRL@l
1863 lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
1864 ori r3,r3,GPIO0_TCR@l
1865 lis r4,CONFIG_SYS_GPIO0_TCR@h
1866 ori r4,r4,CONFIG_SYS_GPIO0_TCR@l
1869 li r3,PB1AP /* program EBC bank 1 for RTC access */
1870 mtdcr EBC0_CFGADDR,r3
1871 lis r3,CONFIG_SYS_EBC_PB1AP@h
1872 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1873 mtdcr EBC0_CFGDATA,r3
1875 mtdcr EBC0_CFGADDR,r3
1876 lis r3,CONFIG_SYS_EBC_PB1CR@h
1877 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1878 mtdcr EBC0_CFGDATA,r3
1880 li r3,PB1AP /* program EBC bank 1 for RTC access */
1881 mtdcr EBC0_CFGADDR,r3
1882 lis r3,CONFIG_SYS_EBC_PB1AP@h
1883 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1884 mtdcr EBC0_CFGDATA,r3
1886 mtdcr EBC0_CFGADDR,r3
1887 lis r3,CONFIG_SYS_EBC_PB1CR@h
1888 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1889 mtdcr EBC0_CFGDATA,r3
1891 li r3,PB4AP /* program EBC bank 4 for FPGA access */
1892 mtdcr EBC0_CFGADDR,r3
1893 lis r3,CONFIG_SYS_EBC_PB4AP@h
1894 ori r3,r3,CONFIG_SYS_EBC_PB4AP@l
1895 mtdcr EBC0_CFGDATA,r3
1897 mtdcr EBC0_CFGADDR,r3
1898 lis r3,CONFIG_SYS_EBC_PB4CR@h
1899 ori r3,r3,CONFIG_SYS_EBC_PB4CR@l
1900 mtdcr EBC0_CFGDATA,r3
1904 !-----------------------------------------------------------------------
1905 ! Check to see if chip is in bypass mode.
1906 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1907 ! CPU reset Otherwise, skip this step and keep going.
1908 ! Note: Running BIOS in bypass mode is not supported since PLB speed
1909 ! will not be fast enough for the SDRAM (min 66MHz)
1910 !-----------------------------------------------------------------------
1912 mfdcr r5, CPC0_PLLMR1
1913 rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
1916 beq pll_done /* if SSCS =b'1' then PLL has */
1917 /* already been set */
1918 /* and CPU has been reset */
1919 /* so skip to next section */
1921 #ifdef CONFIG_BUBINGA
1923 !-----------------------------------------------------------------------
1924 ! Read NVRAM to get value to write in PLLMR.
1925 ! If value has not been correctly saved, write default value
1926 ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1927 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1929 ! WARNING: This code assumes the first three words in the nvram_t
1930 ! structure in openbios.h. Changing the beginning of
1931 ! the structure will break this code.
1933 !-----------------------------------------------------------------------
1935 addis r3,0,NVRAM_BASE@h
1936 addi r3,r3,NVRAM_BASE@l
1939 addis r5,0,NVRVFY1@h
1940 addi r5,r5,NVRVFY1@l
1941 cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
1945 addis r5,0,NVRVFY2@h
1946 addi r5,r5,NVRVFY2@l
1947 cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
1949 addi r3,r3,8 /* Skip over conf_size */
1950 lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
1951 lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
1952 rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
1953 cmpi cr0,0,r5,1 /* See if PLL is locked */
1956 #endif /* CONFIG_BUBINGA */
1960 andi. r5, r4, CPC0_BOOT_SEP@l
1961 bne strap_1 /* serial eeprom present */
1962 addis r5,0,CPLD_REG0_ADDR@h
1963 ori r5,r5,CPLD_REG0_ADDR@l
1966 #endif /* CONFIG_TAIHU */
1968 #if defined(CONFIG_ZEUS)
1970 andi. r5, r4, CPC0_BOOT_SEP@l
1971 bne strap_1 /* serial eeprom present */
1978 mfdcr r3, CPC0_PLLMR0
1979 mfdcr r4, CPC0_PLLMR1
1983 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1984 ori r3,r3,PLLMR0_DEFAULT@l /* */
1985 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1986 ori r4,r4,PLLMR1_DEFAULT@l /* */
1991 addis r3,0,PLLMR0_DEFAULT_PCI66@h
1992 ori r3,r3,PLLMR0_DEFAULT_PCI66@l
1993 addis r4,0,PLLMR1_DEFAULT_PCI66@h
1994 ori r4,r4,PLLMR1_DEFAULT_PCI66@l
1997 mfdcr r3, CPC0_PLLMR0
1998 mfdcr r4, CPC0_PLLMR1
1999 #endif /* CONFIG_TAIHU */
2002 b pll_write /* Write the CPC0_PLLMR with new value */
2006 !-----------------------------------------------------------------------
2007 ! Clear Soft Reset Register
2008 ! This is needed to enable PCI if not booting from serial EPROM
2009 !-----------------------------------------------------------------------
2019 blr /* return to main code */
2022 !-----------------------------------------------------------------------------
2023 ! Function: pll_write
2024 ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
2026 ! 1. Pll is first disabled (de-activated by putting in bypass mode)
2028 ! 3. Clock dividers are set while PLL is held in reset and bypassed
2029 ! 4. PLL Reset is cleared
2030 ! 5. Wait 100us for PLL to lock
2031 ! 6. A core reset is performed
2032 ! Input: r3 = Value to write to CPC0_PLLMR0
2033 ! Input: r4 = Value to write to CPC0_PLLMR1
2035 !-----------------------------------------------------------------------------
2041 ori r5,r5,0x0101 /* Stop the UART clocks */
2042 mtdcr CPC0_UCR,r5 /* Before changing PLL */
2044 mfdcr r5, CPC0_PLLMR1
2045 rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
2046 mtdcr CPC0_PLLMR1,r5
2047 oris r5,r5,0x4000 /* Set PLL Reset */
2048 mtdcr CPC0_PLLMR1,r5
2050 mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
2051 rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
2052 oris r5,r5,0x4000 /* Set PLL Reset */
2053 mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
2054 rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
2055 mtdcr CPC0_PLLMR1,r5
2058 ! Wait min of 100us for PLL to lock.
2059 ! See CMOS 27E databook for more info.
2060 ! At 200MHz, that means waiting 20,000 instructions
2062 addi r3,0,20000 /* 2000 = 0x4e20 */
2067 oris r5,r5,0x8000 /* Enable PLL */
2068 mtdcr CPC0_PLLMR1,r5 /* Engage */
2071 * Reset CPU to guarantee timings are OK
2072 * Not sure if this is needed...
2075 mtspr SPRN_DBCR0,r3 /* This will cause a CPU core reset, and */
2076 /* execution will continue from the poweron */
2077 /* vector of 0xfffffffc */
2078 #endif /* CONFIG_405EP */
2080 #if defined(CONFIG_440)
2081 /*----------------------------------------------------------------------------+
2083 +----------------------------------------------------------------------------*/
2084 function_prolog(mttlb3)
2087 function_epilog(mttlb3)
2089 /*----------------------------------------------------------------------------+
2091 +----------------------------------------------------------------------------*/
2092 function_prolog(mftlb3)
2095 function_epilog(mftlb3)
2097 /*----------------------------------------------------------------------------+
2099 +----------------------------------------------------------------------------*/
2100 function_prolog(mttlb2)
2103 function_epilog(mttlb2)
2105 /*----------------------------------------------------------------------------+
2107 +----------------------------------------------------------------------------*/
2108 function_prolog(mftlb2)
2111 function_epilog(mftlb2)
2113 /*----------------------------------------------------------------------------+
2115 +----------------------------------------------------------------------------*/
2116 function_prolog(mttlb1)
2119 function_epilog(mttlb1)
2121 /*----------------------------------------------------------------------------+
2123 +----------------------------------------------------------------------------*/
2124 function_prolog(mftlb1)
2127 function_epilog(mftlb1)
2128 #endif /* CONFIG_440 */
2130 #if defined(CONFIG_NAND_SPL)
2132 * void nand_boot_relocate(dst, src, bytes)
2134 * r3 = Destination address to copy code to (in SDRAM)
2135 * r4 = Source address to copy code from
2136 * r5 = size to copy in bytes
2144 * Copy SPL from icache into SDRAM
2156 * Calculate "corrected" link register, so that we "continue"
2157 * in execution in destination range
2159 sub r3,r7,r6 /* r3 = src - dst */
2160 sub r8,r8,r3 /* r8 = link-reg - (src - dst) */
2166 * First initialize SDRAM. It has to be available *before* calling
2169 lis r3,CONFIG_SYS_SDRAM_BASE@h
2170 ori r3,r3,CONFIG_SYS_SDRAM_BASE@l
2174 * Now copy the 4k SPL code into SDRAM and continue execution
2177 lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h
2178 ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l
2179 lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h
2180 ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l
2181 lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h
2182 ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l
2183 bl nand_boot_relocate
2186 * We're running from SDRAM now!!!
2188 * It is necessary for 4xx systems to relocate from running at
2189 * the original location (0xfffffxxx) to somewhere else (SDRAM
2190 * preferably). This is because CS0 needs to be reconfigured for
2191 * NAND access. And we can't reconfigure this CS when currently
2192 * "running" from it.
2196 * Finally call nand_boot() to load main NAND U-Boot image from
2197 * NAND and jump to it.
2199 bl nand_boot /* will not return */
2200 #endif /* CONFIG_NAND_SPL */