arch/powerpc: Simplify some calculations using ARRAY_SIZE() macro.
[platform/kernel/u-boot.git] / arch / powerpc / cpu / ppc4xx / reginfo.c
1 /*
2  *(C) Copyright 2005-2009 Netstal Maschinen AG
3  *    Bruno Hars (Bruno.Hars@netstal.com)
4  *    Niklaus Giger (Niklaus.Giger@netstal.com)
5  *
6  * SPDX-License-Identifier:     GPL-2.0+
7  */
8
9 /*
10  * reginfo.c - register dump of HW-configuratin register for PPC4xx based board
11  */
12
13 #include <common.h>
14 #include <command.h>
15 #include <asm/processor.h>
16 #include <asm/io.h>
17 #include <asm/ppc4xx-uic.h>
18 #include <asm/ppc4xx-emac.h>
19
20 enum REGISTER_TYPE {
21         IDCR1,  /* Indirectly Accessed DCR via SDRAM0_CFGADDR/SDRAM0_CFGDATA */
22         IDCR2,  /* Indirectly Accessed DCR via EBC0_CFGADDR/EBC0_CFGDATA */
23         IDCR3,  /* Indirectly Accessed DCR via EBM0_CFGADDR/EBM0_CFGDATA */
24         IDCR4,  /* Indirectly Accessed DCR via PPM0_CFGADDR/PPM0_CFGDATA */
25         IDCR5,  /* Indirectly Accessed DCR via CPR0_CFGADDR/CPR0_CFGDATA */
26         IDCR6,  /* Indirectly Accessed DCR via SDR0_CFGADDR/SDR0_CFGDATA */
27         MM      /* Directly Accessed MMIO Register */
28 };
29
30 struct cpu_register {
31         char *name;
32         enum REGISTER_TYPE type;
33         u32 address;
34 };
35
36 /*
37  * PPC440EPx registers ordered for output
38  * name           type    addr            size
39  * -------------------------------------------
40  */
41
42 const struct cpu_register ppc4xx_reg[] = {
43         {"PB0CR",               IDCR2,  PB0CR},
44         {"PB0AP",               IDCR2,  PB0AP},
45         {"PB1CR",               IDCR2,  PB1CR},
46         {"PB1AP",               IDCR2,  PB1AP},
47         {"PB2CR",               IDCR2,  PB2CR},
48         {"PB2AP",               IDCR2,  PB2AP},
49         {"PB3CR",               IDCR2,  PB3CR},
50         {"PB3AP",               IDCR2,  PB3AP},
51
52         {"PB4CR",               IDCR2,  PB4CR},
53         {"PB4AP",               IDCR2,  PB4AP},
54 #if !defined(CONFIG_405EP)
55         {"PB5CR",               IDCR2,  PB5CR},
56         {"PB5AP",               IDCR2,  PB5AP},
57         {"PB6CR",               IDCR2,  PB6CR},
58         {"PB6AP",               IDCR2,  PB6AP},
59         {"PB7CR",               IDCR2,  PB7CR},
60         {"PB7AP",               IDCR2,  PB7AP},
61 #endif
62
63         {"PBEAR",               IDCR2,  PBEAR},
64 #if defined(CONFIG_405EP) || defined (CONFIG_405GP)
65         {"PBESR0",              IDCR2,  PBESR0},
66         {"PBESR1",              IDCR2,  PBESR1},
67 #endif
68         {"EBC0_CFG",            IDCR2,  EBC0_CFG},
69
70 #ifdef CONFIG_405GP
71         {"SDRAM0_BESR0",        IDCR1,  SDRAM0_BESR0},
72         {"SDRAM0_BESRS0",       IDCR1,  SDRAM0_BESRS0},
73         {"SDRAM0_BESR1",        IDCR1,  SDRAM0_BESR1},
74         {"SDRAM0_BESRS1",       IDCR1,  SDRAM0_BESRS1},
75         {"SDRAM0_BEAR",         IDCR1,  SDRAM0_BEAR},
76         {"SDRAM0_CFG",          IDCR1,  SDRAM0_CFG},
77         {"SDRAM0_RTR",          IDCR1,  SDRAM0_RTR},
78         {"SDRAM0_PMIT",         IDCR1,  SDRAM0_PMIT},
79
80         {"SDRAM0_B0CR",         IDCR1,  SDRAM0_B0CR},
81         {"SDRAM0_B1CR",         IDCR1,  SDRAM0_B1CR},
82         {"SDRAM0_B2CR",         IDCR1,  SDRAM0_B2CR},
83         {"SDRAM0_B3CR",         IDCR1,  SDRAM0_B1CR},
84         {"SDRAM0_TR",           IDCR1,  SDRAM0_TR},
85         {"SDRAM0_ECCCFG",       IDCR1,  SDRAM0_B1CR},
86         {"SDRAM0_ECCESR",       IDCR1,  SDRAM0_ECCESR},
87
88
89 #endif
90
91 #ifdef CONFIG_440EPX
92         {"SDR0_SDSTP0",         IDCR6,  SDR0_SDSTP0},
93         {"SDR0_SDSTP1",         IDCR6,  SDR0_SDSTP1},
94         {"SDR0_SDSTP2",         IDCR6,  SDR0_SDSTP2},
95         {"SDR0_SDSTP3",         IDCR6,  SDR0_SDSTP3},
96         {"SDR0_CUST0",          IDCR6,  SDR0_CUST0},
97         {"SDR0_CUST1",          IDCR6,  SDR0_CUST1},
98         {"SDR0_EBC",            IDCR6,  SDR0_EBC},
99         {"SDR0_AMP0",           IDCR6,  SDR0_AMP0},
100         {"SDR0_AMP1",           IDCR6,  SDR0_AMP1},
101         {"SDR0_CP440",          IDCR6,  SDR0_CP440},
102         {"SDR0_CRYP0",          IDCR6,  SDR0_CRYP0},
103         {"SDR0_DDRCFG",         IDCR6,  SDR0_DDRCFG},
104         {"SDR0_EMAC0RXST",      IDCR6,  SDR0_EMAC0RXST},
105         {"SDR0_EMAC0TXST",      IDCR6,  SDR0_EMAC0TXST},
106         {"SDR0_MFR",            IDCR6,  SDR0_MFR},
107         {"SDR0_PCI0",           IDCR6,  SDR0_PCI0},
108         {"SDR0_PFC0",           IDCR6,  SDR0_PFC0},
109         {"SDR0_PFC1",           IDCR6,  SDR0_PFC1},
110         {"SDR0_PFC2",           IDCR6,  SDR0_PFC2},
111         {"SDR0_PFC4",           IDCR6,  SDR0_PFC4},
112         {"SDR0_UART0",          IDCR6,  SDR0_UART0},
113         {"SDR0_UART1",          IDCR6,  SDR0_UART1},
114         {"SDR0_UART2",          IDCR6,  SDR0_UART2},
115         {"SDR0_UART3",          IDCR6,  SDR0_UART3},
116         {"DDR0_02",             IDCR1,  DDR0_02},
117         {"DDR0_00",             IDCR1,  DDR0_00},
118         {"DDR0_01",             IDCR1,  DDR0_01},
119         {"DDR0_03",             IDCR1,  DDR0_03},
120         {"DDR0_04",             IDCR1,  DDR0_04},
121         {"DDR0_05",             IDCR1,  DDR0_05},
122         {"DDR0_06",             IDCR1,  DDR0_06},
123         {"DDR0_07",             IDCR1,  DDR0_07},
124         {"DDR0_08",             IDCR1,  DDR0_08},
125         {"DDR0_09",             IDCR1,  DDR0_09},
126         {"DDR0_10",             IDCR1,  DDR0_10},
127         {"DDR0_11",             IDCR1,  DDR0_11},
128         {"DDR0_12",             IDCR1,  DDR0_12},
129         {"DDR0_14",             IDCR1,  DDR0_14},
130         {"DDR0_17",             IDCR1,  DDR0_17},
131         {"DDR0_18",             IDCR1,  DDR0_18},
132         {"DDR0_19",             IDCR1,  DDR0_19},
133         {"DDR0_20",             IDCR1,  DDR0_20},
134         {"DDR0_21",             IDCR1,  DDR0_21},
135         {"DDR0_22",             IDCR1,  DDR0_22},
136         {"DDR0_23",             IDCR1,  DDR0_23},
137         {"DDR0_24",             IDCR1,  DDR0_24},
138         {"DDR0_25",             IDCR1,  DDR0_25},
139         {"DDR0_26",             IDCR1,  DDR0_26},
140         {"DDR0_27",             IDCR1,  DDR0_27},
141         {"DDR0_28",             IDCR1,  DDR0_28},
142         {"DDR0_31",             IDCR1,  DDR0_31},
143         {"DDR0_32",             IDCR1,  DDR0_32},
144         {"DDR0_33",             IDCR1,  DDR0_33},
145         {"DDR0_34",             IDCR1,  DDR0_34},
146         {"DDR0_35",             IDCR1,  DDR0_35},
147         {"DDR0_36",             IDCR1,  DDR0_36},
148         {"DDR0_37",             IDCR1,  DDR0_37},
149         {"DDR0_38",             IDCR1,  DDR0_38},
150         {"DDR0_39",             IDCR1,  DDR0_39},
151         {"DDR0_40",             IDCR1,  DDR0_40},
152         {"DDR0_41",             IDCR1,  DDR0_41},
153         {"DDR0_42",             IDCR1,  DDR0_42},
154         {"DDR0_43",             IDCR1,  DDR0_43},
155         {"DDR0_44",             IDCR1,  DDR0_44},
156         {"CPR0_ICFG",           IDCR5,  CPR0_ICFG},
157         {"CPR0_MALD",           IDCR5,  CPR0_MALD},
158         {"CPR0_OPBD00",         IDCR5,  CPR0_OPBD0},
159         {"CPR0_PERD0",          IDCR5,  CPR0_PERD},
160         {"CPR0_PLLC0",          IDCR5,  CPR0_PLLC},
161         {"CPR0_PLLD0",          IDCR5,  CPR0_PLLD},
162         {"CPR0_PRIMAD0",        IDCR5,  CPR0_PRIMAD0},
163         {"CPR0_PRIMBD0",        IDCR5,  CPR0_PRIMBD0},
164         {"CPR0_SPCID",          IDCR5,  CPR0_SPCID},
165         {"SPI0_MODE",           MM,     SPI0_MODE},
166         {"IIC0_CLKDIV",         MM,     PCIL0_PMM1MA},
167         {"PCIL0_PMM0MA",        MM,     PCIL0_PMM0MA},
168         {"PCIL0_PMM1MA",        MM,     PCIL0_PMM1MA},
169         {"PCIL0_PTM1LA",        MM,     PCIL0_PMM1MA},
170         {"PCIL0_PTM1MS",        MM,     PCIL0_PTM1MS},
171         {"PCIL0_PTM2LA",        MM,     PCIL0_PMM1MA},
172         {"PCIL0_PTM2MS",        MM,     PCIL0_PTM2MS},
173         {"ZMII0_FER",           MM,     ZMII0_FER},
174         {"ZMII0_SSR",           MM,     ZMII0_SSR},
175         {"EMAC0_IPGVR",         MM,     EMAC0_IPGVR},
176         {"EMAC0_MR1",           MM,     EMAC0_MR1},
177         {"EMAC0_PTR",           MM,     EMAC0_PTR},
178         {"EMAC0_RWMR",          MM,     EMAC0_RWMR},
179         {"EMAC0_STACR",         MM,     EMAC0_STACR},
180         {"EMAC0_TMR0",          MM,     EMAC0_TMR0},
181         {"EMAC0_TMR1",          MM,     EMAC0_TMR1},
182         {"EMAC0_TRTR",          MM,     EMAC0_TRTR},
183         {"EMAC1_MR1",           MM,     EMAC1_MR1},
184         {"GPIO0_OR",            MM,     GPIO0_OR},
185         {"GPIO1_OR",            MM,     GPIO1_OR},
186         {"GPIO0_TCR",           MM,     GPIO0_TCR},
187         {"GPIO1_TCR",           MM,     GPIO1_TCR},
188         {"GPIO0_ODR",           MM,     GPIO0_ODR},
189         {"GPIO1_ODR",           MM,     GPIO1_ODR},
190         {"GPIO0_OSRL",          MM,     GPIO0_OSRL},
191         {"GPIO0_OSRH",          MM,     GPIO0_OSRH},
192         {"GPIO1_OSRL",          MM,     GPIO1_OSRL},
193         {"GPIO1_OSRH",          MM,     GPIO1_OSRH},
194         {"GPIO0_TSRL",          MM,     GPIO0_TSRL},
195         {"GPIO0_TSRH",          MM,     GPIO0_TSRH},
196         {"GPIO1_TSRL",          MM,     GPIO1_TSRL},
197         {"GPIO1_TSRH",          MM,     GPIO1_TSRH},
198         {"GPIO0_IR",            MM,     GPIO0_IR},
199         {"GPIO1_IR",            MM,     GPIO1_IR},
200         {"GPIO0_ISR1L",         MM,     GPIO0_ISR1L},
201         {"GPIO0_ISR1H",         MM,     GPIO0_ISR1H},
202         {"GPIO1_ISR1L",         MM,     GPIO1_ISR1L},
203         {"GPIO1_ISR1H",         MM,     GPIO1_ISR1H},
204         {"GPIO0_ISR2L",         MM,     GPIO0_ISR2L},
205         {"GPIO0_ISR2H",         MM,     GPIO0_ISR2H},
206         {"GPIO1_ISR2L",         MM,     GPIO1_ISR2L},
207         {"GPIO1_ISR2H",         MM,     GPIO1_ISR2H},
208         {"GPIO0_ISR3L",         MM,     GPIO0_ISR3L},
209         {"GPIO0_ISR3H",         MM,     GPIO0_ISR3H},
210         {"GPIO1_ISR3L",         MM,     GPIO1_ISR3L},
211         {"GPIO1_ISR3H",         MM,     GPIO1_ISR3H},
212         {"SDR0_USB2PHY0CR",     IDCR6,  SDR0_USB2PHY0CR},
213         {"SDR0_USB2H0CR",       IDCR6,  SDR0_USB2H0CR},
214         {"SDR0_USB2D0CR",       IDCR6,  SDR0_USB2D0CR},
215 #endif
216 };
217
218 /*
219  * CPU Register dump of PPC4xx HW configuration registers
220  * Output: first all DCR-registers, then in order of struct ppc4xx_reg
221  */
222 #define PRINT_DCR(dcr)  printf("0x%08x %-16s: 0x%08x\n", dcr,#dcr, mfdcr(dcr));
223
224 void ppc4xx_reginfo(void)
225 {
226         unsigned int i;
227         unsigned int n;
228         u32 value;
229         enum REGISTER_TYPE type;
230 #if defined (CONFIG_405EP)
231         printf("Dump PPC405EP HW configuration registers\n\n");
232 #elif CONFIG_405GP
233         printf ("Dump 405GP HW configuration registers\n\n");
234 #elif CONFIG_440EPX
235         printf("Dump PPC440EPx HW configuration registers\n\n");
236 #endif
237         printf("MSR: 0x%08x\n", mfmsr());
238
239         printf ("\nUniversal Interrupt Controller Regs\n");
240         PRINT_DCR(UIC0SR);
241         PRINT_DCR(UIC0ER);
242         PRINT_DCR(UIC0CR);
243         PRINT_DCR(UIC0PR);
244         PRINT_DCR(UIC0TR);
245         PRINT_DCR(UIC0MSR);
246         PRINT_DCR(UIC0VR);
247         PRINT_DCR(UIC0VCR);
248
249 #if (UIC_MAX > 1)
250         PRINT_DCR(UIC2SR);
251         PRINT_DCR(UIC2ER);
252         PRINT_DCR(UIC2CR);
253         PRINT_DCR(UIC2PR);
254         PRINT_DCR(UIC2TR);
255         PRINT_DCR(UIC2MSR);
256         PRINT_DCR(UIC2VR);
257         PRINT_DCR(UIC2VCR);
258 #endif
259
260 #if (UIC_MAX > 2)
261         PRINT_DCR(UIC2SR);
262         PRINT_DCR(UIC2ER);
263         PRINT_DCR(UIC2CR);
264         PRINT_DCR(UIC2PR);
265         PRINT_DCR(UIC2TR);
266         PRINT_DCR(UIC2MSR);
267         PRINT_DCR(UIC2VR);
268         PRINT_DCR(UIC2VCR);
269 #endif
270
271 #if (UIC_MAX > 3)
272         PRINT_DCR(UIC3SR);
273         PRINT_DCR(UIC3ER);
274         PRINT_DCR(UIC3CR);
275         PRINT_DCR(UIC3PR);
276         PRINT_DCR(UIC3TR);
277         PRINT_DCR(UIC3MSR);
278         PRINT_DCR(UIC3VR);
279         PRINT_DCR(UIC3VCR);
280 #endif
281
282 #if defined (CONFIG_405EP) || defined (CONFIG_405GP)
283         printf ("\n\nDMA Channels\n");
284         PRINT_DCR(DMASR);
285         PRINT_DCR(DMASGC);
286         PRINT_DCR(DMAADR);
287
288         PRINT_DCR(DMACR0);
289         PRINT_DCR(DMACT0);
290         PRINT_DCR(DMADA0);
291         PRINT_DCR(DMASA0);
292         PRINT_DCR(DMASB0);
293
294         PRINT_DCR(DMACR1);
295         PRINT_DCR(DMACT1);
296         PRINT_DCR(DMADA1);
297         PRINT_DCR(DMASA1);
298         PRINT_DCR(DMASB1);
299
300         PRINT_DCR(DMACR2);
301         PRINT_DCR(DMACT2);
302         PRINT_DCR(DMADA2);
303         PRINT_DCR(DMASA2);
304         PRINT_DCR(DMASB2);
305
306         PRINT_DCR(DMACR3);
307         PRINT_DCR(DMACT3);
308         PRINT_DCR(DMADA3);
309         PRINT_DCR(DMASA3);
310         PRINT_DCR(DMASB3);
311 #endif
312
313         printf ("\n\nVarious HW-Configuration registers\n");
314 #if defined (CONFIG_440EPX)
315         PRINT_DCR(MAL0_CFG);
316         PRINT_DCR(CPM0_ER);
317         PRINT_DCR(CPM1_ER);
318         PRINT_DCR(PLB4A0_ACR);
319         PRINT_DCR(PLB4A1_ACR);
320         PRINT_DCR(PLB3A0_ACR);
321         PRINT_DCR(OPB2PLB40_BCTRL);
322         PRINT_DCR(P4P3BO0_CFG);
323 #endif
324         n = ARRAY_SIZE(ppc4xx_reg);
325         for (i = 0; i < n; i++) {
326                 value = 0;
327                 type = ppc4xx_reg[i].type;
328                 switch (type) {
329                 case IDCR1:     /* Indirect via SDRAM0_CFGADDR/DDR0_CFGDATA */
330                         mtdcr(SDRAM0_CFGADDR, ppc4xx_reg[i].address);
331                         value = mfdcr(SDRAM0_CFGDATA);
332                         break;
333                 case IDCR2:     /* Indirect via EBC0_CFGADDR/EBC0_CFGDATA */
334                         mtdcr(EBC0_CFGADDR, ppc4xx_reg[i].address);
335                         value = mfdcr(EBC0_CFGDATA);
336                         break;
337                 case IDCR5:     /* Indirect via CPR0_CFGADDR/CPR0_CFGDATA */
338                         mtdcr(CPR0_CFGADDR, ppc4xx_reg[i].address);
339                         value = mfdcr(CPR0_CFGDATA);
340                         break;
341                 case IDCR6:     /* Indirect via SDR0_CFGADDR/SDR0_CFGDATA */
342                         mtdcr(SDR0_CFGADDR, ppc4xx_reg[i].address);
343                         value = mfdcr(SDR0_CFGDATA);
344                         break;
345                 case MM:        /* Directly Accessed MMIO Register */
346                         value = in_be32((const volatile unsigned __iomem *)
347                                 ppc4xx_reg[i].address);
348                         break;
349                 default:
350                         printf("\nERROR: struct entry %d: unknown register"
351                                 "type\n", i);
352                         break;
353                 }
354                 printf("0x%08x %-16s: 0x%08x\n",ppc4xx_reg[i].address,
355                         ppc4xx_reg[i].name, value);
356         }
357 }