2 * (C) Copyright 2007-2008
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/cache.h>
12 #include <asm/ppc4xx.h>
14 #ifdef CONFIG_OF_BOARD_SETUP
16 #include <fdt_support.h>
17 #include <asm/4xx_pcie.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 int __ft_board_setup(void *blob, bd_t *bd)
26 u32 ranges[EBC_NUM_BANKS * 4];
28 char ebc_path[] = "/plb/opb/ebc";
30 ft_cpu_setup(blob, bd);
33 * Read 4xx EBC bus bridge registers to get mappings of the
34 * peripheral banks into the OPB/PLB address space
36 for (i = 0; i < EBC_NUM_BANKS; i++) {
37 mtdcr(EBC0_CFGADDR, EBC_BXCR(i));
38 bxcr = mfdcr(EBC0_CFGDATA);
40 if ((bxcr & EBC_BXCR_BU_MASK) != EBC_BXCR_BU_NONE) {
43 *p++ = bxcr & EBC_BXCR_BAS_MASK;
44 *p++ = EBC_BXCR_BANK_SIZE(bxcr);
49 #ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
50 /* Update reg property in all nor flash nodes too */
51 fdt_fixup_nor_flash_size(blob);
54 /* Some 405 PPC's have EBC as direct PLB child in the dts */
55 if (fdt_path_offset(blob, ebc_path) < 0)
56 strcpy(ebc_path, "/plb/ebc");
57 rc = fdt_find_and_setprop(blob, ebc_path, "ranges", ranges,
58 (p - ranges) * sizeof(u32), 1);
60 printf("Unable to update property EBC mappings, err=%s\n",
66 int ft_board_setup(void *blob, bd_t *bd)
67 __attribute__((weak, alias("__ft_board_setup")));
70 * Fixup all PCIe nodes by setting the device_type property
71 * to "pci-endpoint" instead is "pci" for endpoint ports.
72 * This property will get checked later by the Linux driver
73 * to properly configure the PCIe port in Linux (again).
75 void fdt_pcie_setup(void *blob)
77 const char *compat = "ibm,plb-pciex";
78 const char *prop = "device_type";
79 const char *prop_val = "pci-endpoint";
84 /* Search first PCIe node */
85 no = fdt_node_offset_by_compatible(blob, -1, compat);
86 while (no != -FDT_ERR_NOTFOUND) {
87 port = fdt_getprop(blob, no, "port", NULL);
89 printf("WARNING: could not find port property\n");
91 if (is_end_point(*port)) {
92 rc = fdt_setprop(blob, no, prop, prop_val,
93 strlen(prop_val) + 1);
95 printf("WARNING: could not set %s for %s: %s.\n",
96 prop, compat, fdt_strerror(rc));
100 /* Jump to next PCIe node */
101 no = fdt_node_offset_by_compatible(blob, no, compat);
105 void ft_cpu_setup(void *blob, bd_t *bd)
110 get_sys_info(&sys_info);
112 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "timebase-frequency",
114 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "clock-frequency",
116 do_fixup_by_path_u32(blob, "/plb", "clock-frequency", sys_info.freqPLB, 1);
117 do_fixup_by_path_u32(blob, "/plb/opb", "clock-frequency", sys_info.freqOPB, 1);
119 if (fdt_path_offset(blob, "/plb/opb/ebc") >= 0)
120 do_fixup_by_path_u32(blob, "/plb/opb/ebc", "clock-frequency",
121 sys_info.freqEBC, 1);
123 do_fixup_by_path_u32(blob, "/plb/ebc", "clock-frequency",
124 sys_info.freqEBC, 1);
126 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
129 * Fixup all UART clocks for CPU internal UARTs
130 * (only these UARTs are definitely clocked by gd->arch.uart_clk)
132 * These UARTs are direct childs of /plb/opb. This code
133 * does not touch any UARTs that are connected to the ebc.
135 off = fdt_path_offset(blob, "/plb/opb");
136 while ((off = fdt_next_node(blob, off, &ndepth)) >= 0) {
138 * process all sub nodes and stop when we are back
139 * at the starting depth
144 /* only update direct childs */
146 (fdt_node_check_compatible(blob, off, "ns16550") == 0))
147 fdt_setprop(blob, off,
149 (void *)&gd->arch.uart_clk, 4);
153 * Fixup all ethernet nodes
154 * Note: aliases in the dts are required for this
156 fdt_fixup_ethernet(blob);
159 * Fixup all available PCIe nodes by setting the device_type property
161 fdt_pcie_setup(blob);
163 #endif /* CONFIG_OF_BOARD_SETUP */