arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c

   1 /*
   2  * arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c
   3  * This SPD SDRAM detection code supports AMCC PPC44x CPUs with a Denali-core
   4  * DDR2 controller, specifically the 440EPx/GRx.
   5  *
   6  * (C) Copyright 2007-2008
   7  * Larry Johnson, lrj@acm.org.
   8  *
   9  * Based primarily on arch/powerpc/cpu/ppc4xx/4xx_spd_ddr2.c, which is...
  10  *
  11  * (C) Copyright 2007
  12  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  13  *
  14  * COPYRIGHT   AMCC   CORPORATION 2004
  15  *
  16  * See file CREDITS for list of people who contributed to this
  17  * project.
  18  *
  19  * This program is free software; you can redistribute it and/or
  20  * modify it under the terms of the GNU General Public License as
  21  * published by the Free Software Foundation; either version 2 of
  22  * the License, or (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, write to the Free Software
  31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  32  * MA 02111-1307 USA
  33  *
  34  */
  35
  36 /* define DEBUG for debugging output (obviously ;-)) */
  37 #if 0
  38 #define DEBUG
  39 #endif
  40
  41 #include <common.h>
  42 #include <command.h>
  43 #include <asm/ppc4xx.h>
  44 #include <i2c.h>
  45 #include <asm/io.h>
  46 #include <asm/processor.h>
  47 #include <asm/mmu.h>
  48 #include <asm/cache.h>
  49
  50 #if defined(CONFIG_SPD_EEPROM) &&                               \
  51         (defined(CONFIG_440EPX) || defined(CONFIG_440GRX))
  52
  53 /*-----------------------------------------------------------------------------+
  54  * Defines
  55  *-----------------------------------------------------------------------------*/
  56 #ifndef TRUE
  57 #define TRUE            1
  58 #endif
  59 #ifndef FALSE
  60 #define FALSE           0
  61 #endif
  62
  63 #define MAXDIMMS        2
  64 #define MAXRANKS        2
  65
  66 #define ONE_BILLION     1000000000
  67
  68 #define MULDIV64(m1, m2, d)     (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
  69
  70 #define DLL_DQS_DELAY   0x19
  71 #define DLL_DQS_BYPASS  0x0B
  72 #define DQS_OUT_SHIFT   0x7F
  73
  74 /*
  75  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
  76  * region. Right now the cache should still be disabled in U-Boot because of the
  77  * EMAC driver, that need it's buffer descriptor to be located in non cached
  78  * memory.
  79  *
  80  * If at some time this restriction doesn't apply anymore, just define
  81  * CONFIG_4xx_DCACHE in the board config file and this code should setup
  82  * everything correctly.
  83  */
  84 #if defined(CONFIG_4xx_DCACHE)
  85 #define MY_TLB_WORD2_I_ENABLE   0                       /* enable caching on SDRAM */
  86 #else
  87 #define MY_TLB_WORD2_I_ENABLE   TLB_WORD2_I_ENABLE      /* disable caching on SDRAM */
  88 #endif
  89
  90 /*-----------------------------------------------------------------------------+
  91  * Prototypes
  92  *-----------------------------------------------------------------------------*/
  93 extern int denali_wait_for_dlllock(void);
  94 extern void denali_core_search_data_eye(void);
  95 extern void dcbz_area(u32 start_address, u32 num_bytes);
  96
  97 /*
  98  * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
  99  */
 100 void __spd_ddr_init_hang(void)
 101 {
 102         hang();
 103 }
 104 void spd_ddr_init_hang(void)
 105     __attribute__ ((weak, alias("__spd_ddr_init_hang")));
 106
 107 #if defined(DEBUG)
 108 static void print_mcsr(void)
 109 {
 110         printf("MCSR = 0x%08X\n", mfspr(SPRN_MCSR));
 111 }
 112
 113 static void denali_sdram_register_dump(void)
 114 {
 115         unsigned int sdram_data;
 116
 117         printf("\n  Register Dump:\n");
 118         mfsdram(DDR0_00, sdram_data);
 119         printf("        DDR0_00 = 0x%08X", sdram_data);
 120         mfsdram(DDR0_01, sdram_data);
 121         printf("        DDR0_01 = 0x%08X\n", sdram_data);
 122         mfsdram(DDR0_02, sdram_data);
 123         printf("        DDR0_02 = 0x%08X", sdram_data);
 124         mfsdram(DDR0_03, sdram_data);
 125         printf("        DDR0_03 = 0x%08X\n", sdram_data);
 126         mfsdram(DDR0_04, sdram_data);
 127         printf("        DDR0_04 = 0x%08X", sdram_data);
 128         mfsdram(DDR0_05, sdram_data);
 129         printf("        DDR0_05 = 0x%08X\n", sdram_data);
 130         mfsdram(DDR0_06, sdram_data);
 131         printf("        DDR0_06 = 0x%08X", sdram_data);
 132         mfsdram(DDR0_07, sdram_data);
 133         printf("        DDR0_07 = 0x%08X\n", sdram_data);
 134         mfsdram(DDR0_08, sdram_data);
 135         printf("        DDR0_08 = 0x%08X", sdram_data);
 136         mfsdram(DDR0_09, sdram_data);
 137         printf("        DDR0_09 = 0x%08X\n", sdram_data);
 138         mfsdram(DDR0_10, sdram_data);
 139         printf("        DDR0_10 = 0x%08X", sdram_data);
 140         mfsdram(DDR0_11, sdram_data);
 141         printf("        DDR0_11 = 0x%08X\n", sdram_data);
 142         mfsdram(DDR0_12, sdram_data);
 143         printf("        DDR0_12 = 0x%08X", sdram_data);
 144         mfsdram(DDR0_14, sdram_data);
 145         printf("        DDR0_14 = 0x%08X\n", sdram_data);
 146         mfsdram(DDR0_17, sdram_data);
 147         printf("        DDR0_17 = 0x%08X", sdram_data);
 148         mfsdram(DDR0_18, sdram_data);
 149         printf("        DDR0_18 = 0x%08X\n", sdram_data);
 150         mfsdram(DDR0_19, sdram_data);
 151         printf("        DDR0_19 = 0x%08X", sdram_data);
 152         mfsdram(DDR0_20, sdram_data);
 153         printf("        DDR0_20 = 0x%08X\n", sdram_data);
 154         mfsdram(DDR0_21, sdram_data);
 155         printf("        DDR0_21 = 0x%08X", sdram_data);
 156         mfsdram(DDR0_22, sdram_data);
 157         printf("        DDR0_22 = 0x%08X\n", sdram_data);
 158         mfsdram(DDR0_23, sdram_data);
 159         printf("        DDR0_23 = 0x%08X", sdram_data);
 160         mfsdram(DDR0_24, sdram_data);
 161         printf("        DDR0_24 = 0x%08X\n", sdram_data);
 162         mfsdram(DDR0_25, sdram_data);
 163         printf("        DDR0_25 = 0x%08X", sdram_data);
 164         mfsdram(DDR0_26, sdram_data);
 165         printf("        DDR0_26 = 0x%08X\n", sdram_data);
 166         mfsdram(DDR0_27, sdram_data);
 167         printf("        DDR0_27 = 0x%08X", sdram_data);
 168         mfsdram(DDR0_28, sdram_data);
 169         printf("        DDR0_28 = 0x%08X\n", sdram_data);
 170         mfsdram(DDR0_31, sdram_data);
 171         printf("        DDR0_31 = 0x%08X", sdram_data);
 172         mfsdram(DDR0_32, sdram_data);
 173         printf("        DDR0_32 = 0x%08X\n", sdram_data);
 174         mfsdram(DDR0_33, sdram_data);
 175         printf("        DDR0_33 = 0x%08X", sdram_data);
 176         mfsdram(DDR0_34, sdram_data);
 177         printf("        DDR0_34 = 0x%08X\n", sdram_data);
 178         mfsdram(DDR0_35, sdram_data);
 179         printf("        DDR0_35 = 0x%08X", sdram_data);
 180         mfsdram(DDR0_36, sdram_data);
 181         printf("        DDR0_36 = 0x%08X\n", sdram_data);
 182         mfsdram(DDR0_37, sdram_data);
 183         printf("        DDR0_37 = 0x%08X", sdram_data);
 184         mfsdram(DDR0_38, sdram_data);
 185         printf("        DDR0_38 = 0x%08X\n", sdram_data);
 186         mfsdram(DDR0_39, sdram_data);
 187         printf("        DDR0_39 = 0x%08X", sdram_data);
 188         mfsdram(DDR0_40, sdram_data);
 189         printf("        DDR0_40 = 0x%08X\n", sdram_data);
 190         mfsdram(DDR0_41, sdram_data);
 191         printf("        DDR0_41 = 0x%08X", sdram_data);
 192         mfsdram(DDR0_42, sdram_data);
 193         printf("        DDR0_42 = 0x%08X\n", sdram_data);
 194         mfsdram(DDR0_43, sdram_data);
 195         printf("        DDR0_43 = 0x%08X", sdram_data);
 196         mfsdram(DDR0_44, sdram_data);
 197         printf("        DDR0_44 = 0x%08X\n", sdram_data);
 198 }
 199 #else
 200 static inline void denali_sdram_register_dump(void)
 201 {
 202 }
 203
 204 inline static void print_mcsr(void)
 205 {
 206 }
 207 #endif /* defined(DEBUG) */
 208
 209 static int is_ecc_enabled(void)
 210 {
 211         u32 val;
 212
 213         mfsdram(DDR0_22, val);
 214         return 0x3 == DDR0_22_CTRL_RAW_DECODE(val);
 215 }
 216
 217 static unsigned char spd_read(u8 chip, unsigned int addr)
 218 {
 219         u8 data[2];
 220
 221         if (0 != i2c_probe(chip) || 0 != i2c_read(chip, addr, 1, data, 1)) {
 222                 debug("spd_read(0x%02X, 0x%02X) failed\n", chip, addr);
 223                 return 0;
 224         }
 225         debug("spd_read(0x%02X, 0x%02X) returned 0x%02X\n",
 226               chip, addr, data[0]);
 227         return data[0];
 228 }
 229
 230 static unsigned long get_tcyc(unsigned char reg)
 231 {
 232         /*
 233          * Byte 9, et al: Cycle time for CAS Latency=X, is split into two
 234          * nibbles: the higher order nibble (bits 4-7) designates the cycle time
 235          * to a granularity of 1ns; the value presented by the lower order
 236          * nibble (bits 0-3) has a granularity of .1ns and is added to the value
 237          * designated by the higher nibble. In addition, four lines of the lower
 238          * order nibble are assigned to support +.25, +.33, +.66, and +.75.
 239          */
 240
 241         unsigned char subfield_b = reg & 0x0F;
 242
 243         switch (subfield_b & 0x0F) {
 244         case 0x0:
 245         case 0x1:
 246         case 0x2:
 247         case 0x3:
 248         case 0x4:
 249         case 0x5:
 250         case 0x6:
 251         case 0x7:
 252         case 0x8:
 253         case 0x9:
 254                 return 1000 * (reg >> 4) + 100 * subfield_b;
 255         case 0xA:
 256                 return 1000 * (reg >> 4) + 250;
 257         case 0xB:
 258                 return 1000 * (reg >> 4) + 333;
 259         case 0xC:
 260                 return 1000 * (reg >> 4) + 667;
 261         case 0xD:
 262                 return 1000 * (reg >> 4) + 750;
 263         }
 264         return 0;
 265 }
 266
 267 /*------------------------------------------------------------------
 268  * Find the installed DIMMs, make sure that the are DDR2, and fill
 269  * in the dimm_ranks array.  Then dimm_ranks[dimm_num] > 0 iff the
 270  * DIMM and dimm_num is present.
 271  * Note: Because there are only two chip-select lines, it is assumed
 272  * that a board with a single socket can support two ranks on that
 273  * socket, while a board with two sockets can support only one rank
 274  * on each socket.
 275  *-----------------------------------------------------------------*/
 276 static void get_spd_info(unsigned long dimm_ranks[],
 277                          unsigned long *ranks,
 278                          unsigned char const iic0_dimm_addr[],
 279                          unsigned long num_dimm_banks)
 280 {
 281         unsigned long dimm_num;
 282         unsigned long dimm_found = FALSE;
 283         unsigned long const max_ranks_per_dimm = (1 == num_dimm_banks) ? 2 : 1;
 284         unsigned char num_of_bytes;
 285         unsigned char total_size;
 286
 287         *ranks = 0;
 288         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 289                 num_of_bytes = 0;
 290                 total_size = 0;
 291
 292                 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
 293                 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 294                 if ((num_of_bytes != 0) && (total_size != 0)) {
 295                         unsigned char const dimm_type =
 296                             spd_read(iic0_dimm_addr[dimm_num], 2);
 297
 298                         unsigned long ranks_on_dimm =
 299                             (spd_read(iic0_dimm_addr[dimm_num], 5) & 0x07) + 1;
 300
 301                         if (8 != dimm_type) {
 302                                 switch (dimm_type) {
 303                                 case 1:
 304                                         printf("ERROR: Standard Fast Page Mode "
 305                                                "DRAM DIMM");
 306                                         break;
 307                                 case 2:
 308                                         printf("ERROR: EDO DIMM");
 309                                         break;
 310                                 case 3:
 311                                         printf("ERROR: Pipelined Nibble DIMM");
 312                                         break;
 313                                 case 4:
 314                                         printf("ERROR: SDRAM DIMM");
 315                                         break;
 316                                 case 5:
 317                                         printf("ERROR: Multiplexed ROM DIMM");
 318                                         break;
 319                                 case 6:
 320                                         printf("ERROR: SGRAM DIMM");
 321                                         break;
 322                                 case 7:
 323                                         printf("ERROR: DDR1 DIMM");
 324                                         break;
 325                                 default:
 326                                         printf("ERROR: Unknown DIMM (type %d)",
 327                                                (unsigned int)dimm_type);
 328                                         break;
 329                                 }
 330                                 printf(" detected in slot %lu.\n", dimm_num);
 331                                 printf("Only DDR2 SDRAM DIMMs are supported."
 332                                        "\n");
 333                                 printf("Replace the module with a DDR2 DIMM."
 334                                        "\n\n");
 335                                 spd_ddr_init_hang();
 336                         }
 337                         dimm_found = TRUE;
 338                         debug("DIMM slot %lu: populated with %lu-rank DDR2 DIMM"
 339                               "\n", dimm_num, ranks_on_dimm);
 340                         if (ranks_on_dimm > max_ranks_per_dimm) {
 341                                 printf("WARNING: DRAM DIMM in slot %lu has %lu "
 342                                        "ranks.\n", dimm_num, ranks_on_dimm);
 343                                 if (1 == max_ranks_per_dimm) {
 344                                         printf("Only one rank will be used.\n");
 345                                 } else {
 346                                         printf
 347                                             ("Only two ranks will be used.\n");
 348                                 }
 349                                 ranks_on_dimm = max_ranks_per_dimm;
 350                         }
 351                         dimm_ranks[dimm_num] = ranks_on_dimm;
 352                         *ranks += ranks_on_dimm;
 353                 } else {
 354                         dimm_ranks[dimm_num] = 0;
 355                         debug("DIMM slot %lu: Not populated\n", dimm_num);
 356                 }
 357         }
 358         if (dimm_found == FALSE) {
 359                 printf("ERROR: No memory installed.\n");
 360                 printf("Install at least one DDR2 DIMM.\n\n");
 361                 spd_ddr_init_hang();
 362         }
 363         debug("Total number of ranks = %d\n", *ranks);
 364 }
 365
 366 /*------------------------------------------------------------------
 367  * For the memory DIMMs installed, this routine verifies that
 368  * frequency previously calculated is supported.
 369  *-----------------------------------------------------------------*/
 370 static void check_frequency(unsigned long *dimm_ranks,
 371                             unsigned char const iic0_dimm_addr[],
 372                             unsigned long num_dimm_banks,
 373                             unsigned long sdram_freq)
 374 {
 375         unsigned long dimm_num;
 376         unsigned long cycle_time;
 377         unsigned long calc_cycle_time;
 378
 379         /*
 380          * calc_cycle_time is calculated from DDR frequency set by board/chip
 381          * and is expressed in picoseconds to match the way DIMM cycle time is
 382          * calculated below.
 383          */
 384         calc_cycle_time = MULDIV64(ONE_BILLION, 1000, sdram_freq);
 385
 386         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 387                 if (dimm_ranks[dimm_num]) {
 388                         cycle_time =
 389                             get_tcyc(spd_read(iic0_dimm_addr[dimm_num], 9));
 390                         debug("cycle_time=%d ps\n", cycle_time);
 391
 392                         if (cycle_time > (calc_cycle_time + 10)) {
 393                                 /*
 394                                  * the provided sdram cycle_time is too small
 395                                  * for the available DIMM cycle_time. The
 396                                  * additionnal 10ps is here to accept a small
 397                                  * incertainty.
 398                                  */
 399                                 printf
 400                                     ("ERROR: DRAM DIMM detected with cycle_time %d ps in "
 401                                      "slot %d \n while calculated cycle time is %d ps.\n",
 402                                      (unsigned int)cycle_time,
 403                                      (unsigned int)dimm_num,
 404                                      (unsigned int)calc_cycle_time);
 405                                 printf
 406                                     ("Replace the DIMM, or change DDR frequency via "
 407                                      "strapping bits.\n\n");
 408                                 spd_ddr_init_hang();
 409                         }
 410                 }
 411         }
 412 }
 413
 414 /*------------------------------------------------------------------
 415  * This routine gets size information for the installed memory
 416  * DIMMs.
 417  *-----------------------------------------------------------------*/
 418 static void get_dimm_size(unsigned long dimm_ranks[],
 419                           unsigned char const iic0_dimm_addr[],
 420                           unsigned long num_dimm_banks,
 421                           unsigned long *const rows,
 422                           unsigned long *const banks,
 423                           unsigned long *const cols, unsigned long *const width)
 424 {
 425         unsigned long dimm_num;
 426
 427         *rows = 0;
 428         *banks = 0;
 429         *cols = 0;
 430         *width = 0;
 431         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 432                 if (dimm_ranks[dimm_num]) {
 433                         unsigned long t;
 434
 435                         /* Rows */
 436                         t = spd_read(iic0_dimm_addr[dimm_num], 3);
 437                         if (0 == *rows) {
 438                                 *rows = t;
 439                         } else if (t != *rows) {
 440                                 printf("ERROR: DRAM DIMM modules do not all "
 441                                        "have the same number of rows.\n\n");
 442                                 spd_ddr_init_hang();
 443                         }
 444                         /* Banks */
 445                         t = spd_read(iic0_dimm_addr[dimm_num], 17);
 446                         if (0 == *banks) {
 447                                 *banks = t;
 448                         } else if (t != *banks) {
 449                                 printf("ERROR: DRAM DIMM modules do not all "
 450                                        "have the same number of banks.\n\n");
 451                                 spd_ddr_init_hang();
 452                         }
 453                         /* Columns */
 454                         t = spd_read(iic0_dimm_addr[dimm_num], 4);
 455                         if (0 == *cols) {
 456                                 *cols = t;
 457                         } else if (t != *cols) {
 458                                 printf("ERROR: DRAM DIMM modules do not all "
 459                                        "have the same number of columns.\n\n");
 460                                 spd_ddr_init_hang();
 461                         }
 462                         /* Data width */
 463                         t = spd_read(iic0_dimm_addr[dimm_num], 6);
 464                         if (0 == *width) {
 465                                 *width = t;
 466                         } else if (t != *width) {
 467                                 printf("ERROR: DRAM DIMM modules do not all "
 468                                        "have the same data width.\n\n");
 469                                 spd_ddr_init_hang();
 470                         }
 471                 }
 472         }
 473         debug("Number of rows = %d\n", *rows);
 474         debug("Number of columns = %d\n", *cols);
 475         debug("Number of banks = %d\n", *banks);
 476         debug("Data width = %d\n", *width);
 477         if (*rows > 14) {
 478                 printf("ERROR: DRAM DIMM modules have %lu address rows.\n",
 479                        *rows);
 480                 printf("Only modules with 14 or fewer rows are supported.\n\n");
 481                 spd_ddr_init_hang();
 482         }
 483         if (4 != *banks && 8 != *banks) {
 484                 printf("ERROR: DRAM DIMM modules have %lu banks.\n", *banks);
 485                 printf("Only modules with 4 or 8 banks are supported.\n\n");
 486                 spd_ddr_init_hang();
 487         }
 488         if (*cols > 12) {
 489                 printf("ERROR: DRAM DIMM modules have %lu address columns.\n",
 490                        *cols);
 491                 printf("Only modules with 12 or fewer columns are "
 492                        "supported.\n\n");
 493                 spd_ddr_init_hang();
 494         }
 495         if (32 != *width && 40 != *width && 64 != *width && 72 != *width) {
 496                 printf("ERROR: DRAM DIMM modules have a width of %lu bit.\n",
 497                        *width);
 498                 printf("Only modules with widths of 32, 40, 64, and 72 bits "
 499                        "are supported.\n\n");
 500                 spd_ddr_init_hang();
 501         }
 502 }
 503
 504 /*------------------------------------------------------------------
 505  * Only 1.8V modules are supported.  This routine verifies this.
 506  *-----------------------------------------------------------------*/
 507 static void check_voltage_type(unsigned long dimm_ranks[],
 508                                unsigned char const iic0_dimm_addr[],
 509                                unsigned long num_dimm_banks)
 510 {
 511         unsigned long dimm_num;
 512         unsigned long voltage_type;
 513
 514         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 515                 if (dimm_ranks[dimm_num]) {
 516                         voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
 517                         if (0x05 != voltage_type) {     /* 1.8V for DDR2 */
 518                                 printf("ERROR: Slot %lu provides 1.8V for DDR2 "
 519                                        "DIMMs.\n", dimm_num);
 520                                 switch (voltage_type) {
 521                                 case 0x00:
 522                                         printf("This DIMM is 5.0 Volt/TTL.\n");
 523                                         break;
 524                                 case 0x01:
 525                                         printf("This DIMM is LVTTL.\n");
 526                                         break;
 527                                 case 0x02:
 528                                         printf("This DIMM is 1.5 Volt.\n");
 529                                         break;
 530                                 case 0x03:
 531                                         printf("This DIMM is 3.3 Volt/TTL.\n");
 532                                         break;
 533                                 case 0x04:
 534                                         printf("This DIMM is 2.5 Volt.\n");
 535                                         break;
 536                                 default:
 537                                         printf("This DIMM is an unknown "
 538                                                "voltage.\n");
 539                                         break;
 540                                 }
 541                                 printf("Replace it with a 1.8V DDR2 DIMM.\n\n");
 542                                 spd_ddr_init_hang();
 543                         }
 544                 }
 545         }
 546 }
 547
 548 static void program_ddr0_03(unsigned long dimm_ranks[],
 549                             unsigned char const iic0_dimm_addr[],
 550                             unsigned long num_dimm_banks,
 551                             unsigned long sdram_freq,
 552                             unsigned long rows, unsigned long *cas_latency)
 553 {
 554         unsigned long dimm_num;
 555         unsigned long cas_index;
 556         unsigned long cycle_2_0_clk;
 557         unsigned long cycle_3_0_clk;
 558         unsigned long cycle_4_0_clk;
 559         unsigned long cycle_5_0_clk;
 560         unsigned long max_2_0_tcyc_ps = 100;
 561         unsigned long max_3_0_tcyc_ps = 100;
 562         unsigned long max_4_0_tcyc_ps = 100;
 563         unsigned long max_5_0_tcyc_ps = 100;
 564         unsigned char cas_available = 0x3C;     /* value for DDR2 */
 565         u32 ddr0_03 = DDR0_03_BSTLEN_ENCODE(0x2) | DDR0_03_INITAREF_ENCODE(0x2);
 566         unsigned int const tcyc_addr[3] = { 9, 23, 25 };
 567
 568         /*------------------------------------------------------------------
 569          * Get the board configuration info.
 570          *-----------------------------------------------------------------*/
 571         debug("sdram_freq = %d\n", sdram_freq);
 572
 573         /*------------------------------------------------------------------
 574          * Handle the timing.  We need to find the worst case timing of all
 575          * the dimm modules installed.
 576          *-----------------------------------------------------------------*/
 577         /* loop through all the DIMM slots on the board */
 578         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 579                 /* If a dimm is installed in a particular slot ... */
 580                 if (dimm_ranks[dimm_num]) {
 581                         unsigned char const cas_bit =
 582                             spd_read(iic0_dimm_addr[dimm_num], 18);
 583                         unsigned char cas_mask;
 584
 585                         cas_available &= cas_bit;
 586                         for (cas_mask = 0x80; cas_mask; cas_mask >>= 1) {
 587                                 if (cas_bit & cas_mask)
 588                                         break;
 589                         }
 590                         debug("cas_bit (SPD byte 18) = %02X, cas_mask = %02X\n",
 591                               cas_bit, cas_mask);
 592
 593                         for (cas_index = 0; cas_index < 3;
 594                              cas_mask >>= 1, cas_index++) {
 595                                 unsigned long cycle_time_ps;
 596
 597                                 if (!(cas_available & cas_mask)) {
 598                                         continue;
 599                                 }
 600                                 cycle_time_ps =
 601                                     get_tcyc(spd_read(iic0_dimm_addr[dimm_num],
 602                                                       tcyc_addr[cas_index]));
 603
 604                                 debug("cas_index = %d: cycle_time_ps = %d\n",
 605                                       cas_index, cycle_time_ps);
 606                                 /*
 607                                  * DDR2 devices use the following bitmask for CAS latency:
 608                                  *  Bit   7    6    5    4    3    2    1    0
 609                                  *       TBD  6.0  5.0  4.0  3.0  2.0  TBD  TBD
 610                                  */
 611                                 switch (cas_mask) {
 612                                 case 0x20:
 613                                         max_5_0_tcyc_ps =
 614                                             max(max_5_0_tcyc_ps, cycle_time_ps);
 615                                         break;
 616                                 case 0x10:
 617                                         max_4_0_tcyc_ps =
 618                                             max(max_4_0_tcyc_ps, cycle_time_ps);
 619                                         break;
 620                                 case 0x08:
 621                                         max_3_0_tcyc_ps =
 622                                             max(max_3_0_tcyc_ps, cycle_time_ps);
 623                                         break;
 624                                 case 0x04:
 625                                         max_2_0_tcyc_ps =
 626                                             max(max_2_0_tcyc_ps, cycle_time_ps);
 627                                         break;
 628                                 }
 629                         }
 630                 }
 631         }
 632         debug("cas_available (bit map) = 0x%02X\n", cas_available);
 633
 634         /*------------------------------------------------------------------
 635          * Set the SDRAM mode, SDRAM_MMODE
 636          *-----------------------------------------------------------------*/
 637
 638         /* add 10 here because of rounding problems */
 639         cycle_2_0_clk = MULDIV64(ONE_BILLION, 1000, max_2_0_tcyc_ps) + 10;
 640         cycle_3_0_clk = MULDIV64(ONE_BILLION, 1000, max_3_0_tcyc_ps) + 10;
 641         cycle_4_0_clk = MULDIV64(ONE_BILLION, 1000, max_4_0_tcyc_ps) + 10;
 642         cycle_5_0_clk = MULDIV64(ONE_BILLION, 1000, max_5_0_tcyc_ps) + 10;
 643         debug("cycle_2_0_clk = %d\n", cycle_2_0_clk);
 644         debug("cycle_3_0_clk = %d\n", cycle_3_0_clk);
 645         debug("cycle_4_0_clk = %d\n", cycle_4_0_clk);
 646         debug("cycle_5_0_clk = %d\n", cycle_5_0_clk);
 647
 648         if ((cas_available & 0x04) && (sdram_freq <= cycle_2_0_clk)) {
 649                 *cas_latency = 2;
 650                 ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x2) |
 651                     DDR0_03_CASLAT_LIN_ENCODE(0x4);
 652         } else if ((cas_available & 0x08) && (sdram_freq <= cycle_3_0_clk)) {
 653                 *cas_latency = 3;
 654                 ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x3) |
 655                     DDR0_03_CASLAT_LIN_ENCODE(0x6);
 656         } else if ((cas_available & 0x10) && (sdram_freq <= cycle_4_0_clk)) {
 657                 *cas_latency = 4;
 658                 ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x4) |
 659                     DDR0_03_CASLAT_LIN_ENCODE(0x8);
 660         } else if ((cas_available & 0x20) && (sdram_freq <= cycle_5_0_clk)) {
 661                 *cas_latency = 5;
 662                 ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x5) |
 663                     DDR0_03_CASLAT_LIN_ENCODE(0xA);
 664         } else {
 665                 printf("ERROR: Cannot find a supported CAS latency with the "
 666                        "installed DIMMs.\n");
 667                 printf("Only DDR2 DIMMs with CAS latencies of 2.0, 3.0, 4.0, "
 668                        "and 5.0 are supported.\n");
 669                 printf("Make sure the PLB speed is within the supported range "
 670                        "of the DIMMs.\n");
 671                 printf("sdram_freq=%ld cycle2=%ld cycle3=%ld cycle4=%ld "
 672                        "cycle5=%ld\n\n", sdram_freq, cycle_2_0_clk,
 673                        cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
 674                 spd_ddr_init_hang();
 675         }
 676         debug("CAS latency = %d\n", *cas_latency);
 677         mtsdram(DDR0_03, ddr0_03);
 678 }
 679
 680 static void program_ddr0_04(unsigned long dimm_ranks[],
 681                             unsigned char const iic0_dimm_addr[],
 682                             unsigned long num_dimm_banks,
 683                             unsigned long sdram_freq)
 684 {
 685         unsigned long dimm_num;
 686         unsigned long t_rc_ps = 0;
 687         unsigned long t_rrd_ps = 0;
 688         unsigned long t_rtp_ps = 0;
 689         unsigned long t_rc_clk;
 690         unsigned long t_rrd_clk;
 691         unsigned long t_rtp_clk;
 692
 693         /*------------------------------------------------------------------
 694          * Handle the timing.  We need to find the worst case timing of all
 695          * the dimm modules installed.
 696          *-----------------------------------------------------------------*/
 697         /* loop through all the DIMM slots on the board */
 698         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 699                 /* If a dimm is installed in a particular slot ... */
 700                 if (dimm_ranks[dimm_num]) {
 701                         unsigned long ps;
 702
 703                         /* tRC */
 704                         ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 41);
 705                         switch (spd_read(iic0_dimm_addr[dimm_num], 40) >> 4) {
 706                         case 0x1:
 707                                 ps += 250;
 708                                 break;
 709                         case 0x2:
 710                                 ps += 333;
 711                                 break;
 712                         case 0x3:
 713                                 ps += 500;
 714                                 break;
 715                         case 0x4:
 716                                 ps += 667;
 717                                 break;
 718                         case 0x5:
 719                                 ps += 750;
 720                                 break;
 721                         }
 722                         t_rc_ps = max(t_rc_ps, ps);
 723                         /* tRRD */
 724                         ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 28);
 725                         t_rrd_ps = max(t_rrd_ps, ps);
 726                         /* tRTP */
 727                         ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 38);
 728                         t_rtp_ps = max(t_rtp_ps, ps);
 729                 }
 730         }
 731         debug("t_rc_ps  = %d\n", t_rc_ps);
 732         t_rc_clk = (MULDIV64(sdram_freq, t_rc_ps, ONE_BILLION) + 999) / 1000;
 733         debug("t_rrd_ps = %d\n", t_rrd_ps);
 734         t_rrd_clk = (MULDIV64(sdram_freq, t_rrd_ps, ONE_BILLION) + 999) / 1000;
 735         debug("t_rtp_ps = %d\n", t_rtp_ps);
 736         t_rtp_clk = (MULDIV64(sdram_freq, t_rtp_ps, ONE_BILLION) + 999) / 1000;
 737         mtsdram(DDR0_04, DDR0_04_TRC_ENCODE(t_rc_clk) |
 738                 DDR0_04_TRRD_ENCODE(t_rrd_clk) |
 739                 DDR0_04_TRTP_ENCODE(t_rtp_clk));
 740 }
 741
 742 static void program_ddr0_05(unsigned long dimm_ranks[],
 743                             unsigned char const iic0_dimm_addr[],
 744                             unsigned long num_dimm_banks,
 745                             unsigned long sdram_freq)
 746 {
 747         unsigned long dimm_num;
 748         unsigned long t_rp_ps = 0;
 749         unsigned long t_ras_ps = 0;
 750         unsigned long t_rp_clk;
 751         unsigned long t_ras_clk;
 752         u32 ddr0_05 = DDR0_05_TMRD_ENCODE(0x2) | DDR0_05_TEMRS_ENCODE(0x2);
 753
 754         /*------------------------------------------------------------------
 755          * Handle the timing.  We need to find the worst case timing of all
 756          * the dimm modules installed.
 757          *-----------------------------------------------------------------*/
 758         /* loop through all the DIMM slots on the board */
 759         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 760                 /* If a dimm is installed in a particular slot ... */
 761                 if (dimm_ranks[dimm_num]) {
 762                         unsigned long ps;
 763
 764                         /* tRP */
 765                         ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 27);
 766                         t_rp_ps = max(t_rp_ps, ps);
 767                         /* tRAS */
 768                         ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 30);
 769                         t_ras_ps = max(t_ras_ps, ps);
 770                 }
 771         }
 772         debug("t_rp_ps  = %d\n", t_rp_ps);
 773         t_rp_clk = (MULDIV64(sdram_freq, t_rp_ps, ONE_BILLION) + 999) / 1000;
 774         debug("t_ras_ps = %d\n", t_ras_ps);
 775         t_ras_clk = (MULDIV64(sdram_freq, t_ras_ps, ONE_BILLION) + 999) / 1000;
 776         mtsdram(DDR0_05, ddr0_05 | DDR0_05_TRP_ENCODE(t_rp_clk) |
 777                 DDR0_05_TRAS_MIN_ENCODE(t_ras_clk));
 778 }
 779
 780 static void program_ddr0_06(unsigned long dimm_ranks[],
 781                             unsigned char const iic0_dimm_addr[],
 782                             unsigned long num_dimm_banks,
 783                             unsigned long sdram_freq)
 784 {
 785         unsigned long dimm_num;
 786         unsigned char spd_40;
 787         unsigned long t_wtr_ps = 0;
 788         unsigned long t_rfc_ps = 0;
 789         unsigned long t_wtr_clk;
 790         unsigned long t_rfc_clk;
 791         u32 ddr0_06 =
 792             DDR0_06_WRITEINTERP_ENCODE(0x1) | DDR0_06_TDLL_ENCODE(200);
 793
 794         /*------------------------------------------------------------------
 795          * Handle the timing.  We need to find the worst case timing of all
 796          * the dimm modules installed.
 797          *-----------------------------------------------------------------*/
 798         /* loop through all the DIMM slots on the board */
 799         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 800                 /* If a dimm is installed in a particular slot ... */
 801                 if (dimm_ranks[dimm_num]) {
 802                         unsigned long ps;
 803
 804                         /* tWTR */
 805                         ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 37);
 806                         t_wtr_ps = max(t_wtr_ps, ps);
 807                         /* tRFC */
 808                         ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 42);
 809                         spd_40 = spd_read(iic0_dimm_addr[dimm_num], 40);
 810                         ps += 256000 * (spd_40 & 0x01);
 811                         switch ((spd_40 & 0x0E) >> 1) {
 812                         case 0x1:
 813                                 ps += 250;
 814                                 break;
 815                         case 0x2:
 816                                 ps += 333;
 817                                 break;
 818                         case 0x3:
 819                                 ps += 500;
 820                                 break;
 821                         case 0x4:
 822                                 ps += 667;
 823                                 break;
 824                         case 0x5:
 825                                 ps += 750;
 826                                 break;
 827                         }
 828                         t_rfc_ps = max(t_rfc_ps, ps);
 829                 }
 830         }
 831         debug("t_wtr_ps = %d\n", t_wtr_ps);
 832         t_wtr_clk = (MULDIV64(sdram_freq, t_wtr_ps, ONE_BILLION) + 999) / 1000;
 833         debug("t_rfc_ps = %d\n", t_rfc_ps);
 834         t_rfc_clk = (MULDIV64(sdram_freq, t_rfc_ps, ONE_BILLION) + 999) / 1000;
 835         mtsdram(DDR0_06, ddr0_06 | DDR0_06_TWTR_ENCODE(t_wtr_clk) |
 836                 DDR0_06_TRFC_ENCODE(t_rfc_clk));
 837 }
 838
 839 static void program_ddr0_10(unsigned long dimm_ranks[], unsigned long ranks)
 840 {
 841         unsigned long csmap;
 842
 843         if (2 == ranks) {
 844                 /* Both chip selects in use */
 845                 csmap = 0x03;
 846         } else {
 847                 /* One chip select in use */
 848                 csmap = (1 == dimm_ranks[0]) ? 0x1 : 0x2;
 849         }
 850         mtsdram(DDR0_10, DDR0_10_WRITE_MODEREG_ENCODE(0x0) |
 851                 DDR0_10_CS_MAP_ENCODE(csmap) |
 852                 DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(0));
 853 }
 854
 855 static void program_ddr0_11(unsigned long sdram_freq)
 856 {
 857         unsigned long const t_xsnr_ps = 200000; /* 200 ns */
 858         unsigned long t_xsnr_clk;
 859
 860         debug("t_xsnr_ps = %d\n", t_xsnr_ps);
 861         t_xsnr_clk =
 862             (MULDIV64(sdram_freq, t_xsnr_ps, ONE_BILLION) + 999) / 1000;
 863         mtsdram(DDR0_11, DDR0_11_SREFRESH_ENCODE(0) |
 864                 DDR0_11_TXSNR_ENCODE(t_xsnr_clk) | DDR0_11_TXSR_ENCODE(200));
 865 }
 866
 867 static void program_ddr0_22(unsigned long dimm_ranks[],
 868                             unsigned char const iic0_dimm_addr[],
 869                             unsigned long num_dimm_banks, unsigned long width)
 870 {
 871 #if defined(CONFIG_DDR_ECC)
 872         unsigned long dimm_num;
 873         unsigned long ecc_available = width >= 64;
 874         u32 ddr0_22 = DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(0x26) |
 875             DDR0_22_DQS_OUT_SHIFT_ENCODE(DQS_OUT_SHIFT) |
 876             DDR0_22_DLL_DQS_BYPASS_8_ENCODE(DLL_DQS_BYPASS);
 877
 878         /* loop through all the DIMM slots on the board */
 879         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 880                 /* If a dimm is installed in a particular slot ... */
 881                 if (dimm_ranks[dimm_num]) {
 882                         /* Check for ECC */
 883                         if (0 == (spd_read(iic0_dimm_addr[dimm_num], 11) &
 884                                   0x02)) {
 885                                 ecc_available = FALSE;
 886                         }
 887                 }
 888         }
 889         if (ecc_available) {
 890                 debug("ECC found on all DIMMs present\n");
 891                 mtsdram(DDR0_22, ddr0_22 | DDR0_22_CTRL_RAW_ENCODE(0x3));
 892         } else {
 893                 debug("ECC not found on some or all DIMMs present\n");
 894                 mtsdram(DDR0_22, ddr0_22 | DDR0_22_CTRL_RAW_ENCODE(0x0));
 895         }
 896 #else
 897         mtsdram(DDR0_22, DDR0_22_CTRL_RAW_ENCODE(0x0) |
 898                 DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(0x26) |
 899                 DDR0_22_DQS_OUT_SHIFT_ENCODE(DQS_OUT_SHIFT) |
 900                 DDR0_22_DLL_DQS_BYPASS_8_ENCODE(DLL_DQS_BYPASS));
 901 #endif /* defined(CONFIG_DDR_ECC) */
 902 }
 903
 904 static void program_ddr0_24(unsigned long ranks)
 905 {
 906         u32 ddr0_24 = DDR0_24_RTT_PAD_TERMINATION_ENCODE(0x1) | /* 75 ohm */
 907             DDR0_24_ODT_RD_MAP_CS1_ENCODE(0x0);
 908
 909         if (2 == ranks) {
 910                 /* Both chip selects in use */
 911                 ddr0_24 |= DDR0_24_ODT_WR_MAP_CS1_ENCODE(0x1) |
 912                     DDR0_24_ODT_WR_MAP_CS0_ENCODE(0x2);
 913         } else {
 914                 /* One chip select in use */
 915                 /* One of the two fields added to ddr0_24 is a "don't care" */
 916                 ddr0_24 |= DDR0_24_ODT_WR_MAP_CS1_ENCODE(0x2) |
 917                     DDR0_24_ODT_WR_MAP_CS0_ENCODE(0x1);
 918         }
 919         mtsdram(DDR0_24, ddr0_24);
 920 }
 921
 922 static void program_ddr0_26(unsigned long sdram_freq)
 923 {
 924         unsigned long const t_ref_ps = 7800000; /* 7.8 us. refresh */
 925         /* TODO: check definition of tRAS_MAX */
 926         unsigned long const t_ras_max_ps = 9 * t_ref_ps;
 927         unsigned long t_ras_max_clk;
 928         unsigned long t_ref_clk;
 929
 930         /* Round down t_ras_max_clk and t_ref_clk */
 931         debug("t_ras_max_ps = %d\n", t_ras_max_ps);
 932         t_ras_max_clk = MULDIV64(sdram_freq, t_ras_max_ps, ONE_BILLION) / 1000;
 933         debug("t_ref_ps     = %d\n", t_ref_ps);
 934         t_ref_clk = MULDIV64(sdram_freq, t_ref_ps, ONE_BILLION) / 1000;
 935         mtsdram(DDR0_26, DDR0_26_TRAS_MAX_ENCODE(t_ras_max_clk) |
 936                 DDR0_26_TREF_ENCODE(t_ref_clk));
 937 }
 938
 939 static void program_ddr0_27(unsigned long sdram_freq)
 940 {
 941         unsigned long const t_init_ps = 200000000;      /* 200 us. init */
 942         unsigned long t_init_clk;
 943
 944         debug("t_init_ps = %d\n", t_init_ps);
 945         t_init_clk =
 946             (MULDIV64(sdram_freq, t_init_ps, ONE_BILLION) + 999) / 1000;
 947         mtsdram(DDR0_27, DDR0_27_EMRS_DATA_ENCODE(0x0000) |
 948                 DDR0_27_TINIT_ENCODE(t_init_clk));
 949 }
 950
 951 static void program_ddr0_43(unsigned long dimm_ranks[],
 952                             unsigned char const iic0_dimm_addr[],
 953                             unsigned long num_dimm_banks,
 954                             unsigned long sdram_freq,
 955                             unsigned long cols, unsigned long banks)
 956 {
 957         unsigned long dimm_num;
 958         unsigned long t_wr_ps = 0;
 959         unsigned long t_wr_clk;
 960         u32 ddr0_43 = DDR0_43_APREBIT_ENCODE(10) |
 961             DDR0_43_COLUMN_SIZE_ENCODE(12 - cols) |
 962             DDR0_43_EIGHT_BANK_MODE_ENCODE(8 == banks ? 1 : 0);
 963
 964         /*------------------------------------------------------------------
 965          * Handle the timing.  We need to find the worst case timing of all
 966          * the dimm modules installed.
 967          *-----------------------------------------------------------------*/
 968         /* loop through all the DIMM slots on the board */
 969         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 970                 /* If a dimm is installed in a particular slot ... */
 971                 if (dimm_ranks[dimm_num]) {
 972                         unsigned long ps;
 973
 974                         ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 36);
 975                         t_wr_ps = max(t_wr_ps, ps);
 976                 }
 977         }
 978         debug("t_wr_ps = %d\n", t_wr_ps);
 979         t_wr_clk = (MULDIV64(sdram_freq, t_wr_ps, ONE_BILLION) + 999) / 1000;
 980         mtsdram(DDR0_43, ddr0_43 | DDR0_43_TWR_ENCODE(t_wr_clk));
 981 }
 982
 983 static void program_ddr0_44(unsigned long dimm_ranks[],
 984                             unsigned char const iic0_dimm_addr[],
 985                             unsigned long num_dimm_banks,
 986                             unsigned long sdram_freq)
 987 {
 988         unsigned long dimm_num;
 989         unsigned long t_rcd_ps = 0;
 990         unsigned long t_rcd_clk;
 991
 992         /*------------------------------------------------------------------
 993          * Handle the timing.  We need to find the worst case timing of all
 994          * the dimm modules installed.
 995          *-----------------------------------------------------------------*/
 996         /* loop through all the DIMM slots on the board */
 997         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 998                 /* If a dimm is installed in a particular slot ... */
 999                 if (dimm_ranks[dimm_num]) {
1000                         unsigned long ps;
1001
1002                         ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 29);
1003                         t_rcd_ps = max(t_rcd_ps, ps);
1004                 }
1005         }
1006         debug("t_rcd_ps = %d\n", t_rcd_ps);
1007         t_rcd_clk = (MULDIV64(sdram_freq, t_rcd_ps, ONE_BILLION) + 999) / 1000;
1008         mtsdram(DDR0_44, DDR0_44_TRCD_ENCODE(t_rcd_clk));
1009 }
1010
1011 /*-----------------------------------------------------------------------------+
1012  * initdram.  Initializes the 440EPx/GPx DDR SDRAM controller.
1013  * Note: This routine runs from flash with a stack set up in the chip's
1014  * sram space.  It is important that the routine does not require .sbss, .bss or
1015  * .data sections.  It also cannot call routines that require these sections.
1016  *-----------------------------------------------------------------------------*/
1017 /*-----------------------------------------------------------------------------
1018  * Function:     initdram
1019  * Description:  Configures SDRAM memory banks for DDR operation.
1020  *               Auto Memory Configuration option reads the DDR SDRAM EEPROMs
1021  *               via the IIC bus and then configures the DDR SDRAM memory
1022  *               banks appropriately. If Auto Memory Configuration is
1023  *               not used, it is assumed that no DIMM is plugged
1024  *-----------------------------------------------------------------------------*/
1025 phys_size_t initdram(int board_type)
1026 {
1027         unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
1028         unsigned long dimm_ranks[MAXDIMMS];
1029         unsigned long ranks;
1030         unsigned long rows;
1031         unsigned long banks;
1032         unsigned long cols;
1033         unsigned long width;
1034         unsigned long const sdram_freq = get_bus_freq(0);
1035         unsigned long const num_dimm_banks = sizeof(iic0_dimm_addr);    /* on board dimm banks */
1036         unsigned long cas_latency = 0;  /* to quiet initialization warning */
1037         unsigned long dram_size;
1038
1039         debug("\nEntering initdram()\n");
1040
1041         /*------------------------------------------------------------------
1042          * Stop the DDR-SDRAM controller.
1043          *-----------------------------------------------------------------*/
1044         mtsdram(DDR0_02, DDR0_02_START_ENCODE(0));
1045
1046         /*
1047          * Make sure I2C controller is initialized
1048          * before continuing.
1049          */
1050         /* switch to correct I2C bus */
1051         I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
1052         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
1053
1054         /*------------------------------------------------------------------
1055          * Clear out the serial presence detect buffers.
1056          * Perform IIC reads from the dimm.  Fill in the spds.
1057          * Check to see if the dimm slots are populated
1058          *-----------------------------------------------------------------*/
1059         get_spd_info(dimm_ranks, &ranks, iic0_dimm_addr, num_dimm_banks);
1060
1061         /*------------------------------------------------------------------
1062          * Check the frequency supported for the dimms plugged.
1063          *-----------------------------------------------------------------*/
1064         check_frequency(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
1065
1066         /*------------------------------------------------------------------
1067          * Check and get size information.
1068          *-----------------------------------------------------------------*/
1069         get_dimm_size(dimm_ranks, iic0_dimm_addr, num_dimm_banks, &rows, &banks,
1070                       &cols, &width);
1071
1072         /*------------------------------------------------------------------
1073          * Check the voltage type for the dimms plugged.
1074          *-----------------------------------------------------------------*/
1075         check_voltage_type(dimm_ranks, iic0_dimm_addr, num_dimm_banks);
1076
1077         /*------------------------------------------------------------------
1078          * Program registers for SDRAM controller.
1079          *-----------------------------------------------------------------*/
1080         mtsdram(DDR0_00, DDR0_00_DLL_INCREMENT_ENCODE(0x19) |
1081                 DDR0_00_DLL_START_POINT_DECODE(0x0A));
1082
1083         mtsdram(DDR0_01, DDR0_01_PLB0_DB_CS_LOWER_ENCODE(0x01) |
1084                 DDR0_01_PLB0_DB_CS_UPPER_ENCODE(0x00) |
1085                 DDR0_01_INT_MASK_ENCODE(0xFF));
1086
1087         program_ddr0_03(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq,
1088                         rows, &cas_latency);
1089
1090         program_ddr0_04(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
1091
1092         program_ddr0_05(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
1093
1094         program_ddr0_06(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
1095
1096         /*
1097          * TODO: tFAW not found in SPD.  Value of 13 taken from Sequoia
1098          * board SDRAM, but may be overly conservative.
1099          */
1100         mtsdram(DDR0_07, DDR0_07_NO_CMD_INIT_ENCODE(0) |
1101                 DDR0_07_TFAW_ENCODE(13) |
1102                 DDR0_07_AUTO_REFRESH_MODE_ENCODE(1) |
1103                 DDR0_07_AREFRESH_ENCODE(0));
1104
1105         mtsdram(DDR0_08, DDR0_08_WRLAT_ENCODE(cas_latency - 1) |
1106                 DDR0_08_TCPD_ENCODE(200) | DDR0_08_DQS_N_EN_ENCODE(0) |
1107                 DDR0_08_DDRII_ENCODE(1));
1108
1109         mtsdram(DDR0_09, DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(0x00) |
1110                 DDR0_09_RTT_0_ENCODE(0x1) |
1111                 DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(0x1D) |
1112                 DDR0_09_WR_DQS_SHIFT_ENCODE(DQS_OUT_SHIFT - 0x20));
1113
1114         program_ddr0_10(dimm_ranks, ranks);
1115
1116         program_ddr0_11(sdram_freq);
1117
1118         mtsdram(DDR0_12, DDR0_12_TCKE_ENCODE(3));
1119
1120         mtsdram(DDR0_14, DDR0_14_DLL_BYPASS_MODE_ENCODE(0) |
1121                 DDR0_14_REDUC_ENCODE(width <= 40 ? 1 : 0) |
1122                 DDR0_14_REG_DIMM_ENABLE_ENCODE(0));
1123
1124         mtsdram(DDR0_17, DDR0_17_DLL_DQS_DELAY_0_ENCODE(DLL_DQS_DELAY));
1125
1126         mtsdram(DDR0_18, DDR0_18_DLL_DQS_DELAY_4_ENCODE(DLL_DQS_DELAY) |
1127                 DDR0_18_DLL_DQS_DELAY_3_ENCODE(DLL_DQS_DELAY) |
1128                 DDR0_18_DLL_DQS_DELAY_2_ENCODE(DLL_DQS_DELAY) |
1129                 DDR0_18_DLL_DQS_DELAY_1_ENCODE(DLL_DQS_DELAY));
1130
1131         mtsdram(DDR0_19, DDR0_19_DLL_DQS_DELAY_8_ENCODE(DLL_DQS_DELAY) |
1132                 DDR0_19_DLL_DQS_DELAY_7_ENCODE(DLL_DQS_DELAY) |
1133                 DDR0_19_DLL_DQS_DELAY_6_ENCODE(DLL_DQS_DELAY) |
1134                 DDR0_19_DLL_DQS_DELAY_5_ENCODE(DLL_DQS_DELAY));
1135
1136         mtsdram(DDR0_20, DDR0_20_DLL_DQS_BYPASS_3_ENCODE(DLL_DQS_BYPASS) |
1137                 DDR0_20_DLL_DQS_BYPASS_2_ENCODE(DLL_DQS_BYPASS) |
1138                 DDR0_20_DLL_DQS_BYPASS_1_ENCODE(DLL_DQS_BYPASS) |
1139                 DDR0_20_DLL_DQS_BYPASS_0_ENCODE(DLL_DQS_BYPASS));
1140
1141         mtsdram(DDR0_21, DDR0_21_DLL_DQS_BYPASS_7_ENCODE(DLL_DQS_BYPASS) |
1142                 DDR0_21_DLL_DQS_BYPASS_6_ENCODE(DLL_DQS_BYPASS) |
1143                 DDR0_21_DLL_DQS_BYPASS_5_ENCODE(DLL_DQS_BYPASS) |
1144                 DDR0_21_DLL_DQS_BYPASS_4_ENCODE(DLL_DQS_BYPASS));
1145
1146         program_ddr0_22(dimm_ranks, iic0_dimm_addr, num_dimm_banks, width);
1147
1148         mtsdram(DDR0_23, DDR0_23_ODT_RD_MAP_CS0_ENCODE(0x0) |
1149                 DDR0_23_FWC_ENCODE(0));
1150
1151         program_ddr0_24(ranks);
1152
1153         program_ddr0_26(sdram_freq);
1154
1155         program_ddr0_27(sdram_freq);
1156
1157         mtsdram(DDR0_28, DDR0_28_EMRS3_DATA_ENCODE(0x0000) |
1158                 DDR0_28_EMRS2_DATA_ENCODE(0x0000));
1159
1160         mtsdram(DDR0_31, DDR0_31_XOR_CHECK_BITS_ENCODE(0x0000));
1161
1162         mtsdram(DDR0_42, DDR0_42_ADDR_PINS_ENCODE(14 - rows) |
1163                 DDR0_42_CASLAT_LIN_GATE_ENCODE(2 * cas_latency));
1164
1165         program_ddr0_43(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq,
1166                         cols, banks);
1167
1168         program_ddr0_44(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
1169
1170         denali_sdram_register_dump();
1171
1172         dram_size = (width >= 64) ? 8 : 4;
1173         dram_size *= 1 << cols;
1174         dram_size *= banks;
1175         dram_size *= 1 << rows;
1176         dram_size *= ranks;
1177         debug("dram_size = %lu\n", dram_size);
1178
1179         /* Start the SDRAM controler */
1180         mtsdram(DDR0_02, DDR0_02_START_ENCODE(1));
1181         denali_wait_for_dlllock();
1182
1183 #if defined(CONFIG_DDR_DATA_EYE)
1184         /*
1185          * Map the first 1 MiB of memory in the TLB, and perform the data eye
1186          * search.
1187          */
1188         program_tlb(0, CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE, TLB_WORD2_I_ENABLE);
1189         denali_core_search_data_eye();
1190         denali_sdram_register_dump();
1191         remove_tlb(CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE);
1192 #endif
1193
1194 #if defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC)
1195         program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, 0);
1196         sync();
1197         /* Zero the memory */
1198         debug("Zeroing SDRAM...");
1199 #if defined(CONFIG_SYS_MEM_TOP_HIDE)
1200         dcbz_area(CONFIG_SYS_SDRAM_BASE, dram_size - CONFIG_SYS_MEM_TOP_HIDE);
1201 #else
1202 #error Please define CONFIG_SYS_MEM_TOP_HIDE (see README) in your board config file
1203 #endif
1204         /* Write modified dcache lines back to memory */
1205         clean_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + dram_size - CONFIG_SYS_MEM_TOP_HIDE);
1206         debug("Completed\n");
1207         sync();
1208         remove_tlb(CONFIG_SYS_SDRAM_BASE, dram_size);
1209
1210 #if defined(CONFIG_DDR_ECC)
1211         /*
1212          * If ECC is enabled, clear and enable interrupts
1213          */
1214         if (is_ecc_enabled()) {
1215                 u32 val;
1216
1217                 sync();
1218                 /* Clear error status */
1219                 mfsdram(DDR0_00, val);
1220                 mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
1221                 /* Set 'int_mask' parameter to functionnal value */
1222                 mfsdram(DDR0_01, val);
1223                 mtsdram(DDR0_01, (val & ~DDR0_01_INT_MASK_MASK) |
1224                         DDR0_01_INT_MASK_ALL_OFF);
1225 #if defined(CONFIG_DDR_DATA_EYE)
1226                 /*
1227                  * Running denali_core_search_data_eye() when ECC is enabled
1228                  * causes non-ECC machine checks.  This clears them.
1229                  */
1230                 print_mcsr();
1231                 mtspr(SPRN_MCSR, mfspr(SPRN_MCSR));
1232                 print_mcsr();
1233 #endif
1234                 sync();
1235         }
1236 #endif /* defined(CONFIG_DDR_ECC) */
1237 #endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */
1238
1239         program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE);
1240         return dram_size;
1241 }
1242
1243 void board_add_ram_info(int use_default)
1244 {
1245         u32 val;
1246
1247         printf(" (ECC");
1248         if (!is_ecc_enabled()) {
1249                 printf(" not");
1250         }
1251         printf(" enabled, %ld MHz", (2 * get_bus_freq(0)) / 1000000);
1252
1253         mfsdram(DDR0_03, val);
1254         printf(", CL%d)", DDR0_03_CASLAT_LIN_DECODE(val) >> 1);
1255 }
1256 #endif /* CONFIG_SPD_EEPROM */