arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c

   1 /*
   2  * arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
   3  * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
   4  * DDR2 controller (non Denali Core). Those currently are:
   5  *
   6  * 405:         405EX(r)
   7  * 440/460:     440SP/440SPe/460EX/460GT
   8  *
   9  * Copyright (c) 2008 Nuovation System Designs, LLC
  10  *   Grant Erickson <gerickson@nuovations.com>
  11
  12  * (C) Copyright 2007-2009
  13  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  14  *
  15  * COPYRIGHT   AMCC   CORPORATION 2004
  16  *
  17  * See file CREDITS for list of people who contributed to this
  18  * project.
  19  *
  20  * This program is free software; you can redistribute it and/or
  21  * modify it under the terms of the GNU General Public License as
  22  * published by the Free Software Foundation; either version 2 of
  23  * the License, or (at your option) any later version.
  24  *
  25  * This program is distributed in the hope that it will be useful,
  26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  28  * GNU General Public License for more details.
  29  *
  30  * You should have received a copy of the GNU General Public License
  31  * along with this program; if not, write to the Free Software
  32  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  33  * MA 02111-1307 USA
  34  *
  35  */
  36
  37 /* define DEBUG for debugging output (obviously ;-)) */
  38 #if 0
  39 #define DEBUG
  40 #endif
  41
  42 #include <common.h>
  43 #include <command.h>
  44 #include <asm/ppc4xx.h>
  45 #include <i2c.h>
  46 #include <asm/io.h>
  47 #include <asm/processor.h>
  48 #include <asm/mmu.h>
  49 #include <asm/cache.h>
  50
  51 #include "ecc.h"
  52
  53 #define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic)                         \
  54         do {                                                            \
  55                 u32 data;                                               \
  56                 mfsdram(SDRAM_##mnemonic, data);                        \
  57                 printf("%20s[%02x] = 0x%08X\n",                         \
  58                        "SDRAM_" #mnemonic, SDRAM_##mnemonic, data);     \
  59         } while (0)
  60
  61 #define PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(mnemonic)                      \
  62         do {                                                            \
  63                 u32 data;                                               \
  64                 data = mfdcr(SDRAM_##mnemonic);                         \
  65                 printf("%20s[%02x] = 0x%08X\n",                         \
  66                        "SDRAM_" #mnemonic, SDRAM_##mnemonic, data);     \
  67         } while (0)
  68
  69 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
  70 static void update_rdcc(void)
  71 {
  72         u32 val;
  73
  74         /*
  75          * Complete RDSS configuration as mentioned on page 7 of the AMCC
  76          * PowerPC440SP/SPe DDR2 application note:
  77          * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
  78          *
  79          * Or item #10 "10. Complete RDSS configuration" in chapter
  80          * "22.2.9 SDRAM Initialization" of AMCC PPC460EX/EXr/GT users
  81          * manual.
  82          */
  83         mfsdram(SDRAM_RTSR, val);
  84         if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
  85                 mfsdram(SDRAM_RDCC, val);
  86                 if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
  87                         val += 0x40000000;
  88                         mtsdram(SDRAM_RDCC, val);
  89                 }
  90         }
  91 }
  92 #endif
  93
  94 #if defined(CONFIG_440)
  95 /*
  96  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2
  97  * memory region. Right now the cache should still be disabled in U-Boot
  98  * because of the EMAC driver, that need its buffer descriptor to be located
  99  * in non cached memory.
 100  *
 101  * If at some time this restriction doesn't apply anymore, just define
 102  * CONFIG_4xx_DCACHE in the board config file and this code should setup
 103  * everything correctly.
 104  */
 105 #ifdef CONFIG_4xx_DCACHE
 106 /* enable caching on SDRAM */
 107 #define MY_TLB_WORD2_I_ENABLE           0
 108 #else
 109 /* disable caching on SDRAM */
 110 #define MY_TLB_WORD2_I_ENABLE           TLB_WORD2_I_ENABLE
 111 #endif /* CONFIG_4xx_DCACHE */
 112
 113 void dcbz_area(u32 start_address, u32 num_bytes);
 114 #endif /* CONFIG_440 */
 115
 116 #define MAXRANKS        4
 117 #define MAXBXCF         4
 118
 119 #define MULDIV64(m1, m2, d)     (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
 120
 121 #if !defined(CONFIG_NAND_SPL)
 122 /*-----------------------------------------------------------------------------+
 123  * sdram_memsize
 124  *-----------------------------------------------------------------------------*/
 125 phys_size_t sdram_memsize(void)
 126 {
 127         phys_size_t mem_size;
 128         unsigned long mcopt2;
 129         unsigned long mcstat;
 130         unsigned long mb0cf;
 131         unsigned long sdsz;
 132         unsigned long i;
 133
 134         mem_size = 0;
 135
 136         mfsdram(SDRAM_MCOPT2, mcopt2);
 137         mfsdram(SDRAM_MCSTAT, mcstat);
 138
 139         /* DDR controller must be enabled and not in self-refresh. */
 140         /* Otherwise memsize is zero. */
 141         if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
 142             && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
 143             && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
 144                 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
 145                 for (i = 0; i < MAXBXCF; i++) {
 146                         mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
 147                         /* Banks enabled */
 148                         if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
 149 #if defined(CONFIG_440)
 150                                 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
 151 #else
 152                                 sdsz = mb0cf & SDRAM_RXBAS_SDSZ_MASK;
 153 #endif
 154                                 switch(sdsz) {
 155                                 case SDRAM_RXBAS_SDSZ_8:
 156                                         mem_size+=8;
 157                                         break;
 158                                 case SDRAM_RXBAS_SDSZ_16:
 159                                         mem_size+=16;
 160                                         break;
 161                                 case SDRAM_RXBAS_SDSZ_32:
 162                                         mem_size+=32;
 163                                         break;
 164                                 case SDRAM_RXBAS_SDSZ_64:
 165                                         mem_size+=64;
 166                                         break;
 167                                 case SDRAM_RXBAS_SDSZ_128:
 168                                         mem_size+=128;
 169                                         break;
 170                                 case SDRAM_RXBAS_SDSZ_256:
 171                                         mem_size+=256;
 172                                         break;
 173                                 case SDRAM_RXBAS_SDSZ_512:
 174                                         mem_size+=512;
 175                                         break;
 176                                 case SDRAM_RXBAS_SDSZ_1024:
 177                                         mem_size+=1024;
 178                                         break;
 179                                 case SDRAM_RXBAS_SDSZ_2048:
 180                                         mem_size+=2048;
 181                                         break;
 182                                 case SDRAM_RXBAS_SDSZ_4096:
 183                                         mem_size+=4096;
 184                                         break;
 185                                 default:
 186                                         printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n"
 187                                                , sdsz);
 188                                         mem_size=0;
 189                                         break;
 190                                 }
 191                         }
 192                 }
 193         }
 194
 195         return mem_size << 20;
 196 }
 197
 198 /*-----------------------------------------------------------------------------+
 199  * is_ecc_enabled
 200  *-----------------------------------------------------------------------------*/
 201 static unsigned long is_ecc_enabled(void)
 202 {
 203         unsigned long val;
 204
 205         mfsdram(SDRAM_MCOPT1, val);
 206
 207         return SDRAM_MCOPT1_MCHK_CHK_DECODE(val);
 208 }
 209
 210 /*-----------------------------------------------------------------------------+
 211  * board_add_ram_info
 212  *-----------------------------------------------------------------------------*/
 213 void board_add_ram_info(int use_default)
 214 {
 215         PPC4xx_SYS_INFO board_cfg;
 216         u32 val;
 217
 218         if (is_ecc_enabled())
 219                 puts(" (ECC");
 220         else
 221                 puts(" (ECC not");
 222
 223         get_sys_info(&board_cfg);
 224
 225 #if defined(CONFIG_405EX)
 226         val = board_cfg.freqPLB;
 227 #else
 228         mfsdr(SDR0_DDR0, val);
 229         val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
 230 #endif
 231         printf(" enabled, %d MHz", (val * 2) / 1000000);
 232
 233         mfsdram(SDRAM_MMODE, val);
 234         val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
 235         printf(", CL%d)", val);
 236 }
 237 #endif /* !CONFIG_NAND_SPL */
 238
 239 #if defined(CONFIG_SPD_EEPROM)
 240
 241 /*-----------------------------------------------------------------------------+
 242  * Defines
 243  *-----------------------------------------------------------------------------*/
 244 #define SDRAM_DDR1      1
 245 #define SDRAM_DDR2      2
 246 #define SDRAM_NONE      0
 247
 248 #define MAXDIMMS        2
 249 #define MAX_SPD_BYTES   256   /* Max number of bytes on the DIMM's SPD EEPROM */
 250
 251 #define ONE_BILLION     1000000000
 252
 253 #define CMD_NOP         (7 << 19)
 254 #define CMD_PRECHARGE   (2 << 19)
 255 #define CMD_REFRESH     (1 << 19)
 256 #define CMD_EMR         (0 << 19)
 257 #define CMD_READ        (5 << 19)
 258 #define CMD_WRITE       (4 << 19)
 259
 260 #define SELECT_MR       (0 << 16)
 261 #define SELECT_EMR      (1 << 16)
 262 #define SELECT_EMR2     (2 << 16)
 263 #define SELECT_EMR3     (3 << 16)
 264
 265 /* MR */
 266 #define DLL_RESET       0x00000100
 267
 268 #define WRITE_RECOV_2   (1 << 9)
 269 #define WRITE_RECOV_3   (2 << 9)
 270 #define WRITE_RECOV_4   (3 << 9)
 271 #define WRITE_RECOV_5   (4 << 9)
 272 #define WRITE_RECOV_6   (5 << 9)
 273
 274 #define BURST_LEN_4     0x00000002
 275
 276 /* EMR */
 277 #define ODT_0_OHM       0x00000000
 278 #define ODT_50_OHM      0x00000044
 279 #define ODT_75_OHM      0x00000004
 280 #define ODT_150_OHM     0x00000040
 281
 282 #define ODS_FULL        0x00000000
 283 #define ODS_REDUCED     0x00000002
 284 #define OCD_CALIB_DEF   0x00000380
 285
 286 /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
 287 #define ODT_EB0R        (0x80000000 >> 8)
 288 #define ODT_EB0W        (0x80000000 >> 7)
 289 #define CALC_ODT_R(n)   (ODT_EB0R << (n << 1))
 290 #define CALC_ODT_W(n)   (ODT_EB0W << (n << 1))
 291 #define CALC_ODT_RW(n)  (CALC_ODT_R(n) | CALC_ODT_W(n))
 292
 293 /* Defines for the Read Cycle Delay test */
 294 #define NUMMEMTESTS     8
 295 #define NUMMEMWORDS     8
 296 #define NUMLOOPS        64              /* memory test loops */
 297
 298 /*
 299  * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
 300  * To support such configurations, we "only" map the first 2GB via the TLB's. We
 301  * need some free virtual address space for the remaining peripherals like, SoC
 302  * devices, FLASH etc.
 303  *
 304  * Note that ECC is currently not supported on configurations with more than 2GB
 305  * SDRAM. This is because we only map the first 2GB on such systems, and therefore
 306  * the ECC parity byte of the remaining area can't be written.
 307  */
 308
 309 /*
 310  * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
 311  */
 312 void __spd_ddr_init_hang (void)
 313 {
 314         hang ();
 315 }
 316 void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
 317
 318 /*
 319  * To provide an interface for board specific config values in this common
 320  * DDR setup code, we implement he "weak" default functions here. They return
 321  * the default value back to the caller.
 322  *
 323  * Please see include/configs/yucca.h for an example fora board specific
 324  * implementation.
 325  */
 326 u32 __ddr_wrdtr(u32 default_val)
 327 {
 328         return default_val;
 329 }
 330 u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
 331
 332 u32 __ddr_clktr(u32 default_val)
 333 {
 334         return default_val;
 335 }
 336 u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
 337
 338
 339 /* Private Structure Definitions */
 340
 341 /* enum only to ease code for cas latency setting */
 342 typedef enum ddr_cas_id {
 343         DDR_CAS_2      = 20,
 344         DDR_CAS_2_5    = 25,
 345         DDR_CAS_3      = 30,
 346         DDR_CAS_4      = 40,
 347         DDR_CAS_5      = 50
 348 } ddr_cas_id_t;
 349
 350 /*-----------------------------------------------------------------------------+
 351  * Prototypes
 352  *-----------------------------------------------------------------------------*/
 353 static void get_spd_info(unsigned long *dimm_populated,
 354                          unsigned char *iic0_dimm_addr,
 355                          unsigned long num_dimm_banks);
 356 static void check_mem_type(unsigned long *dimm_populated,
 357                            unsigned char *iic0_dimm_addr,
 358                            unsigned long num_dimm_banks);
 359 static void check_frequency(unsigned long *dimm_populated,
 360                             unsigned char *iic0_dimm_addr,
 361                             unsigned long num_dimm_banks);
 362 static void check_rank_number(unsigned long *dimm_populated,
 363                               unsigned char *iic0_dimm_addr,
 364                               unsigned long num_dimm_banks);
 365 static void check_voltage_type(unsigned long *dimm_populated,
 366                                unsigned char *iic0_dimm_addr,
 367                                unsigned long num_dimm_banks);
 368 static void program_memory_queue(unsigned long *dimm_populated,
 369                                  unsigned char *iic0_dimm_addr,
 370                                  unsigned long num_dimm_banks);
 371 static void program_codt(unsigned long *dimm_populated,
 372                          unsigned char *iic0_dimm_addr,
 373                          unsigned long num_dimm_banks);
 374 static void program_mode(unsigned long *dimm_populated,
 375                          unsigned char *iic0_dimm_addr,
 376                          unsigned long num_dimm_banks,
 377                          ddr_cas_id_t *selected_cas,
 378                          int *write_recovery);
 379 static void program_tr(unsigned long *dimm_populated,
 380                        unsigned char *iic0_dimm_addr,
 381                        unsigned long num_dimm_banks);
 382 static void program_rtr(unsigned long *dimm_populated,
 383                         unsigned char *iic0_dimm_addr,
 384                         unsigned long num_dimm_banks);
 385 static void program_bxcf(unsigned long *dimm_populated,
 386                          unsigned char *iic0_dimm_addr,
 387                          unsigned long num_dimm_banks);
 388 static void program_copt1(unsigned long *dimm_populated,
 389                           unsigned char *iic0_dimm_addr,
 390                           unsigned long num_dimm_banks);
 391 static void program_initplr(unsigned long *dimm_populated,
 392                             unsigned char *iic0_dimm_addr,
 393                             unsigned long num_dimm_banks,
 394                             ddr_cas_id_t selected_cas,
 395                             int write_recovery);
 396 #ifdef CONFIG_DDR_ECC
 397 static void program_ecc(unsigned long *dimm_populated,
 398                         unsigned char *iic0_dimm_addr,
 399                         unsigned long num_dimm_banks,
 400                         unsigned long tlb_word2_i_value);
 401 #endif
 402 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
 403 static void program_DQS_calibration(unsigned long *dimm_populated,
 404                                 unsigned char *iic0_dimm_addr,
 405                                 unsigned long num_dimm_banks);
 406 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
 407 static void     test(void);
 408 #else
 409 static void     DQS_calibration_process(void);
 410 #endif
 411 #endif
 412
 413 static unsigned char spd_read(uchar chip, uint addr)
 414 {
 415         unsigned char data[2];
 416
 417         if (i2c_probe(chip) == 0)
 418                 if (i2c_read(chip, addr, 1, data, 1) == 0)
 419                         return data[0];
 420
 421         return 0;
 422 }
 423
 424 /*-----------------------------------------------------------------------------+
 425  * initdram.  Initializes the 440SP Memory Queue and DDR SDRAM controller.
 426  * Note: This routine runs from flash with a stack set up in the chip's
 427  * sram space.  It is important that the routine does not require .sbss, .bss or
 428  * .data sections.  It also cannot call routines that require these sections.
 429  *-----------------------------------------------------------------------------*/
 430 /*-----------------------------------------------------------------------------
 431  * Function:     initdram
 432  * Description:  Configures SDRAM memory banks for DDR operation.
 433  *               Auto Memory Configuration option reads the DDR SDRAM EEPROMs
 434  *               via the IIC bus and then configures the DDR SDRAM memory
 435  *               banks appropriately. If Auto Memory Configuration is
 436  *               not used, it is assumed that no DIMM is plugged
 437  *-----------------------------------------------------------------------------*/
 438 phys_size_t initdram(int board_type)
 439 {
 440         unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 441         unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE};
 442         unsigned long num_dimm_banks;           /* on board dimm banks */
 443         unsigned long val;
 444         ddr_cas_id_t selected_cas = DDR_CAS_5;  /* preset to silence compiler */
 445         int write_recovery;
 446         phys_size_t dram_size = 0;
 447
 448         num_dimm_banks = sizeof(iic0_dimm_addr);
 449
 450         /*------------------------------------------------------------------
 451          * Reset the DDR-SDRAM controller.
 452          *-----------------------------------------------------------------*/
 453         mtsdr(SDR0_SRST, SDR0_SRST0_DMC);
 454         mtsdr(SDR0_SRST, 0x00000000);
 455
 456         /*
 457          * Make sure I2C controller is initialized
 458          * before continuing.
 459          */
 460
 461         /* switch to correct I2C bus */
 462         i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
 463
 464         /*------------------------------------------------------------------
 465          * Clear out the serial presence detect buffers.
 466          * Perform IIC reads from the dimm.  Fill in the spds.
 467          * Check to see if the dimm slots are populated
 468          *-----------------------------------------------------------------*/
 469         get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 470
 471         /*------------------------------------------------------------------
 472          * Check the memory type for the dimms plugged.
 473          *-----------------------------------------------------------------*/
 474         check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 475
 476         /*------------------------------------------------------------------
 477          * Check the frequency supported for the dimms plugged.
 478          *-----------------------------------------------------------------*/
 479         check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 480
 481         /*------------------------------------------------------------------
 482          * Check the total rank number.
 483          *-----------------------------------------------------------------*/
 484         check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 485
 486         /*------------------------------------------------------------------
 487          * Check the voltage type for the dimms plugged.
 488          *-----------------------------------------------------------------*/
 489         check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 490
 491         /*------------------------------------------------------------------
 492          * Program SDRAM controller options 2 register
 493          * Except Enabling of the memory controller.
 494          *-----------------------------------------------------------------*/
 495         mfsdram(SDRAM_MCOPT2, val);
 496         mtsdram(SDRAM_MCOPT2,
 497                 (val &
 498                  ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
 499                    SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
 500                    SDRAM_MCOPT2_ISIE_MASK))
 501                 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
 502                    SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
 503                    SDRAM_MCOPT2_ISIE_ENABLE));
 504
 505         /*------------------------------------------------------------------
 506          * Program SDRAM controller options 1 register
 507          * Note: Does not enable the memory controller.
 508          *-----------------------------------------------------------------*/
 509         program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 510
 511         /*------------------------------------------------------------------
 512          * Set the SDRAM Controller On Die Termination Register
 513          *-----------------------------------------------------------------*/
 514         program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 515
 516         /*------------------------------------------------------------------
 517          * Program SDRAM refresh register.
 518          *-----------------------------------------------------------------*/
 519         program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 520
 521         /*------------------------------------------------------------------
 522          * Program SDRAM mode register.
 523          *-----------------------------------------------------------------*/
 524         program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 525                      &selected_cas, &write_recovery);
 526
 527         /*------------------------------------------------------------------
 528          * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
 529          *-----------------------------------------------------------------*/
 530         mfsdram(SDRAM_WRDTR, val);
 531         mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
 532                 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
 533
 534         /*------------------------------------------------------------------
 535          * Set the SDRAM Clock Timing Register
 536          *-----------------------------------------------------------------*/
 537         mfsdram(SDRAM_CLKTR, val);
 538         mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
 539                 ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
 540
 541         /*------------------------------------------------------------------
 542          * Program the BxCF registers.
 543          *-----------------------------------------------------------------*/
 544         program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 545
 546         /*------------------------------------------------------------------
 547          * Program SDRAM timing registers.
 548          *-----------------------------------------------------------------*/
 549         program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 550
 551         /*------------------------------------------------------------------
 552          * Set the Extended Mode register
 553          *-----------------------------------------------------------------*/
 554         mfsdram(SDRAM_MEMODE, val);
 555         mtsdram(SDRAM_MEMODE,
 556                 (val & ~(SDRAM_MEMODE_DIC_MASK  | SDRAM_MEMODE_DLL_MASK |
 557                          SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
 558                 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
 559                  | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
 560
 561         /*------------------------------------------------------------------
 562          * Program Initialization preload registers.
 563          *-----------------------------------------------------------------*/
 564         program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 565                         selected_cas, write_recovery);
 566
 567         /*------------------------------------------------------------------
 568          * Delay to ensure 200usec have elapsed since reset.
 569          *-----------------------------------------------------------------*/
 570         udelay(400);
 571
 572         /*------------------------------------------------------------------
 573          * Set the memory queue core base addr.
 574          *-----------------------------------------------------------------*/
 575         program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 576
 577         /*------------------------------------------------------------------
 578          * Program SDRAM controller options 2 register
 579          * Enable the memory controller.
 580          *-----------------------------------------------------------------*/
 581         mfsdram(SDRAM_MCOPT2, val);
 582         mtsdram(SDRAM_MCOPT2,
 583                 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
 584                          SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
 585                          SDRAM_MCOPT2_IPTR_EXECUTE);
 586
 587         /*------------------------------------------------------------------
 588          * Wait for IPTR_EXECUTE init sequence to complete.
 589          *-----------------------------------------------------------------*/
 590         do {
 591                 mfsdram(SDRAM_MCSTAT, val);
 592         } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
 593
 594         /* enable the controller only after init sequence completes */
 595         mfsdram(SDRAM_MCOPT2, val);
 596         mtsdram(SDRAM_MCOPT2, (val | SDRAM_MCOPT2_DCEN_ENABLE));
 597
 598         /* Make sure delay-line calibration is done before proceeding */
 599         do {
 600                 mfsdram(SDRAM_DLCR, val);
 601         } while (!(val & SDRAM_DLCR_DLCS_COMPLETE));
 602
 603         /* get installed memory size */
 604         dram_size = sdram_memsize();
 605
 606         /*
 607          * Limit size to 2GB
 608          */
 609         if (dram_size > CONFIG_MAX_MEM_MAPPED)
 610                 dram_size = CONFIG_MAX_MEM_MAPPED;
 611
 612         /* and program tlb entries for this size (dynamic) */
 613
 614         /*
 615          * Program TLB entries with caches enabled, for best performace
 616          * while auto-calibrating and ECC generation
 617          */
 618         program_tlb(0, 0, dram_size, 0);
 619
 620         /*------------------------------------------------------------------
 621          * DQS calibration.
 622          *-----------------------------------------------------------------*/
 623 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
 624         DQS_autocalibration();
 625 #else
 626         program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 627 #endif
 628         /*
 629          * Now complete RDSS configuration as mentioned on page 7 of the AMCC
 630          * PowerPC440SP/SPe DDR2 application note:
 631          * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
 632          */
 633         update_rdcc();
 634
 635 #ifdef CONFIG_DDR_ECC
 636         /*------------------------------------------------------------------
 637          * If ecc is enabled, initialize the parity bits.
 638          *-----------------------------------------------------------------*/
 639         program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
 640 #endif
 641
 642         /*
 643          * Flush the dcache before removing the TLB with caches
 644          * enabled. Otherwise this might lead to problems later on,
 645          * e.g. while booting Linux (as seen on ICON-440SPe).
 646          */
 647         flush_dcache();
 648
 649         /*
 650          * Now after initialization (auto-calibration and ECC generation)
 651          * remove the TLB entries with caches enabled and program again with
 652          * desired cache functionality
 653          */
 654         remove_tlb(0, dram_size);
 655         program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
 656
 657         ppc4xx_ibm_ddr2_register_dump();
 658
 659         /*
 660          * Clear potential errors resulting from auto-calibration.
 661          * If not done, then we could get an interrupt later on when
 662          * exceptions are enabled.
 663          */
 664         set_mcsr(get_mcsr());
 665
 666         return sdram_memsize();
 667 }
 668
 669 static void get_spd_info(unsigned long *dimm_populated,
 670                          unsigned char *iic0_dimm_addr,
 671                          unsigned long num_dimm_banks)
 672 {
 673         unsigned long dimm_num;
 674         unsigned long dimm_found;
 675         unsigned char num_of_bytes;
 676         unsigned char total_size;
 677
 678         dimm_found = false;
 679         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 680                 num_of_bytes = 0;
 681                 total_size = 0;
 682
 683                 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
 684                 debug("\nspd_read(0x%x) returned %d\n",
 685                       iic0_dimm_addr[dimm_num], num_of_bytes);
 686                 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 687                 debug("spd_read(0x%x) returned %d\n",
 688                       iic0_dimm_addr[dimm_num], total_size);
 689
 690                 if ((num_of_bytes != 0) && (total_size != 0)) {
 691                         dimm_populated[dimm_num] = true;
 692                         dimm_found = true;
 693                         debug("DIMM slot %lu: populated\n", dimm_num);
 694                 } else {
 695                         dimm_populated[dimm_num] = false;
 696                         debug("DIMM slot %lu: Not populated\n", dimm_num);
 697                 }
 698         }
 699
 700         if (dimm_found == false) {
 701                 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
 702                 spd_ddr_init_hang ();
 703         }
 704 }
 705
 706
 707 /*------------------------------------------------------------------
 708  * For the memory DIMMs installed, this routine verifies that they
 709  * really are DDR specific DIMMs.
 710  *-----------------------------------------------------------------*/
 711 static void check_mem_type(unsigned long *dimm_populated,
 712                            unsigned char *iic0_dimm_addr,
 713                            unsigned long num_dimm_banks)
 714 {
 715         unsigned long dimm_num;
 716         unsigned long dimm_type;
 717
 718         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 719                 if (dimm_populated[dimm_num] == true) {
 720                         dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
 721                         switch (dimm_type) {
 722                         case 1:
 723                                 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
 724                                        "slot %d.\n", (unsigned int)dimm_num);
 725                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 726                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 727                                 spd_ddr_init_hang ();
 728                                 break;
 729                         case 2:
 730                                 printf("ERROR: EDO DIMM detected in slot %d.\n",
 731                                        (unsigned int)dimm_num);
 732                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 733                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 734                                 spd_ddr_init_hang ();
 735                                 break;
 736                         case 3:
 737                                 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
 738                                        (unsigned int)dimm_num);
 739                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 740                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 741                                 spd_ddr_init_hang ();
 742                                 break;
 743                         case 4:
 744                                 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
 745                                        (unsigned int)dimm_num);
 746                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 747                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 748                                 spd_ddr_init_hang ();
 749                                 break;
 750                         case 5:
 751                                 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
 752                                        (unsigned int)dimm_num);
 753                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 754                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 755                                 spd_ddr_init_hang ();
 756                                 break;
 757                         case 6:
 758                                 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
 759                                        (unsigned int)dimm_num);
 760                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 761                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 762                                 spd_ddr_init_hang ();
 763                                 break;
 764                         case 7:
 765                                 debug("DIMM slot %lu: DDR1 SDRAM detected\n", dimm_num);
 766                                 dimm_populated[dimm_num] = SDRAM_DDR1;
 767                                 break;
 768                         case 8:
 769                                 debug("DIMM slot %lu: DDR2 SDRAM detected\n", dimm_num);
 770                                 dimm_populated[dimm_num] = SDRAM_DDR2;
 771                                 break;
 772                         default:
 773                                 printf("ERROR: Unknown DIMM detected in slot %d.\n",
 774                                        (unsigned int)dimm_num);
 775                                 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
 776                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 777                                 spd_ddr_init_hang ();
 778                                 break;
 779                         }
 780                 }
 781         }
 782         for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
 783                 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
 784                     && (dimm_populated[dimm_num]   != SDRAM_NONE)
 785                     && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
 786                         printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
 787                         spd_ddr_init_hang ();
 788                 }
 789         }
 790 }
 791
 792 /*------------------------------------------------------------------
 793  * For the memory DIMMs installed, this routine verifies that
 794  * frequency previously calculated is supported.
 795  *-----------------------------------------------------------------*/
 796 static void check_frequency(unsigned long *dimm_populated,
 797                             unsigned char *iic0_dimm_addr,
 798                             unsigned long num_dimm_banks)
 799 {
 800         unsigned long dimm_num;
 801         unsigned long tcyc_reg;
 802         unsigned long cycle_time;
 803         unsigned long calc_cycle_time;
 804         unsigned long sdram_freq;
 805         unsigned long sdr_ddrpll;
 806         PPC4xx_SYS_INFO board_cfg;
 807
 808         /*------------------------------------------------------------------
 809          * Get the board configuration info.
 810          *-----------------------------------------------------------------*/
 811         get_sys_info(&board_cfg);
 812
 813         mfsdr(SDR0_DDR0, sdr_ddrpll);
 814         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
 815
 816         /*
 817          * calc_cycle_time is calculated from DDR frequency set by board/chip
 818          * and is expressed in multiple of 10 picoseconds
 819          * to match the way DIMM cycle time is calculated below.
 820          */
 821         calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
 822
 823         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 824                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 825                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
 826                         /*
 827                          * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
 828                          * the higher order nibble (bits 4-7) designates the cycle time
 829                          * to a granularity of 1ns;
 830                          * the value presented by the lower order nibble (bits 0-3)
 831                          * has a granularity of .1ns and is added to the value designated
 832                          * by the higher nibble. In addition, four lines of the lower order
 833                          * nibble are assigned to support +.25,+.33, +.66 and +.75.
 834                          */
 835                          /* Convert from hex to decimal */
 836                         if ((tcyc_reg & 0x0F) == 0x0D)
 837                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
 838                         else if ((tcyc_reg & 0x0F) == 0x0C)
 839                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
 840                         else if ((tcyc_reg & 0x0F) == 0x0B)
 841                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
 842                         else if ((tcyc_reg & 0x0F) == 0x0A)
 843                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
 844                         else
 845                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
 846                                         ((tcyc_reg & 0x0F)*10);
 847                         debug("cycle_time=%lu [10 picoseconds]\n", cycle_time);
 848
 849                         if  (cycle_time > (calc_cycle_time + 10)) {
 850                                 /*
 851                                  * the provided sdram cycle_time is too small
 852                                  * for the available DIMM cycle_time.
 853                                  * The additionnal 100ps is here to accept a small incertainty.
 854                                  */
 855                                 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
 856                                        "slot %d \n while calculated cycle time is %d ps.\n",
 857                                        (unsigned int)(cycle_time*10),
 858                                        (unsigned int)dimm_num,
 859                                        (unsigned int)(calc_cycle_time*10));
 860                                 printf("Replace the DIMM, or change DDR frequency via "
 861                                        "strapping bits.\n\n");
 862                                 spd_ddr_init_hang ();
 863                         }
 864                 }
 865         }
 866 }
 867
 868 /*------------------------------------------------------------------
 869  * For the memory DIMMs installed, this routine verifies two
 870  * ranks/banks maximum are availables.
 871  *-----------------------------------------------------------------*/
 872 static void check_rank_number(unsigned long *dimm_populated,
 873                               unsigned char *iic0_dimm_addr,
 874                               unsigned long num_dimm_banks)
 875 {
 876         unsigned long dimm_num;
 877         unsigned long dimm_rank;
 878         unsigned long total_rank = 0;
 879
 880         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 881                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 882                         dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
 883                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
 884                                 dimm_rank = (dimm_rank & 0x0F) +1;
 885                         else
 886                                 dimm_rank = dimm_rank & 0x0F;
 887
 888
 889                         if (dimm_rank > MAXRANKS) {
 890                                 printf("ERROR: DRAM DIMM detected with %lu ranks in "
 891                                        "slot %lu is not supported.\n", dimm_rank, dimm_num);
 892                                 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 893                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 894                                 spd_ddr_init_hang ();
 895                         } else
 896                                 total_rank += dimm_rank;
 897                 }
 898                 if (total_rank > MAXRANKS) {
 899                         printf("ERROR: DRAM DIMM detected with a total of %d ranks "
 900                                "for all slots.\n", (unsigned int)total_rank);
 901                         printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 902                         printf("Remove one of the DIMM modules.\n\n");
 903                         spd_ddr_init_hang ();
 904                 }
 905         }
 906 }
 907
 908 /*------------------------------------------------------------------
 909  * only support 2.5V modules.
 910  * This routine verifies this.
 911  *-----------------------------------------------------------------*/
 912 static void check_voltage_type(unsigned long *dimm_populated,
 913                                unsigned char *iic0_dimm_addr,
 914                                unsigned long num_dimm_banks)
 915 {
 916         unsigned long dimm_num;
 917         unsigned long voltage_type;
 918
 919         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 920                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 921                         voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
 922                         switch (voltage_type) {
 923                         case 0x00:
 924                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 925                                 printf("This DIMM is 5.0 Volt/TTL.\n");
 926                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 927                                        (unsigned int)dimm_num);
 928                                 spd_ddr_init_hang ();
 929                                 break;
 930                         case 0x01:
 931                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 932                                 printf("This DIMM is LVTTL.\n");
 933                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 934                                        (unsigned int)dimm_num);
 935                                 spd_ddr_init_hang ();
 936                                 break;
 937                         case 0x02:
 938                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 939                                 printf("This DIMM is 1.5 Volt.\n");
 940                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 941                                        (unsigned int)dimm_num);
 942                                 spd_ddr_init_hang ();
 943                                 break;
 944                         case 0x03:
 945                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 946                                 printf("This DIMM is 3.3 Volt/TTL.\n");
 947                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 948                                        (unsigned int)dimm_num);
 949                                 spd_ddr_init_hang ();
 950                                 break;
 951                         case 0x04:
 952                                 /* 2.5 Voltage only for DDR1 */
 953                                 break;
 954                         case 0x05:
 955                                 /* 1.8 Voltage only for DDR2 */
 956                                 break;
 957                         default:
 958                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 959                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 960                                        (unsigned int)dimm_num);
 961                                 spd_ddr_init_hang ();
 962                                 break;
 963                         }
 964                 }
 965         }
 966 }
 967
 968 /*-----------------------------------------------------------------------------+
 969  * program_copt1.
 970  *-----------------------------------------------------------------------------*/
 971 static void program_copt1(unsigned long *dimm_populated,
 972                           unsigned char *iic0_dimm_addr,
 973                           unsigned long num_dimm_banks)
 974 {
 975         unsigned long dimm_num;
 976         unsigned long mcopt1;
 977         unsigned long ecc_enabled;
 978         unsigned long ecc = 0;
 979         unsigned long data_width = 0;
 980         unsigned long dimm_32bit;
 981         unsigned long dimm_64bit;
 982         unsigned long registered = 0;
 983         unsigned long attribute = 0;
 984         unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
 985         unsigned long bankcount;
 986         unsigned long val;
 987
 988 #ifdef CONFIG_DDR_ECC
 989         ecc_enabled = true;
 990 #else
 991         ecc_enabled = false;
 992 #endif
 993         dimm_32bit = false;
 994         dimm_64bit = false;
 995         buf0 = false;
 996         buf1 = false;
 997
 998         /*------------------------------------------------------------------
 999          * Set memory controller options reg 1, SDRAM_MCOPT1.
1000          *-----------------------------------------------------------------*/
1001         mfsdram(SDRAM_MCOPT1, val);
1002         mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
1003                          SDRAM_MCOPT1_PMU_MASK  | SDRAM_MCOPT1_DMWD_MASK |
1004                          SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
1005                          SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
1006                          SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
1007                          SDRAM_MCOPT1_DREF_MASK);
1008
1009         mcopt1 |= SDRAM_MCOPT1_QDEP;
1010         mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
1011         mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
1012         mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
1013         mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
1014         mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
1015
1016         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1017                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1018                         /* test ecc support */
1019                         ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
1020                         if (ecc != 0x02) /* ecc not supported */
1021                                 ecc_enabled = false;
1022
1023                         /* test bank count */
1024                         bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
1025                         if (bankcount == 0x04) /* bank count = 4 */
1026                                 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
1027                         else /* bank count = 8 */
1028                                 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
1029
1030                         /* test for buffered/unbuffered, registered, differential clocks */
1031                         registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
1032                         attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
1033
1034                         /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
1035                         if (dimm_num == 0) {
1036                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1037                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1038                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1039                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1040                                 if (registered == 1) { /* DDR2 always buffered */
1041                                         /* TODO: what about above  comments ? */
1042                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
1043                                         buf0 = true;
1044                                 } else {
1045                                         /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
1046                                         if ((attribute & 0x02) == 0x00) {
1047                                                 /* buffered not supported */
1048                                                 buf0 = false;
1049                                         } else {
1050                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
1051                                                 buf0 = true;
1052                                         }
1053                                 }
1054                         }
1055                         else if (dimm_num == 1) {
1056                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1057                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1058                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1059                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1060                                 if (registered == 1) {
1061                                         /* DDR2 always buffered */
1062                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
1063                                         buf1 = true;
1064                                 } else {
1065                                         if ((attribute & 0x02) == 0x00) {
1066                                                 /* buffered not supported */
1067                                                 buf1 = false;
1068                                         } else {
1069                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
1070                                                 buf1 = true;
1071                                         }
1072                                 }
1073                         }
1074
1075                         /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
1076                         data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
1077                                 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
1078
1079                         switch (data_width) {
1080                         case 72:
1081                         case 64:
1082                                 dimm_64bit = true;
1083                                 break;
1084                         case 40:
1085                         case 32:
1086                                 dimm_32bit = true;
1087                                 break;
1088                         default:
1089                                 printf("WARNING: Detected a DIMM with a data width of %lu bits.\n",
1090                                        data_width);
1091                                 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
1092                                 break;
1093                         }
1094                 }
1095         }
1096
1097         /* verify matching properties */
1098         if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
1099                 if (buf0 != buf1) {
1100                         printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
1101                         spd_ddr_init_hang ();
1102                 }
1103         }
1104
1105         if ((dimm_64bit == true) && (dimm_32bit == true)) {
1106                 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
1107                 spd_ddr_init_hang ();
1108         } else if ((dimm_64bit == true) && (dimm_32bit == false)) {
1109                 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1110         } else if ((dimm_64bit == false) && (dimm_32bit == true)) {
1111                 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1112         } else {
1113                 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
1114                 spd_ddr_init_hang ();
1115         }
1116
1117         if (ecc_enabled == true)
1118                 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1119         else
1120                 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1121
1122         mtsdram(SDRAM_MCOPT1, mcopt1);
1123 }
1124
1125 /*-----------------------------------------------------------------------------+
1126  * program_codt.
1127  *-----------------------------------------------------------------------------*/
1128 static void program_codt(unsigned long *dimm_populated,
1129                          unsigned char *iic0_dimm_addr,
1130                          unsigned long num_dimm_banks)
1131 {
1132         unsigned long codt;
1133         unsigned long modt0 = 0;
1134         unsigned long modt1 = 0;
1135         unsigned long modt2 = 0;
1136         unsigned long modt3 = 0;
1137         unsigned char dimm_num;
1138         unsigned char dimm_rank;
1139         unsigned char total_rank = 0;
1140         unsigned char total_dimm = 0;
1141         unsigned char dimm_type = 0;
1142         unsigned char firstSlot = 0;
1143
1144         /*------------------------------------------------------------------
1145          * Set the SDRAM Controller On Die Termination Register
1146          *-----------------------------------------------------------------*/
1147         mfsdram(SDRAM_CODT, codt);
1148         codt &= ~(SDRAM_CODT_DQS_SINGLE_END | SDRAM_CODT_CKSE_SINGLE_END);
1149         codt |= SDRAM_CODT_IO_NMODE;
1150
1151         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1152                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1153                         dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1154                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1155                                 dimm_rank = (dimm_rank & 0x0F) + 1;
1156                                 dimm_type = SDRAM_DDR2;
1157                         } else {
1158                                 dimm_rank = dimm_rank & 0x0F;
1159                                 dimm_type = SDRAM_DDR1;
1160                         }
1161
1162                         total_rank += dimm_rank;
1163                         total_dimm++;
1164                         if ((dimm_num == 0) && (total_dimm == 1))
1165                                 firstSlot = true;
1166                         else
1167                                 firstSlot = false;
1168                 }
1169         }
1170         if (dimm_type == SDRAM_DDR2) {
1171                 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1172                 if ((total_dimm == 1) && (firstSlot == true)) {
1173                         if (total_rank == 1) {  /* PUUU */
1174                                 codt |= CALC_ODT_R(0);
1175                                 modt0 = CALC_ODT_W(0);
1176                                 modt1 = 0x00000000;
1177                                 modt2 = 0x00000000;
1178                                 modt3 = 0x00000000;
1179                         }
1180                         if (total_rank == 2) {  /* PPUU */
1181                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
1182                                 modt0 = CALC_ODT_W(0) | CALC_ODT_W(1);
1183                                 modt1 = 0x00000000;
1184                                 modt2 = 0x00000000;
1185                                 modt3 = 0x00000000;
1186                         }
1187                 } else if ((total_dimm == 1) && (firstSlot != true)) {
1188                         if (total_rank == 1) {  /* UUPU */
1189                                 codt |= CALC_ODT_R(2);
1190                                 modt0 = 0x00000000;
1191                                 modt1 = 0x00000000;
1192                                 modt2 = CALC_ODT_W(2);
1193                                 modt3 = 0x00000000;
1194                         }
1195                         if (total_rank == 2) {  /* UUPP */
1196                                 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1197                                 modt0 = 0x00000000;
1198                                 modt1 = 0x00000000;
1199                                 modt2 = CALC_ODT_W(2) | CALC_ODT_W(3);
1200                                 modt3 = 0x00000000;
1201                         }
1202                 }
1203                 if (total_dimm == 2) {
1204                         if (total_rank == 2) {  /* PUPU */
1205                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1206                                 modt0 = CALC_ODT_RW(2);
1207                                 modt1 = 0x00000000;
1208                                 modt2 = CALC_ODT_RW(0);
1209                                 modt3 = 0x00000000;
1210                         }
1211                         if (total_rank == 4) {  /* PPPP */
1212                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
1213                                         CALC_ODT_R(2) | CALC_ODT_R(3);
1214                                 modt0 = CALC_ODT_RW(2) | CALC_ODT_RW(3);
1215                                 modt1 = 0x00000000;
1216                                 modt2 = CALC_ODT_RW(0) | CALC_ODT_RW(1);
1217                                 modt3 = 0x00000000;
1218                         }
1219                 }
1220         } else {
1221                 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1222                 modt0 = 0x00000000;
1223                 modt1 = 0x00000000;
1224                 modt2 = 0x00000000;
1225                 modt3 = 0x00000000;
1226
1227                 if (total_dimm == 1) {
1228                         if (total_rank == 1)
1229                                 codt |= 0x00800000;
1230                         if (total_rank == 2)
1231                                 codt |= 0x02800000;
1232                 }
1233                 if (total_dimm == 2) {
1234                         if (total_rank == 2)
1235                                 codt |= 0x08800000;
1236                         if (total_rank == 4)
1237                                 codt |= 0x2a800000;
1238                 }
1239         }
1240
1241         debug("nb of dimm %d\n", total_dimm);
1242         debug("nb of rank %d\n", total_rank);
1243         if (total_dimm == 1)
1244                 debug("dimm in slot %d\n", firstSlot);
1245
1246         mtsdram(SDRAM_CODT, codt);
1247         mtsdram(SDRAM_MODT0, modt0);
1248         mtsdram(SDRAM_MODT1, modt1);
1249         mtsdram(SDRAM_MODT2, modt2);
1250         mtsdram(SDRAM_MODT3, modt3);
1251 }
1252
1253 /*-----------------------------------------------------------------------------+
1254  * program_initplr.
1255  *-----------------------------------------------------------------------------*/
1256 static void program_initplr(unsigned long *dimm_populated,
1257                             unsigned char *iic0_dimm_addr,
1258                             unsigned long num_dimm_banks,
1259                             ddr_cas_id_t selected_cas,
1260                             int write_recovery)
1261 {
1262         u32 cas = 0;
1263         u32 odt = 0;
1264         u32 ods = 0;
1265         u32 mr;
1266         u32 wr;
1267         u32 emr;
1268         u32 emr2;
1269         u32 emr3;
1270         int dimm_num;
1271         int total_dimm = 0;
1272
1273         /******************************************************
1274          ** Assumption: if more than one DIMM, all DIMMs are the same
1275          **             as already checked in check_memory_type
1276          ******************************************************/
1277
1278         if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1279                 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1280                 mtsdram(SDRAM_INITPLR1, 0x81900400);
1281                 mtsdram(SDRAM_INITPLR2, 0x81810000);
1282                 mtsdram(SDRAM_INITPLR3, 0xff800162);
1283                 mtsdram(SDRAM_INITPLR4, 0x81900400);
1284                 mtsdram(SDRAM_INITPLR5, 0x86080000);
1285                 mtsdram(SDRAM_INITPLR6, 0x86080000);
1286                 mtsdram(SDRAM_INITPLR7, 0x81000062);
1287         } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1288                 switch (selected_cas) {
1289                 case DDR_CAS_3:
1290                         cas = 3 << 4;
1291                         break;
1292                 case DDR_CAS_4:
1293                         cas = 4 << 4;
1294                         break;
1295                 case DDR_CAS_5:
1296                         cas = 5 << 4;
1297                         break;
1298                 default:
1299                         printf("ERROR: ucode error on selected_cas value %d", selected_cas);
1300                         spd_ddr_init_hang ();
1301                         break;
1302                 }
1303
1304 #if 0
1305                 /*
1306                  * ToDo - Still a problem with the write recovery:
1307                  * On the Corsair CM2X512-5400C4 module, setting write recovery
1308                  * in the INITPLR reg to the value calculated in program_mode()
1309                  * results in not correctly working DDR2 memory (crash after
1310                  * relocation).
1311                  *
1312                  * So for now, set the write recovery to 3. This seems to work
1313                  * on the Corair module too.
1314                  *
1315                  * 2007-03-01, sr
1316                  */
1317                 switch (write_recovery) {
1318                 case 3:
1319                         wr = WRITE_RECOV_3;
1320                         break;
1321                 case 4:
1322                         wr = WRITE_RECOV_4;
1323                         break;
1324                 case 5:
1325                         wr = WRITE_RECOV_5;
1326                         break;
1327                 case 6:
1328                         wr = WRITE_RECOV_6;
1329                         break;
1330                 default:
1331                         printf("ERROR: write recovery not support (%d)", write_recovery);
1332                         spd_ddr_init_hang ();
1333                         break;
1334                 }
1335 #else
1336                 wr = WRITE_RECOV_3; /* test-only, see description above */
1337 #endif
1338
1339                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1340                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1341                                 total_dimm++;
1342                 if (total_dimm == 1) {
1343                         odt = ODT_150_OHM;
1344                         ods = ODS_FULL;
1345                 } else if (total_dimm == 2) {
1346                         odt = ODT_75_OHM;
1347                         ods = ODS_REDUCED;
1348                 } else {
1349                         printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
1350                         spd_ddr_init_hang ();
1351                 }
1352
1353                 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1354                 emr = CMD_EMR | SELECT_EMR | odt | ods;
1355                 emr2 = CMD_EMR | SELECT_EMR2;
1356                 emr3 = CMD_EMR | SELECT_EMR3;
1357                 /* NOP - Wait 106 MemClk cycles */
1358                 mtsdram(SDRAM_INITPLR0, SDRAM_INITPLR_ENABLE | CMD_NOP |
1359                                         SDRAM_INITPLR_IMWT_ENCODE(106));
1360                 udelay(1000);
1361                 /* precharge 4 MemClk cycles */
1362                 mtsdram(SDRAM_INITPLR1, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1363                                         SDRAM_INITPLR_IMWT_ENCODE(4));
1364                 /* EMR2 - Wait tMRD (2 MemClk cycles) */
1365                 mtsdram(SDRAM_INITPLR2, SDRAM_INITPLR_ENABLE | emr2 |
1366                                         SDRAM_INITPLR_IMWT_ENCODE(2));
1367                 /* EMR3 - Wait tMRD (2 MemClk cycles) */
1368                 mtsdram(SDRAM_INITPLR3, SDRAM_INITPLR_ENABLE | emr3 |
1369                                         SDRAM_INITPLR_IMWT_ENCODE(2));
1370                 /* EMR DLL ENABLE - Wait tMRD (2 MemClk cycles) */
1371                 mtsdram(SDRAM_INITPLR4, SDRAM_INITPLR_ENABLE | emr |
1372                                         SDRAM_INITPLR_IMWT_ENCODE(2));
1373                 /* MR w/ DLL reset - 200 cycle wait for DLL reset */
1374                 mtsdram(SDRAM_INITPLR5, SDRAM_INITPLR_ENABLE | mr | DLL_RESET |
1375                                         SDRAM_INITPLR_IMWT_ENCODE(200));
1376                 udelay(1000);
1377                 /* precharge 4 MemClk cycles */
1378                 mtsdram(SDRAM_INITPLR6, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1379                                         SDRAM_INITPLR_IMWT_ENCODE(4));
1380                 /* Refresh 25 MemClk cycles */
1381                 mtsdram(SDRAM_INITPLR7, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1382                                         SDRAM_INITPLR_IMWT_ENCODE(25));
1383                 /* Refresh 25 MemClk cycles */
1384                 mtsdram(SDRAM_INITPLR8, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1385                                         SDRAM_INITPLR_IMWT_ENCODE(25));
1386                 /* Refresh 25 MemClk cycles */
1387                 mtsdram(SDRAM_INITPLR9, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1388                                         SDRAM_INITPLR_IMWT_ENCODE(25));
1389                 /* Refresh 25 MemClk cycles */
1390                 mtsdram(SDRAM_INITPLR10, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1391                                          SDRAM_INITPLR_IMWT_ENCODE(25));
1392                 /* MR w/o DLL reset - Wait tMRD (2 MemClk cycles) */
1393                 mtsdram(SDRAM_INITPLR11, SDRAM_INITPLR_ENABLE | mr |
1394                                          SDRAM_INITPLR_IMWT_ENCODE(2));
1395                 /* EMR OCD Default - Wait tMRD (2 MemClk cycles) */
1396                 mtsdram(SDRAM_INITPLR12, SDRAM_INITPLR_ENABLE | OCD_CALIB_DEF |
1397                                          SDRAM_INITPLR_IMWT_ENCODE(2) | emr);
1398                 /* EMR OCD Exit */
1399                 mtsdram(SDRAM_INITPLR13, SDRAM_INITPLR_ENABLE | emr |
1400                                          SDRAM_INITPLR_IMWT_ENCODE(2));
1401         } else {
1402                 printf("ERROR: ucode error as unknown DDR type in program_initplr");
1403                 spd_ddr_init_hang ();
1404         }
1405 }
1406
1407 /*------------------------------------------------------------------
1408  * This routine programs the SDRAM_MMODE register.
1409  * the selected_cas is an output parameter, that will be passed
1410  * by caller to call the above program_initplr( )
1411  *-----------------------------------------------------------------*/
1412 static void program_mode(unsigned long *dimm_populated,
1413                          unsigned char *iic0_dimm_addr,
1414                          unsigned long num_dimm_banks,
1415                          ddr_cas_id_t *selected_cas,
1416                          int *write_recovery)
1417 {
1418         unsigned long dimm_num;
1419         unsigned long sdram_ddr1;
1420         unsigned long t_wr_ns;
1421         unsigned long t_wr_clk;
1422         unsigned long cas_bit;
1423         unsigned long cas_index;
1424         unsigned long sdram_freq;
1425         unsigned long ddr_check;
1426         unsigned long mmode;
1427         unsigned long tcyc_reg;
1428         unsigned long cycle_2_0_clk;
1429         unsigned long cycle_2_5_clk;
1430         unsigned long cycle_3_0_clk;
1431         unsigned long cycle_4_0_clk;
1432         unsigned long cycle_5_0_clk;
1433         unsigned long max_2_0_tcyc_ns_x_100;
1434         unsigned long max_2_5_tcyc_ns_x_100;
1435         unsigned long max_3_0_tcyc_ns_x_100;
1436         unsigned long max_4_0_tcyc_ns_x_100;
1437         unsigned long max_5_0_tcyc_ns_x_100;
1438         unsigned long cycle_time_ns_x_100[3];
1439         PPC4xx_SYS_INFO board_cfg;
1440         unsigned char cas_2_0_available;
1441         unsigned char cas_2_5_available;
1442         unsigned char cas_3_0_available;
1443         unsigned char cas_4_0_available;
1444         unsigned char cas_5_0_available;
1445         unsigned long sdr_ddrpll;
1446
1447         /*------------------------------------------------------------------
1448          * Get the board configuration info.
1449          *-----------------------------------------------------------------*/
1450         get_sys_info(&board_cfg);
1451
1452         mfsdr(SDR0_DDR0, sdr_ddrpll);
1453         sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
1454         debug("sdram_freq=%lu\n", sdram_freq);
1455
1456         /*------------------------------------------------------------------
1457          * Handle the timing.  We need to find the worst case timing of all
1458          * the dimm modules installed.
1459          *-----------------------------------------------------------------*/
1460         t_wr_ns = 0;
1461         cas_2_0_available = true;
1462         cas_2_5_available = true;
1463         cas_3_0_available = true;
1464         cas_4_0_available = true;
1465         cas_5_0_available = true;
1466         max_2_0_tcyc_ns_x_100 = 10;
1467         max_2_5_tcyc_ns_x_100 = 10;
1468         max_3_0_tcyc_ns_x_100 = 10;
1469         max_4_0_tcyc_ns_x_100 = 10;
1470         max_5_0_tcyc_ns_x_100 = 10;
1471         sdram_ddr1 = true;
1472
1473         /* loop through all the DIMM slots on the board */
1474         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1475                 /* If a dimm is installed in a particular slot ... */
1476                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1477                         if (dimm_populated[dimm_num] == SDRAM_DDR1)
1478                                 sdram_ddr1 = true;
1479                         else
1480                                 sdram_ddr1 = false;
1481
1482                         cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1483                         debug("cas_bit[SPD byte 18]=%02lx\n", cas_bit);
1484
1485                         /* For a particular DIMM, grab the three CAS values it supports */
1486                         for (cas_index = 0; cas_index < 3; cas_index++) {
1487                                 switch (cas_index) {
1488                                 case 0:
1489                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1490                                         break;
1491                                 case 1:
1492                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1493                                         break;
1494                                 default:
1495                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1496                                         break;
1497                                 }
1498
1499                                 if ((tcyc_reg & 0x0F) >= 10) {
1500                                         if ((tcyc_reg & 0x0F) == 0x0D) {
1501                                                 /* Convert from hex to decimal */
1502                                                 cycle_time_ns_x_100[cas_index] =
1503                                                         (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
1504                                         } else {
1505                                                 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1506                                                        "in slot %d\n", (unsigned int)dimm_num);
1507                                                 spd_ddr_init_hang ();
1508                                         }
1509                                 } else {
1510                                         /* Convert from hex to decimal */
1511                                         cycle_time_ns_x_100[cas_index] =
1512                                                 (((tcyc_reg & 0xF0) >> 4) * 100) +
1513                                                 ((tcyc_reg & 0x0F)*10);
1514                                 }
1515                                 debug("cas_index=%lu: cycle_time_ns_x_100=%lu\n", cas_index,
1516                                       cycle_time_ns_x_100[cas_index]);
1517                         }
1518
1519                         /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1520                         /* supported for a particular DIMM. */
1521                         cas_index = 0;
1522
1523                         if (sdram_ddr1) {
1524                                 /*
1525                                  * DDR devices use the following bitmask for CAS latency:
1526                                  *  Bit   7    6    5    4    3    2    1    0
1527                                  *       TBD  4.0  3.5  3.0  2.5  2.0  1.5  1.0
1528                                  */
1529                                 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
1530                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1531                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1532                                                                     cycle_time_ns_x_100[cas_index]);
1533                                         cas_index++;
1534                                 } else {
1535                                         if (cas_index != 0)
1536                                                 cas_index++;
1537                                         cas_4_0_available = false;
1538                                 }
1539
1540                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1541                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1542                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1543                                                                     cycle_time_ns_x_100[cas_index]);
1544                                         cas_index++;
1545                                 } else {
1546                                         if (cas_index != 0)
1547                                                 cas_index++;
1548                                         cas_3_0_available = false;
1549                                 }
1550
1551                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1552                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1553                                         max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
1554                                                                     cycle_time_ns_x_100[cas_index]);
1555                                         cas_index++;
1556                                 } else {
1557                                         if (cas_index != 0)
1558                                                 cas_index++;
1559                                         cas_2_5_available = false;
1560                                 }
1561
1562                                 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
1563                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1564                                         max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
1565                                                                     cycle_time_ns_x_100[cas_index]);
1566                                         cas_index++;
1567                                 } else {
1568                                         if (cas_index != 0)
1569                                                 cas_index++;
1570                                         cas_2_0_available = false;
1571                                 }
1572                         } else {
1573                                 /*
1574                                  * DDR2 devices use the following bitmask for CAS latency:
1575                                  *  Bit   7    6    5    4    3    2    1    0
1576                                  *       TBD  6.0  5.0  4.0  3.0  2.0  TBD  TBD
1577                                  */
1578                                 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
1579                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1580                                         max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
1581                                                                     cycle_time_ns_x_100[cas_index]);
1582                                         cas_index++;
1583                                 } else {
1584                                         if (cas_index != 0)
1585                                                 cas_index++;
1586                                         cas_5_0_available = false;
1587                                 }
1588
1589                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1590                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1591                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1592                                                                     cycle_time_ns_x_100[cas_index]);
1593                                         cas_index++;
1594                                 } else {
1595                                         if (cas_index != 0)
1596                                                 cas_index++;
1597                                         cas_4_0_available = false;
1598                                 }
1599
1600                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1601                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1602                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1603                                                                     cycle_time_ns_x_100[cas_index]);
1604                                         cas_index++;
1605                                 } else {
1606                                         if (cas_index != 0)
1607                                                 cas_index++;
1608                                         cas_3_0_available = false;
1609                                 }
1610                         }
1611                 }
1612         }
1613
1614         /*------------------------------------------------------------------
1615          * Set the SDRAM mode, SDRAM_MMODE
1616          *-----------------------------------------------------------------*/
1617         mfsdram(SDRAM_MMODE, mmode);
1618         mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1619
1620         /* add 10 here because of rounding problems */
1621         cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1622         cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1623         cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1624         cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1625         cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
1626         debug("cycle_3_0_clk=%lu\n", cycle_3_0_clk);
1627         debug("cycle_4_0_clk=%lu\n", cycle_4_0_clk);
1628         debug("cycle_5_0_clk=%lu\n", cycle_5_0_clk);
1629
1630         if (sdram_ddr1 == true) { /* DDR1 */
1631                 if ((cas_2_0_available == true) &&
1632                         (sdram_freq <= cycle_2_0_clk)) {
1633                         mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1634                         *selected_cas = DDR_CAS_2;
1635                 } else if ((cas_2_5_available == true) &&
1636                         (sdram_freq <= cycle_2_5_clk)) {
1637                         mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1638                         *selected_cas = DDR_CAS_2_5;
1639                 } else if ((cas_3_0_available == true) &&
1640                         (sdram_freq <= cycle_3_0_clk)) {
1641                         mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1642                         *selected_cas = DDR_CAS_3;
1643                 } else {
1644                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1645                         printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1646                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1647                         spd_ddr_init_hang ();
1648                 }
1649         } else { /* DDR2 */
1650                 debug("cas_3_0_available=%d\n", cas_3_0_available);
1651                 debug("cas_4_0_available=%d\n", cas_4_0_available);
1652                 debug("cas_5_0_available=%d\n", cas_5_0_available);
1653                 if ((cas_3_0_available == true) &&
1654                         (sdram_freq <= cycle_3_0_clk)) {
1655                         mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1656                         *selected_cas = DDR_CAS_3;
1657                 } else if ((cas_4_0_available == true) &&
1658                         (sdram_freq <= cycle_4_0_clk)) {
1659                         mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1660                         *selected_cas = DDR_CAS_4;
1661                 } else if ((cas_5_0_available == true) &&
1662                         (sdram_freq <= cycle_5_0_clk)) {
1663                         mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1664                         *selected_cas = DDR_CAS_5;
1665                 } else {
1666                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1667                         printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
1668                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1669                         printf("cas3=%d cas4=%d cas5=%d\n",
1670                                cas_3_0_available, cas_4_0_available, cas_5_0_available);
1671                         printf("sdram_freq=%lu cycle3=%lu cycle4=%lu cycle5=%lu\n\n",
1672                                sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
1673                         spd_ddr_init_hang ();
1674                 }
1675         }
1676
1677         if (sdram_ddr1 == true)
1678                 mmode |= SDRAM_MMODE_WR_DDR1;
1679         else {
1680
1681                 /* loop through all the DIMM slots on the board */
1682                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1683                         /* If a dimm is installed in a particular slot ... */
1684                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1685                                 t_wr_ns = max(t_wr_ns,
1686                                               spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1687                 }
1688
1689                 /*
1690                  * convert from nanoseconds to ddr clocks
1691                  * round up if necessary
1692                  */
1693                 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1694                 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1695                 if (sdram_freq != ddr_check)
1696                         t_wr_clk++;
1697
1698                 switch (t_wr_clk) {
1699                 case 0:
1700                 case 1:
1701                 case 2:
1702                 case 3:
1703                         mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1704                         break;
1705                 case 4:
1706                         mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1707                         break;
1708                 case 5:
1709                         mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1710                         break;
1711                 default:
1712                         mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1713                         break;
1714                 }
1715                 *write_recovery = t_wr_clk;
1716         }
1717
1718         debug("CAS latency = %d\n", *selected_cas);
1719         debug("Write recovery = %d\n", *write_recovery);
1720
1721         mtsdram(SDRAM_MMODE, mmode);
1722 }
1723
1724 /*-----------------------------------------------------------------------------+
1725  * program_rtr.
1726  *-----------------------------------------------------------------------------*/
1727 static void program_rtr(unsigned long *dimm_populated,
1728                         unsigned char *iic0_dimm_addr,
1729                         unsigned long num_dimm_banks)
1730 {
1731         PPC4xx_SYS_INFO board_cfg;
1732         unsigned long max_refresh_rate;
1733         unsigned long dimm_num;
1734         unsigned long refresh_rate_type;
1735         unsigned long refresh_rate;
1736         unsigned long rint;
1737         unsigned long sdram_freq;
1738         unsigned long sdr_ddrpll;
1739         unsigned long val;
1740
1741         /*------------------------------------------------------------------
1742          * Get the board configuration info.
1743          *-----------------------------------------------------------------*/
1744         get_sys_info(&board_cfg);
1745
1746         /*------------------------------------------------------------------
1747          * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1748          *-----------------------------------------------------------------*/
1749         mfsdr(SDR0_DDR0, sdr_ddrpll);
1750         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1751
1752         max_refresh_rate = 0;
1753         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1754                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1755
1756                         refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1757                         refresh_rate_type &= 0x7F;
1758                         switch (refresh_rate_type) {
1759                         case 0:
1760                                 refresh_rate =  15625;
1761                                 break;
1762                         case 1:
1763                                 refresh_rate =   3906;
1764                                 break;
1765                         case 2:
1766                                 refresh_rate =   7812;
1767                                 break;
1768                         case 3:
1769                                 refresh_rate =  31250;
1770                                 break;
1771                         case 4:
1772                                 refresh_rate =  62500;
1773                                 break;
1774                         case 5:
1775                                 refresh_rate = 125000;
1776                                 break;
1777                         default:
1778                                 refresh_rate = 0;
1779                                 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1780                                        (unsigned int)dimm_num);
1781                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1782                                 spd_ddr_init_hang ();
1783                                 break;
1784                         }
1785
1786                         max_refresh_rate = max(max_refresh_rate, refresh_rate);
1787                 }
1788         }
1789
1790         rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1791         mfsdram(SDRAM_RTR, val);
1792         mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1793                 (SDRAM_RTR_RINT_ENCODE(rint)));
1794 }
1795
1796 /*------------------------------------------------------------------
1797  * This routine programs the SDRAM_TRx registers.
1798  *-----------------------------------------------------------------*/
1799 static void program_tr(unsigned long *dimm_populated,
1800                        unsigned char *iic0_dimm_addr,
1801                        unsigned long num_dimm_banks)
1802 {
1803         unsigned long dimm_num;
1804         unsigned long sdram_ddr1;
1805         unsigned long t_rp_ns;
1806         unsigned long t_rcd_ns;
1807         unsigned long t_rrd_ns;
1808         unsigned long t_ras_ns;
1809         unsigned long t_rc_ns;
1810         unsigned long t_rfc_ns;
1811         unsigned long t_wpc_ns;
1812         unsigned long t_wtr_ns;
1813         unsigned long t_rpc_ns;
1814         unsigned long t_rp_clk;
1815         unsigned long t_rcd_clk;
1816         unsigned long t_rrd_clk;
1817         unsigned long t_ras_clk;
1818         unsigned long t_rc_clk;
1819         unsigned long t_rfc_clk;
1820         unsigned long t_wpc_clk;
1821         unsigned long t_wtr_clk;
1822         unsigned long t_rpc_clk;
1823         unsigned long sdtr1, sdtr2, sdtr3;
1824         unsigned long ddr_check;
1825         unsigned long sdram_freq;
1826         unsigned long sdr_ddrpll;
1827
1828         PPC4xx_SYS_INFO board_cfg;
1829
1830         /*------------------------------------------------------------------
1831          * Get the board configuration info.
1832          *-----------------------------------------------------------------*/
1833         get_sys_info(&board_cfg);
1834
1835         mfsdr(SDR0_DDR0, sdr_ddrpll);
1836         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1837
1838         /*------------------------------------------------------------------
1839          * Handle the timing.  We need to find the worst case timing of all
1840          * the dimm modules installed.
1841          *-----------------------------------------------------------------*/
1842         t_rp_ns = 0;
1843         t_rrd_ns = 0;
1844         t_rcd_ns = 0;
1845         t_ras_ns = 0;
1846         t_rc_ns = 0;
1847         t_rfc_ns = 0;
1848         t_wpc_ns = 0;
1849         t_wtr_ns = 0;
1850         t_rpc_ns = 0;
1851         sdram_ddr1 = true;
1852
1853         /* loop through all the DIMM slots on the board */
1854         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1855                 /* If a dimm is installed in a particular slot ... */
1856                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1857                         if (dimm_populated[dimm_num] == SDRAM_DDR2)
1858                                 sdram_ddr1 = true;
1859                         else
1860                                 sdram_ddr1 = false;
1861
1862                         t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1863                         t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1864                         t_rp_ns  = max(t_rp_ns,  spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1865                         t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1866                         t_rc_ns  = max(t_rc_ns,  spd_read(iic0_dimm_addr[dimm_num], 41));
1867                         t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1868                 }
1869         }
1870
1871         /*------------------------------------------------------------------
1872          * Set the SDRAM Timing Reg 1, SDRAM_TR1
1873          *-----------------------------------------------------------------*/
1874         mfsdram(SDRAM_SDTR1, sdtr1);
1875         sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1876                    SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1877
1878         /* default values */
1879         sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1880         sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1881
1882         /* normal operations */
1883         sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1884         sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1885
1886         mtsdram(SDRAM_SDTR1, sdtr1);
1887
1888         /*------------------------------------------------------------------
1889          * Set the SDRAM Timing Reg 2, SDRAM_TR2
1890          *-----------------------------------------------------------------*/
1891         mfsdram(SDRAM_SDTR2, sdtr2);
1892         sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK  | SDRAM_SDTR2_WTR_MASK |
1893                    SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1894                    SDRAM_SDTR2_RPC_MASK  | SDRAM_SDTR2_RP_MASK  |
1895                    SDRAM_SDTR2_RRD_MASK);
1896
1897         /*
1898          * convert t_rcd from nanoseconds to ddr clocks
1899          * round up if necessary
1900          */
1901         t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1902         ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1903         if (sdram_freq != ddr_check)
1904                 t_rcd_clk++;
1905
1906         switch (t_rcd_clk) {
1907         case 0:
1908         case 1:
1909                 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1910                 break;
1911         case 2:
1912                 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1913                 break;
1914         case 3:
1915                 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1916                 break;
1917         case 4:
1918                 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1919                 break;
1920         default:
1921                 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1922                 break;
1923         }
1924
1925         if (sdram_ddr1 == true) { /* DDR1 */
1926                 if (sdram_freq < 200000000) {
1927                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1928                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1929                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1930                 } else {
1931                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1932                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1933                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1934                 }
1935         } else { /* DDR2 */
1936                 /* loop through all the DIMM slots on the board */
1937                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1938                         /* If a dimm is installed in a particular slot ... */
1939                         if (dimm_populated[dimm_num] != SDRAM_NONE) {
1940                                 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1941                                 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1942                                 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1943                         }
1944                 }
1945
1946                 /*
1947                  * convert from nanoseconds to ddr clocks
1948                  * round up if necessary
1949                  */
1950                 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1951                 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1952                 if (sdram_freq != ddr_check)
1953                         t_wpc_clk++;
1954
1955                 switch (t_wpc_clk) {
1956                 case 0:
1957                 case 1:
1958                 case 2:
1959                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1960                         break;
1961                 case 3:
1962                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1963                         break;
1964                 case 4:
1965                         sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1966                         break;
1967                 case 5:
1968                         sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1969                         break;
1970                 default:
1971                         sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1972                         break;
1973                 }
1974
1975                 /*
1976                  * convert from nanoseconds to ddr clocks
1977                  * round up if necessary
1978                  */
1979                 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1980                 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1981                 if (sdram_freq != ddr_check)
1982                         t_wtr_clk++;
1983
1984                 switch (t_wtr_clk) {
1985                 case 0:
1986                 case 1:
1987                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1988                         break;
1989                 case 2:
1990                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1991                         break;
1992                 case 3:
1993                         sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
1994                         break;
1995                 default:
1996                         sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
1997                         break;
1998                 }
1999
2000                 /*
2001                  * convert from nanoseconds to ddr clocks
2002                  * round up if necessary
2003                  */
2004                 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
2005                 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
2006                 if (sdram_freq != ddr_check)
2007                         t_rpc_clk++;
2008
2009                 switch (t_rpc_clk) {
2010                 case 0:
2011                 case 1:
2012                 case 2:
2013                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
2014                         break;
2015                 case 3:
2016                         sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
2017                         break;
2018                 default:
2019                         sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
2020                         break;
2021                 }
2022         }
2023
2024         /* default value */
2025         sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
2026
2027         /*
2028          * convert t_rrd from nanoseconds to ddr clocks
2029          * round up if necessary
2030          */
2031         t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
2032         ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
2033         if (sdram_freq != ddr_check)
2034                 t_rrd_clk++;
2035
2036         if (t_rrd_clk == 3)
2037                 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
2038         else
2039                 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
2040
2041         /*
2042          * convert t_rp from nanoseconds to ddr clocks
2043          * round up if necessary
2044          */
2045         t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
2046         ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
2047         if (sdram_freq != ddr_check)
2048                 t_rp_clk++;
2049
2050         switch (t_rp_clk) {
2051         case 0:
2052         case 1:
2053         case 2:
2054         case 3:
2055                 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
2056                 break;
2057         case 4:
2058                 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
2059                 break;
2060         case 5:
2061                 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
2062                 break;
2063         case 6:
2064                 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
2065                 break;
2066         default:
2067                 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
2068                 break;
2069         }
2070
2071         mtsdram(SDRAM_SDTR2, sdtr2);
2072
2073         /*------------------------------------------------------------------
2074          * Set the SDRAM Timing Reg 3, SDRAM_TR3
2075          *-----------------------------------------------------------------*/
2076         mfsdram(SDRAM_SDTR3, sdtr3);
2077         sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK  | SDRAM_SDTR3_RC_MASK |
2078                    SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
2079
2080         /*
2081          * convert t_ras from nanoseconds to ddr clocks
2082          * round up if necessary
2083          */
2084         t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
2085         ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
2086         if (sdram_freq != ddr_check)
2087                 t_ras_clk++;
2088
2089         sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
2090
2091         /*
2092          * convert t_rc from nanoseconds to ddr clocks
2093          * round up if necessary
2094          */
2095         t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
2096         ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
2097         if (sdram_freq != ddr_check)
2098                 t_rc_clk++;
2099
2100         sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
2101
2102         /* default xcs value */
2103         sdtr3 |= SDRAM_SDTR3_XCS;
2104
2105         /*
2106          * convert t_rfc from nanoseconds to ddr clocks
2107          * round up if necessary
2108          */
2109         t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
2110         ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
2111         if (sdram_freq != ddr_check)
2112                 t_rfc_clk++;
2113
2114         sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
2115
2116         mtsdram(SDRAM_SDTR3, sdtr3);
2117 }
2118
2119 /*-----------------------------------------------------------------------------+
2120  * program_bxcf.
2121  *-----------------------------------------------------------------------------*/
2122 static void program_bxcf(unsigned long *dimm_populated,
2123                          unsigned char *iic0_dimm_addr,
2124                          unsigned long num_dimm_banks)
2125 {
2126         unsigned long dimm_num;
2127         unsigned long num_col_addr;
2128         unsigned long num_ranks;
2129         unsigned long num_banks;
2130         unsigned long mode;
2131         unsigned long ind_rank;
2132         unsigned long ind;
2133         unsigned long ind_bank;
2134         unsigned long bank_0_populated;
2135
2136         /*------------------------------------------------------------------
2137          * Set the BxCF regs.  First, wipe out the bank config registers.
2138          *-----------------------------------------------------------------*/
2139         mtsdram(SDRAM_MB0CF, 0x00000000);
2140         mtsdram(SDRAM_MB1CF, 0x00000000);
2141         mtsdram(SDRAM_MB2CF, 0x00000000);
2142         mtsdram(SDRAM_MB3CF, 0x00000000);
2143
2144         mode = SDRAM_BXCF_M_BE_ENABLE;
2145
2146         bank_0_populated = 0;
2147
2148         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2149                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2150                         num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
2151                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2152                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2153                                 num_ranks = (num_ranks & 0x0F) +1;
2154                         else
2155                                 num_ranks = num_ranks & 0x0F;
2156
2157                         num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
2158
2159                         for (ind_bank = 0; ind_bank < 2; ind_bank++) {
2160                                 if (num_banks == 4)
2161                                         ind = 0;
2162                                 else
2163                                         ind = 5 << 8;
2164                                 switch (num_col_addr) {
2165                                 case 0x08:
2166                                         mode |= (SDRAM_BXCF_M_AM_0 + ind);
2167                                         break;
2168                                 case 0x09:
2169                                         mode |= (SDRAM_BXCF_M_AM_1 + ind);
2170                                         break;
2171                                 case 0x0A:
2172                                         mode |= (SDRAM_BXCF_M_AM_2 + ind);
2173                                         break;
2174                                 case 0x0B:
2175                                         mode |= (SDRAM_BXCF_M_AM_3 + ind);
2176                                         break;
2177                                 case 0x0C:
2178                                         mode |= (SDRAM_BXCF_M_AM_4 + ind);
2179                                         break;
2180                                 default:
2181                                         printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2182                                                (unsigned int)dimm_num);
2183                                         printf("ERROR: Unsupported value for number of "
2184                                                "column addresses: %d.\n", (unsigned int)num_col_addr);
2185                                         printf("Replace the DIMM module with a supported DIMM.\n\n");
2186                                         spd_ddr_init_hang ();
2187                                 }
2188                         }
2189
2190                         if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2191                                 bank_0_populated = 1;
2192
2193                         for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
2194                                 mtsdram(SDRAM_MB0CF +
2195                                         ((dimm_num + bank_0_populated + ind_rank) << 2),
2196                                         mode);
2197                         }
2198                 }
2199         }
2200 }
2201
2202 /*------------------------------------------------------------------
2203  * program memory queue.
2204  *-----------------------------------------------------------------*/
2205 static void program_memory_queue(unsigned long *dimm_populated,
2206                                  unsigned char *iic0_dimm_addr,
2207                                  unsigned long num_dimm_banks)
2208 {
2209         unsigned long dimm_num;
2210         phys_size_t rank_base_addr;
2211         unsigned long rank_reg;
2212         phys_size_t rank_size_bytes;
2213         unsigned long rank_size_id;
2214         unsigned long num_ranks;
2215         unsigned long baseadd_size;
2216         unsigned long i;
2217         unsigned long bank_0_populated = 0;
2218         phys_size_t total_size = 0;
2219
2220         /*------------------------------------------------------------------
2221          * Reset the rank_base_address.
2222          *-----------------------------------------------------------------*/
2223         rank_reg   = SDRAM_R0BAS;
2224
2225         rank_base_addr = 0x00000000;
2226
2227         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2228                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2229                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2230                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2231                                 num_ranks = (num_ranks & 0x0F) + 1;
2232                         else
2233                                 num_ranks = num_ranks & 0x0F;
2234
2235                         rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2236
2237                         /*------------------------------------------------------------------
2238                          * Set the sizes
2239                          *-----------------------------------------------------------------*/
2240                         baseadd_size = 0;
2241                         switch (rank_size_id) {
2242                         case 0x01:
2243                                 baseadd_size |= SDRAM_RXBAS_SDSZ_1024;
2244                                 total_size = 1024;
2245                                 break;
2246                         case 0x02:
2247                                 baseadd_size |= SDRAM_RXBAS_SDSZ_2048;
2248                                 total_size = 2048;
2249                                 break;
2250                         case 0x04:
2251                                 baseadd_size |= SDRAM_RXBAS_SDSZ_4096;
2252                                 total_size = 4096;
2253                                 break;
2254                         case 0x08:
2255                                 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
2256                                 total_size = 32;
2257                                 break;
2258                         case 0x10:
2259                                 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
2260                                 total_size = 64;
2261                                 break;
2262                         case 0x20:
2263                                 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
2264                                 total_size = 128;
2265                                 break;
2266                         case 0x40:
2267                                 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
2268                                 total_size = 256;
2269                                 break;
2270                         case 0x80:
2271                                 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
2272                                 total_size = 512;
2273                                 break;
2274                         default:
2275                                 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2276                                        (unsigned int)dimm_num);
2277                                 printf("ERROR: Unsupported value for the banksize: %d.\n",
2278                                        (unsigned int)rank_size_id);
2279                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
2280                                 spd_ddr_init_hang ();
2281                         }
2282                         rank_size_bytes = total_size << 20;
2283
2284                         if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2285                                 bank_0_populated = 1;
2286
2287                         for (i = 0; i < num_ranks; i++) {
2288                                 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
2289                                           (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2290                                            baseadd_size));
2291                                 rank_base_addr += rank_size_bytes;
2292                         }
2293                 }
2294         }
2295
2296 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
2297     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
2298     defined(CONFIG_460SX)
2299         /*
2300          * Enable high bandwidth access
2301          * This is currently not used, but with this setup
2302          * it is possible to use it later on in e.g. the Linux
2303          * EMAC driver for performance gain.
2304          */
2305         mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
2306         mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
2307
2308         /*
2309          * Set optimal value for Memory Queue HB/LL Configuration registers
2310          */
2311         mtdcr(SDRAM_CONF1HB, (mfdcr(SDRAM_CONF1HB) & ~SDRAM_CONF1HB_MASK) |
2312               SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE |
2313               SDRAM_CONF1HB_RPLM | SDRAM_CONF1HB_WRCL);
2314         mtdcr(SDRAM_CONF1LL, (mfdcr(SDRAM_CONF1LL) & ~SDRAM_CONF1LL_MASK) |
2315               SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE |
2316               SDRAM_CONF1LL_RPLM);
2317         mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
2318 #endif
2319 }
2320
2321 #ifdef CONFIG_DDR_ECC
2322 /*-----------------------------------------------------------------------------+
2323  * program_ecc.
2324  *-----------------------------------------------------------------------------*/
2325 static void program_ecc(unsigned long *dimm_populated,
2326                         unsigned char *iic0_dimm_addr,
2327                         unsigned long num_dimm_banks,
2328                         unsigned long tlb_word2_i_value)
2329 {
2330         unsigned long dimm_num;
2331         unsigned long ecc;
2332
2333         ecc = 0;
2334         /* loop through all the DIMM slots on the board */
2335         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2336                 /* If a dimm is installed in a particular slot ... */
2337                 if (dimm_populated[dimm_num] != SDRAM_NONE)
2338                         ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2339         }
2340         if (ecc == 0)
2341                 return;
2342
2343         do_program_ecc(tlb_word2_i_value);
2344 }
2345 #endif
2346
2347 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
2348 /*-----------------------------------------------------------------------------+
2349  * program_DQS_calibration.
2350  *-----------------------------------------------------------------------------*/
2351 static void program_DQS_calibration(unsigned long *dimm_populated,
2352                                     unsigned char *iic0_dimm_addr,
2353                                     unsigned long num_dimm_banks)
2354 {
2355         unsigned long val;
2356
2357 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2358         mtsdram(SDRAM_RQDC, 0x80000037);
2359         mtsdram(SDRAM_RDCC, 0x40000000);
2360         mtsdram(SDRAM_RFDC, 0x000001DF);
2361
2362         test();
2363 #else
2364         /*------------------------------------------------------------------
2365          * Program RDCC register
2366          * Read sample cycle auto-update enable
2367          *-----------------------------------------------------------------*/
2368
2369         mfsdram(SDRAM_RDCC, val);
2370         mtsdram(SDRAM_RDCC,
2371                 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
2372                 | SDRAM_RDCC_RSAE_ENABLE);
2373
2374         /*------------------------------------------------------------------
2375          * Program RQDC register
2376          * Internal DQS delay mechanism enable
2377          *-----------------------------------------------------------------*/
2378         mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2379
2380         /*------------------------------------------------------------------
2381          * Program RFDC register
2382          * Set Feedback Fractional Oversample
2383          * Auto-detect read sample cycle enable
2384          * Set RFOS to 1/4 of memclk cycle (0x3f)
2385          *-----------------------------------------------------------------*/
2386         mfsdram(SDRAM_RFDC, val);
2387         mtsdram(SDRAM_RFDC,
2388                 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2389                          SDRAM_RFDC_RFFD_MASK))
2390                 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0x3f) |
2391                    SDRAM_RFDC_RFFD_ENCODE(0)));
2392
2393         DQS_calibration_process();
2394 #endif
2395 }
2396
2397 static int short_mem_test(void)
2398 {
2399         u32 *membase;
2400         u32 bxcr_num;
2401         u32 bxcf;
2402         int i;
2403         int j;
2404         phys_size_t base_addr;
2405         u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2406                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2407                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2408                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2409                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2410                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2411                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2412                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2413                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2414                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2415                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2416                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2417                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2418                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2419                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2420                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2421                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2422         int l;
2423
2424         for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2425                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2426
2427                 /* Banks enabled */
2428                 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2429                         /* Bank is enabled */
2430
2431                         /*
2432                          * Only run test on accessable memory (below 2GB)
2433                          */
2434                         base_addr = SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num));
2435                         if (base_addr >= CONFIG_MAX_MEM_MAPPED)
2436                                 continue;
2437
2438                         /*------------------------------------------------------------------
2439                          * Run the short memory test.
2440                          *-----------------------------------------------------------------*/
2441                         membase = (u32 *)(u32)base_addr;
2442
2443                         for (i = 0; i < NUMMEMTESTS; i++) {
2444                                 for (j = 0; j < NUMMEMWORDS; j++) {
2445                                         membase[j] = test[i][j];
2446                                         ppcDcbf((u32)&(membase[j]));
2447                                 }
2448                                 sync();
2449                                 for (l=0; l<NUMLOOPS; l++) {
2450                                         for (j = 0; j < NUMMEMWORDS; j++) {
2451                                                 if (membase[j] != test[i][j]) {
2452                                                         ppcDcbf((u32)&(membase[j]));
2453                                                         return 0;
2454                                                 }
2455                                                 ppcDcbf((u32)&(membase[j]));
2456                                         }
2457                                         sync();
2458                                 }
2459                         }
2460                 }       /* if bank enabled */
2461         }               /* for bxcf_num */
2462
2463         return 1;
2464 }
2465
2466 #ifndef HARD_CODED_DQS
2467 /*-----------------------------------------------------------------------------+
2468  * DQS_calibration_process.
2469  *-----------------------------------------------------------------------------*/
2470 static void DQS_calibration_process(void)
2471 {
2472         unsigned long rfdc_reg;
2473         unsigned long rffd;
2474         unsigned long val;
2475         long rffd_average;
2476         long max_start;
2477         unsigned long dlycal;
2478         unsigned long dly_val;
2479         unsigned long max_pass_length;
2480         unsigned long current_pass_length;
2481         unsigned long current_fail_length;
2482         unsigned long current_start;
2483         long max_end;
2484         unsigned char fail_found;
2485         unsigned char pass_found;
2486 #if !defined(CONFIG_DDR_RQDC_FIXED)
2487         int window_found;
2488         u32 rqdc_reg;
2489         u32 rqfd;
2490         u32 rqfd_start;
2491         u32 rqfd_average;
2492         int loopi = 0;
2493         char str[] = "Auto calibration -";
2494         char slash[] = "\\|/-\\|/-";
2495
2496         /*------------------------------------------------------------------
2497          * Test to determine the best read clock delay tuning bits.
2498          *
2499          * Before the DDR controller can be used, the read clock delay needs to be
2500          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2501          * This value cannot be hardcoded into the program because it changes
2502          * depending on the board's setup and environment.
2503          * To do this, all delay values are tested to see if they
2504          * work or not.  By doing this, you get groups of fails with groups of
2505          * passing values.  The idea is to find the start and end of a passing
2506          * window and take the center of it to use as the read clock delay.
2507          *
2508          * A failure has to be seen first so that when we hit a pass, we know
2509          * that it is truely the start of the window.  If we get passing values
2510          * to start off with, we don't know if we are at the start of the window.
2511          *
2512          * The code assumes that a failure will always be found.
2513          * If a failure is not found, there is no easy way to get the middle
2514          * of the passing window.  I guess we can pretty much pick any value
2515          * but some values will be better than others.  Since the lowest speed
2516          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2517          * from experimentation it is safe to say you will always have a failure.
2518          *-----------------------------------------------------------------*/
2519
2520         /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2521         rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
2522
2523         puts(str);
2524
2525 calibration_loop:
2526         mfsdram(SDRAM_RQDC, rqdc_reg);
2527         mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2528                 SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
2529 #else /* CONFIG_DDR_RQDC_FIXED */
2530         /*
2531          * On Katmai the complete auto-calibration somehow doesn't seem to
2532          * produce the best results, meaning optimal values for RQFD/RFFD.
2533          * This was discovered by GDA using a high bandwidth scope,
2534          * analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
2535          * so now on Katmai "only" RFFD is auto-calibrated.
2536          */
2537         mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
2538 #endif /* CONFIG_DDR_RQDC_FIXED */
2539
2540         max_start = 0;
2541
2542         max_pass_length = 0;
2543         max_start = 0;
2544         max_end = 0;
2545         current_pass_length = 0;
2546         current_fail_length = 0;
2547         current_start = 0;
2548         fail_found = false;
2549         pass_found = false;
2550
2551         /*
2552          * get the delay line calibration register value
2553          */
2554         mfsdram(SDRAM_DLCR, dlycal);
2555         dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2556
2557         for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2558                 mfsdram(SDRAM_RFDC, rfdc_reg);
2559                 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2560
2561                 /*------------------------------------------------------------------
2562                  * Set the timing reg for the test.
2563                  *-----------------------------------------------------------------*/
2564                 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2565
2566                 /*------------------------------------------------------------------
2567                  * See if the rffd value passed.
2568                  *-----------------------------------------------------------------*/
2569                 if (short_mem_test()) {
2570                         if (fail_found == true) {
2571                                 pass_found = true;
2572                                 if (current_pass_length == 0)
2573                                         current_start = rffd;
2574
2575                                 current_fail_length = 0;
2576                                 current_pass_length++;
2577
2578                                 if (current_pass_length > max_pass_length) {
2579                                         max_pass_length = current_pass_length;
2580                                         max_start = current_start;
2581                                         max_end = rffd;
2582                                 }
2583                         }
2584                 } else {
2585                         current_pass_length = 0;
2586                         current_fail_length++;
2587
2588                         if (current_fail_length >= (dly_val >> 2)) {
2589                                 if (fail_found == false)
2590                                         fail_found = true;
2591                                 else if (pass_found == true)
2592                                         break;
2593                         }
2594                 }
2595         }               /* for rffd */
2596
2597         /*------------------------------------------------------------------
2598          * Set the average RFFD value
2599          *-----------------------------------------------------------------*/
2600         rffd_average = ((max_start + max_end) >> 1);
2601
2602         if (rffd_average < 0)
2603                 rffd_average = 0;
2604
2605         if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2606                 rffd_average = SDRAM_RFDC_RFFD_MAX;
2607         /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2608         mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2609
2610 #if !defined(CONFIG_DDR_RQDC_FIXED)
2611         max_pass_length = 0;
2612         max_start = 0;
2613         max_end = 0;
2614         current_pass_length = 0;
2615         current_fail_length = 0;
2616         current_start = 0;
2617         window_found = false;
2618         fail_found = false;
2619         pass_found = false;
2620
2621         for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2622                 mfsdram(SDRAM_RQDC, rqdc_reg);
2623                 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2624
2625                 /*------------------------------------------------------------------
2626                  * Set the timing reg for the test.
2627                  *-----------------------------------------------------------------*/
2628                 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2629
2630                 /*------------------------------------------------------------------
2631                  * See if the rffd value passed.
2632                  *-----------------------------------------------------------------*/
2633                 if (short_mem_test()) {
2634                         if (fail_found == true) {
2635                                 pass_found = true;
2636                                 if (current_pass_length == 0)
2637                                         current_start = rqfd;
2638
2639                                 current_fail_length = 0;
2640                                 current_pass_length++;
2641
2642                                 if (current_pass_length > max_pass_length) {
2643                                         max_pass_length = current_pass_length;
2644                                         max_start = current_start;
2645                                         max_end = rqfd;
2646                                 }
2647                         }
2648                 } else {
2649                         current_pass_length = 0;
2650                         current_fail_length++;
2651
2652                         if (fail_found == false) {
2653                                 fail_found = true;
2654                         } else if (pass_found == true) {
2655                                 window_found = true;
2656                                 break;
2657                         }
2658                 }
2659         }
2660
2661         rqfd_average = ((max_start + max_end) >> 1);
2662
2663         /*------------------------------------------------------------------
2664          * Make sure we found the valid read passing window.  Halt if not
2665          *-----------------------------------------------------------------*/
2666         if (window_found == false) {
2667                 if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
2668                         putc('\b');
2669                         putc(slash[loopi++ % 8]);
2670
2671                         /* try again from with a different RQFD start value */
2672                         rqfd_start++;
2673                         goto calibration_loop;
2674                 }
2675
2676                 printf("\nERROR: Cannot determine a common read delay for the "
2677                        "DIMM(s) installed.\n");
2678                 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2679                 ppc4xx_ibm_ddr2_register_dump();
2680                 spd_ddr_init_hang ();
2681         }
2682
2683         if (rqfd_average < 0)
2684                 rqfd_average = 0;
2685
2686         if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2687                 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2688
2689         mtsdram(SDRAM_RQDC,
2690                 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2691                 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2692
2693         blank_string(strlen(str));
2694 #endif /* CONFIG_DDR_RQDC_FIXED */
2695
2696         mfsdram(SDRAM_DLCR, val);
2697         debug("%s[%d] DLCR: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2698         mfsdram(SDRAM_RQDC, val);
2699         debug("%s[%d] RQDC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2700         mfsdram(SDRAM_RFDC, val);
2701         debug("%s[%d] RFDC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2702         mfsdram(SDRAM_RDCC, val);
2703         debug("%s[%d] RDCC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2704 }
2705 #else /* calibration test with hardvalues */
2706 /*-----------------------------------------------------------------------------+
2707  * DQS_calibration_process.
2708  *-----------------------------------------------------------------------------*/
2709 static void test(void)
2710 {
2711         unsigned long dimm_num;
2712         unsigned long ecc_temp;
2713         unsigned long i, j;
2714         unsigned long *membase;
2715         unsigned long bxcf[MAXRANKS];
2716         unsigned long val;
2717         char window_found;
2718         char begin_found[MAXDIMMS];
2719         char end_found[MAXDIMMS];
2720         char search_end[MAXDIMMS];
2721         unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2722                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2723                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2724                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2725                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2726                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2727                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2728                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2729                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2730                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2731                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2732                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2733                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2734                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2735                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2736                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2737                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2738
2739         /*------------------------------------------------------------------
2740          * Test to determine the best read clock delay tuning bits.
2741          *
2742          * Before the DDR controller can be used, the read clock delay needs to be
2743          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2744          * This value cannot be hardcoded into the program because it changes
2745          * depending on the board's setup and environment.
2746          * To do this, all delay values are tested to see if they
2747          * work or not.  By doing this, you get groups of fails with groups of
2748          * passing values.  The idea is to find the start and end of a passing
2749          * window and take the center of it to use as the read clock delay.
2750          *
2751          * A failure has to be seen first so that when we hit a pass, we know
2752          * that it is truely the start of the window.  If we get passing values
2753          * to start off with, we don't know if we are at the start of the window.
2754          *
2755          * The code assumes that a failure will always be found.
2756          * If a failure is not found, there is no easy way to get the middle
2757          * of the passing window.  I guess we can pretty much pick any value
2758          * but some values will be better than others.  Since the lowest speed
2759          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2760          * from experimentation it is safe to say you will always have a failure.
2761          *-----------------------------------------------------------------*/
2762         mfsdram(SDRAM_MCOPT1, ecc_temp);
2763         ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2764         mfsdram(SDRAM_MCOPT1, val);
2765         mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2766                 SDRAM_MCOPT1_MCHK_NON);
2767
2768         window_found = false;
2769         begin_found[0] = false;
2770         end_found[0] = false;
2771         search_end[0] = false;
2772         begin_found[1] = false;
2773         end_found[1] = false;
2774         search_end[1] = false;
2775
2776         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2777                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2778
2779                 /* Banks enabled */
2780                 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2781
2782                         /* Bank is enabled */
2783                         membase =
2784                                 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2785
2786                         /*------------------------------------------------------------------
2787                          * Run the short memory test.
2788                          *-----------------------------------------------------------------*/
2789                         for (i = 0; i < NUMMEMTESTS; i++) {
2790                                 for (j = 0; j < NUMMEMWORDS; j++) {
2791                                         membase[j] = test[i][j];
2792                                         ppcDcbf((u32)&(membase[j]));
2793                                 }
2794                                 sync();
2795                                 for (j = 0; j < NUMMEMWORDS; j++) {
2796                                         if (membase[j] != test[i][j]) {
2797                                                 ppcDcbf((u32)&(membase[j]));
2798                                                 break;
2799                                         }
2800                                         ppcDcbf((u32)&(membase[j]));
2801                                 }
2802                                 sync();
2803                                 if (j < NUMMEMWORDS)
2804                                         break;
2805                         }
2806
2807                         /*------------------------------------------------------------------
2808                          * See if the rffd value passed.
2809                          *-----------------------------------------------------------------*/
2810                         if (i < NUMMEMTESTS) {
2811                                 if ((end_found[dimm_num] == false) &&
2812                                     (search_end[dimm_num] == true)) {
2813                                         end_found[dimm_num] = true;
2814                                 }
2815                                 if ((end_found[0] == true) &&
2816                                     (end_found[1] == true))
2817                                         break;
2818                         } else {
2819                                 if (begin_found[dimm_num] == false) {
2820                                         begin_found[dimm_num] = true;
2821                                         search_end[dimm_num] = true;
2822                                 }
2823                         }
2824                 } else {
2825                         begin_found[dimm_num] = true;
2826                         end_found[dimm_num] = true;
2827                 }
2828         }
2829
2830         if ((begin_found[0] == true) && (begin_found[1] == true))
2831                 window_found = true;
2832
2833         /*------------------------------------------------------------------
2834          * Make sure we found the valid read passing window.  Halt if not
2835          *-----------------------------------------------------------------*/
2836         if (window_found == false) {
2837                 printf("ERROR: Cannot determine a common read delay for the "
2838                        "DIMM(s) installed.\n");
2839                 spd_ddr_init_hang ();
2840         }
2841
2842         /*------------------------------------------------------------------
2843          * Restore the ECC variable to what it originally was
2844          *-----------------------------------------------------------------*/
2845         mtsdram(SDRAM_MCOPT1,
2846                 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2847                 | ecc_temp);
2848 }
2849 #endif /* !HARD_CODED_DQS */
2850 #endif /* !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) */
2851
2852 #else /* CONFIG_SPD_EEPROM */
2853
2854 /*-----------------------------------------------------------------------------
2855  * Function:    initdram
2856  * Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller.
2857  *              The configuration is performed using static, compile-
2858  *              time parameters.
2859  *              Configures the PPC405EX(r) and PPC460EX/GT
2860  *---------------------------------------------------------------------------*/
2861 phys_size_t initdram(int board_type)
2862 {
2863         /*
2864          * Only run this SDRAM init code once. For NAND booting
2865          * targets like Kilauea, we call initdram() early from the
2866          * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
2867          * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
2868          * which calls initdram() again. This time the controller
2869          * mustn't be reconfigured again since we're already running
2870          * from SDRAM.
2871          */
2872 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
2873         unsigned long val;
2874
2875 #if defined(CONFIG_440)
2876         mtdcr(SDRAM_R0BAS,      CONFIG_SYS_SDRAM_R0BAS);
2877         mtdcr(SDRAM_R1BAS,      CONFIG_SYS_SDRAM_R1BAS);
2878         mtdcr(SDRAM_R2BAS,      CONFIG_SYS_SDRAM_R2BAS);
2879         mtdcr(SDRAM_R3BAS,      CONFIG_SYS_SDRAM_R3BAS);
2880         mtdcr(SDRAM_PLBADDULL,  CONFIG_SYS_SDRAM_PLBADDULL);    /* MQ0_BAUL */
2881         mtdcr(SDRAM_PLBADDUHB,  CONFIG_SYS_SDRAM_PLBADDUHB);    /* MQ0_BAUH */
2882         mtdcr(SDRAM_CONF1LL,    CONFIG_SYS_SDRAM_CONF1LL);
2883         mtdcr(SDRAM_CONF1HB,    CONFIG_SYS_SDRAM_CONF1HB);
2884         mtdcr(SDRAM_CONFPATHB,  CONFIG_SYS_SDRAM_CONFPATHB);
2885 #endif
2886
2887         /* Set Memory Bank Configuration Registers */
2888
2889         mtsdram(SDRAM_MB0CF, CONFIG_SYS_SDRAM0_MB0CF);
2890         mtsdram(SDRAM_MB1CF, CONFIG_SYS_SDRAM0_MB1CF);
2891         mtsdram(SDRAM_MB2CF, CONFIG_SYS_SDRAM0_MB2CF);
2892         mtsdram(SDRAM_MB3CF, CONFIG_SYS_SDRAM0_MB3CF);
2893
2894         /* Set Memory Clock Timing Register */
2895
2896         mtsdram(SDRAM_CLKTR, CONFIG_SYS_SDRAM0_CLKTR);
2897
2898         /* Set Refresh Time Register */
2899
2900         mtsdram(SDRAM_RTR, CONFIG_SYS_SDRAM0_RTR);
2901
2902         /* Set SDRAM Timing Registers */
2903
2904         mtsdram(SDRAM_SDTR1, CONFIG_SYS_SDRAM0_SDTR1);
2905         mtsdram(SDRAM_SDTR2, CONFIG_SYS_SDRAM0_SDTR2);
2906         mtsdram(SDRAM_SDTR3, CONFIG_SYS_SDRAM0_SDTR3);
2907
2908         /* Set Mode and Extended Mode Registers */
2909
2910         mtsdram(SDRAM_MMODE, CONFIG_SYS_SDRAM0_MMODE);
2911         mtsdram(SDRAM_MEMODE, CONFIG_SYS_SDRAM0_MEMODE);
2912
2913         /* Set Memory Controller Options 1 Register */
2914
2915         mtsdram(SDRAM_MCOPT1, CONFIG_SYS_SDRAM0_MCOPT1);
2916
2917         /* Set Manual Initialization Control Registers */
2918
2919         mtsdram(SDRAM_INITPLR0, CONFIG_SYS_SDRAM0_INITPLR0);
2920         mtsdram(SDRAM_INITPLR1, CONFIG_SYS_SDRAM0_INITPLR1);
2921         mtsdram(SDRAM_INITPLR2, CONFIG_SYS_SDRAM0_INITPLR2);
2922         mtsdram(SDRAM_INITPLR3, CONFIG_SYS_SDRAM0_INITPLR3);
2923         mtsdram(SDRAM_INITPLR4, CONFIG_SYS_SDRAM0_INITPLR4);
2924         mtsdram(SDRAM_INITPLR5, CONFIG_SYS_SDRAM0_INITPLR5);
2925         mtsdram(SDRAM_INITPLR6, CONFIG_SYS_SDRAM0_INITPLR6);
2926         mtsdram(SDRAM_INITPLR7, CONFIG_SYS_SDRAM0_INITPLR7);
2927         mtsdram(SDRAM_INITPLR8, CONFIG_SYS_SDRAM0_INITPLR8);
2928         mtsdram(SDRAM_INITPLR9, CONFIG_SYS_SDRAM0_INITPLR9);
2929         mtsdram(SDRAM_INITPLR10, CONFIG_SYS_SDRAM0_INITPLR10);
2930         mtsdram(SDRAM_INITPLR11, CONFIG_SYS_SDRAM0_INITPLR11);
2931         mtsdram(SDRAM_INITPLR12, CONFIG_SYS_SDRAM0_INITPLR12);
2932         mtsdram(SDRAM_INITPLR13, CONFIG_SYS_SDRAM0_INITPLR13);
2933         mtsdram(SDRAM_INITPLR14, CONFIG_SYS_SDRAM0_INITPLR14);
2934         mtsdram(SDRAM_INITPLR15, CONFIG_SYS_SDRAM0_INITPLR15);
2935
2936         /* Set On-Die Termination Registers */
2937
2938         mtsdram(SDRAM_CODT, CONFIG_SYS_SDRAM0_CODT);
2939         mtsdram(SDRAM_MODT0, CONFIG_SYS_SDRAM0_MODT0);
2940         mtsdram(SDRAM_MODT1, CONFIG_SYS_SDRAM0_MODT1);
2941
2942         /* Set Write Timing Register */
2943
2944         mtsdram(SDRAM_WRDTR, CONFIG_SYS_SDRAM0_WRDTR);
2945
2946         /*
2947          * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
2948          * SDRAM0_MCOPT2[IPTR] = 1
2949          */
2950
2951         mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT |
2952                                SDRAM_MCOPT2_IPTR_EXECUTE));
2953
2954         /*
2955          * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
2956          * completion of initialization.
2957          */
2958
2959         do {
2960                 mfsdram(SDRAM_MCSTAT, val);
2961         } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
2962
2963         /* Set Delay Control Registers */
2964
2965         mtsdram(SDRAM_DLCR, CONFIG_SYS_SDRAM0_DLCR);
2966
2967 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
2968         mtsdram(SDRAM_RDCC, CONFIG_SYS_SDRAM0_RDCC);
2969         mtsdram(SDRAM_RQDC, CONFIG_SYS_SDRAM0_RQDC);
2970         mtsdram(SDRAM_RFDC, CONFIG_SYS_SDRAM0_RFDC);
2971 #endif /* !CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
2972
2973         /*
2974          * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
2975          */
2976
2977         mfsdram(SDRAM_MCOPT2, val);
2978         mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
2979
2980 #if defined(CONFIG_440)
2981         /*
2982          * Program TLB entries with caches enabled, for best performace
2983          * while auto-calibrating and ECC generation
2984          */
2985         program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), 0);
2986 #endif
2987
2988 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
2989 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
2990         /*------------------------------------------------------------------
2991          | DQS calibration.
2992          +-----------------------------------------------------------------*/
2993         DQS_autocalibration();
2994 #endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
2995 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
2996
2997         /*
2998          * Now complete RDSS configuration as mentioned on page 7 of the AMCC
2999          * PowerPC440SP/SPe DDR2 application note:
3000          * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
3001          */
3002         update_rdcc();
3003
3004 #if defined(CONFIG_DDR_ECC)
3005         do_program_ecc(0);
3006 #endif /* defined(CONFIG_DDR_ECC) */
3007
3008 #if defined(CONFIG_440)
3009         /*
3010          * Now after initialization (auto-calibration and ECC generation)
3011          * remove the TLB entries with caches enabled and program again with
3012          * desired cache functionality
3013          */
3014         remove_tlb(0, (CONFIG_SYS_MBYTES_SDRAM << 20));
3015         program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), MY_TLB_WORD2_I_ENABLE);
3016 #endif
3017
3018         ppc4xx_ibm_ddr2_register_dump();
3019
3020 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
3021         /*
3022          * Clear potential errors resulting from auto-calibration.
3023          * If not done, then we could get an interrupt later on when
3024          * exceptions are enabled.
3025          */
3026         set_mcsr(get_mcsr());
3027 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3028
3029 #endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
3030
3031         return (CONFIG_SYS_MBYTES_SDRAM << 20);
3032 }
3033 #endif /* CONFIG_SPD_EEPROM */
3034
3035 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
3036 #if defined(CONFIG_440)
3037 u32 mfdcr_any(u32 dcr)
3038 {
3039         u32 val;
3040
3041         switch (dcr) {
3042         case SDRAM_R0BAS + 0:
3043                 val = mfdcr(SDRAM_R0BAS + 0);
3044                 break;
3045         case SDRAM_R0BAS + 1:
3046                 val = mfdcr(SDRAM_R0BAS + 1);
3047                 break;
3048         case SDRAM_R0BAS + 2:
3049                 val = mfdcr(SDRAM_R0BAS + 2);
3050                 break;
3051         case SDRAM_R0BAS + 3:
3052                 val = mfdcr(SDRAM_R0BAS + 3);
3053                 break;
3054         default:
3055                 printf("DCR %d not defined in case statement!!!\n", dcr);
3056                 val = 0; /* just to satisfy the compiler */
3057         }
3058
3059         return val;
3060 }
3061
3062 void mtdcr_any(u32 dcr, u32 val)
3063 {
3064         switch (dcr) {
3065         case SDRAM_R0BAS + 0:
3066                 mtdcr(SDRAM_R0BAS + 0, val);
3067                 break;
3068         case SDRAM_R0BAS + 1:
3069                 mtdcr(SDRAM_R0BAS + 1, val);
3070                 break;
3071         case SDRAM_R0BAS + 2:
3072                 mtdcr(SDRAM_R0BAS + 2, val);
3073                 break;
3074         case SDRAM_R0BAS + 3:
3075                 mtdcr(SDRAM_R0BAS + 3, val);
3076                 break;
3077         default:
3078                 printf("DCR %d not defined in case statement!!!\n", dcr);
3079         }
3080 }
3081 #endif /* defined(CONFIG_440) */
3082 #endif /* !defined(CONFIG_NAND_U_BOOT) &&  !defined(CONFIG_NAND_SPL) */
3083
3084 inline void ppc4xx_ibm_ddr2_register_dump(void)
3085 {
3086 #if defined(DEBUG)
3087         printf("\nPPC4xx IBM DDR2 Register Dump:\n");
3088
3089 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3090      defined(CONFIG_460EX) || defined(CONFIG_460GT))
3091         PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R0BAS);
3092         PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R1BAS);
3093         PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R2BAS);
3094         PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R3BAS);
3095 #endif /* (defined(CONFIG_440SP) || ... */
3096 #if defined(CONFIG_405EX)
3097         PPC4xx_IBM_DDR2_DUMP_REGISTER(BESR);
3098         PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARL);
3099         PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARH);
3100         PPC4xx_IBM_DDR2_DUMP_REGISTER(WMIRQ);
3101         PPC4xx_IBM_DDR2_DUMP_REGISTER(PLBOPT);
3102         PPC4xx_IBM_DDR2_DUMP_REGISTER(PUABA);
3103 #endif /* defined(CONFIG_405EX) */
3104         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB0CF);
3105         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB1CF);
3106         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB2CF);
3107         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB3CF);
3108         PPC4xx_IBM_DDR2_DUMP_REGISTER(MCSTAT);
3109         PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT1);
3110         PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT2);
3111         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT0);
3112         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT1);
3113         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT2);
3114         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT3);
3115         PPC4xx_IBM_DDR2_DUMP_REGISTER(CODT);
3116 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3117      defined(CONFIG_460EX) || defined(CONFIG_460GT))
3118         PPC4xx_IBM_DDR2_DUMP_REGISTER(VVPR);
3119         PPC4xx_IBM_DDR2_DUMP_REGISTER(OPARS);
3120         /*
3121          * OPART is only used as a trigger register.
3122          *
3123          * No data is contained in this register, and reading or writing
3124          * to is can cause bad things to happen (hangs). Just skip it and
3125          * report "N/A".
3126          */
3127         printf("%20s = N/A\n", "SDRAM_OPART");
3128 #endif /* defined(CONFIG_440SP) || ... */
3129         PPC4xx_IBM_DDR2_DUMP_REGISTER(RTR);
3130         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR0);
3131         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR1);
3132         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR2);
3133         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR3);
3134         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR4);
3135         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR5);
3136         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR6);
3137         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR7);
3138         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR8);
3139         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR9);
3140         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR10);
3141         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR11);
3142         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR12);
3143         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR13);
3144         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR14);
3145         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR15);
3146         PPC4xx_IBM_DDR2_DUMP_REGISTER(RQDC);
3147         PPC4xx_IBM_DDR2_DUMP_REGISTER(RFDC);
3148         PPC4xx_IBM_DDR2_DUMP_REGISTER(RDCC);
3149         PPC4xx_IBM_DDR2_DUMP_REGISTER(DLCR);
3150         PPC4xx_IBM_DDR2_DUMP_REGISTER(CLKTR);
3151         PPC4xx_IBM_DDR2_DUMP_REGISTER(WRDTR);
3152         PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR1);
3153         PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR2);
3154         PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR3);
3155         PPC4xx_IBM_DDR2_DUMP_REGISTER(MMODE);
3156         PPC4xx_IBM_DDR2_DUMP_REGISTER(MEMODE);
3157         PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCES);
3158 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3159      defined(CONFIG_460EX) || defined(CONFIG_460GT))
3160         PPC4xx_IBM_DDR2_DUMP_REGISTER(CID);
3161 #endif /* defined(CONFIG_440SP) || ... */
3162         PPC4xx_IBM_DDR2_DUMP_REGISTER(RID);
3163         PPC4xx_IBM_DDR2_DUMP_REGISTER(FCSR);
3164         PPC4xx_IBM_DDR2_DUMP_REGISTER(RTSR);
3165 #endif /* defined(DEBUG) */
3166 }