arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c

   1 /*
   2  * arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
   3  * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
   4  * DDR2 controller (non Denali Core). Those currently are:
   5  *
   6  * 405:         405EX(r)
   7  * 440/460:     440SP/440SPe/460EX/460GT
   8  *
   9  * Copyright (c) 2008 Nuovation System Designs, LLC
  10  *   Grant Erickson <gerickson@nuovations.com>
  11
  12  * (C) Copyright 2007-2009
  13  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  14  *
  15  * COPYRIGHT   AMCC   CORPORATION 2004
  16  *
  17  * SPDX-License-Identifier:     GPL-2.0+
  18  */
  19
  20 /* define DEBUG for debugging output (obviously ;-)) */
  21 #if 0
  22 #define DEBUG
  23 #endif
  24
  25 #include <common.h>
  26 #include <command.h>
  27 #include <asm/ppc4xx.h>
  28 #include <i2c.h>
  29 #include <asm/io.h>
  30 #include <asm/processor.h>
  31 #include <asm/mmu.h>
  32 #include <asm/cache.h>
  33
  34 #include "ecc.h"
  35
  36 #define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic)                         \
  37         do {                                                            \
  38                 u32 data;                                               \
  39                 mfsdram(SDRAM_##mnemonic, data);                        \
  40                 printf("%20s[%02x] = 0x%08X\n",                         \
  41                        "SDRAM_" #mnemonic, SDRAM_##mnemonic, data);     \
  42         } while (0)
  43
  44 #define PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(mnemonic)                      \
  45         do {                                                            \
  46                 u32 data;                                               \
  47                 data = mfdcr(SDRAM_##mnemonic);                         \
  48                 printf("%20s[%02x] = 0x%08X\n",                         \
  49                        "SDRAM_" #mnemonic, SDRAM_##mnemonic, data);     \
  50         } while (0)
  51
  52 static void update_rdcc(void)
  53 {
  54         u32 val;
  55
  56         /*
  57          * Complete RDSS configuration as mentioned on page 7 of the AMCC
  58          * PowerPC440SP/SPe DDR2 application note:
  59          * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
  60          *
  61          * Or item #10 "10. Complete RDSS configuration" in chapter
  62          * "22.2.9 SDRAM Initialization" of AMCC PPC460EX/EXr/GT users
  63          * manual.
  64          */
  65         mfsdram(SDRAM_RTSR, val);
  66         if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
  67                 mfsdram(SDRAM_RDCC, val);
  68                 if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
  69                         val += 0x40000000;
  70                         mtsdram(SDRAM_RDCC, val);
  71                 }
  72         }
  73 }
  74
  75 #if defined(CONFIG_440)
  76 /*
  77  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2
  78  * memory region. Right now the cache should still be disabled in U-Boot
  79  * because of the EMAC driver, that need its buffer descriptor to be located
  80  * in non cached memory.
  81  *
  82  * If at some time this restriction doesn't apply anymore, just define
  83  * CONFIG_4xx_DCACHE in the board config file and this code should setup
  84  * everything correctly.
  85  */
  86 #ifdef CONFIG_4xx_DCACHE
  87 /* enable caching on SDRAM */
  88 #define MY_TLB_WORD2_I_ENABLE           0
  89 #else
  90 /* disable caching on SDRAM */
  91 #define MY_TLB_WORD2_I_ENABLE           TLB_WORD2_I_ENABLE
  92 #endif /* CONFIG_4xx_DCACHE */
  93
  94 void dcbz_area(u32 start_address, u32 num_bytes);
  95 #endif /* CONFIG_440 */
  96
  97 #define MAXRANKS        4
  98 #define MAXBXCF         4
  99
 100 #define MULDIV64(m1, m2, d)     (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
 101
 102 /*-----------------------------------------------------------------------------+
 103  * sdram_memsize
 104  *-----------------------------------------------------------------------------*/
 105 phys_size_t sdram_memsize(void)
 106 {
 107         phys_size_t mem_size;
 108         unsigned long mcopt2;
 109         unsigned long mcstat;
 110         unsigned long mb0cf;
 111         unsigned long sdsz;
 112         unsigned long i;
 113
 114         mem_size = 0;
 115
 116         mfsdram(SDRAM_MCOPT2, mcopt2);
 117         mfsdram(SDRAM_MCSTAT, mcstat);
 118
 119         /* DDR controller must be enabled and not in self-refresh. */
 120         /* Otherwise memsize is zero. */
 121         if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
 122             && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
 123             && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
 124                 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
 125                 for (i = 0; i < MAXBXCF; i++) {
 126                         mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
 127                         /* Banks enabled */
 128                         if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
 129 #if defined(CONFIG_440)
 130                                 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
 131 #else
 132                                 sdsz = mb0cf & SDRAM_RXBAS_SDSZ_MASK;
 133 #endif
 134                                 switch(sdsz) {
 135                                 case SDRAM_RXBAS_SDSZ_8:
 136                                         mem_size+=8;
 137                                         break;
 138                                 case SDRAM_RXBAS_SDSZ_16:
 139                                         mem_size+=16;
 140                                         break;
 141                                 case SDRAM_RXBAS_SDSZ_32:
 142                                         mem_size+=32;
 143                                         break;
 144                                 case SDRAM_RXBAS_SDSZ_64:
 145                                         mem_size+=64;
 146                                         break;
 147                                 case SDRAM_RXBAS_SDSZ_128:
 148                                         mem_size+=128;
 149                                         break;
 150                                 case SDRAM_RXBAS_SDSZ_256:
 151                                         mem_size+=256;
 152                                         break;
 153                                 case SDRAM_RXBAS_SDSZ_512:
 154                                         mem_size+=512;
 155                                         break;
 156                                 case SDRAM_RXBAS_SDSZ_1024:
 157                                         mem_size+=1024;
 158                                         break;
 159                                 case SDRAM_RXBAS_SDSZ_2048:
 160                                         mem_size+=2048;
 161                                         break;
 162                                 case SDRAM_RXBAS_SDSZ_4096:
 163                                         mem_size+=4096;
 164                                         break;
 165                                 default:
 166                                         printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n"
 167                                                , sdsz);
 168                                         mem_size=0;
 169                                         break;
 170                                 }
 171                         }
 172                 }
 173         }
 174
 175         return mem_size << 20;
 176 }
 177
 178 /*-----------------------------------------------------------------------------+
 179  * is_ecc_enabled
 180  *-----------------------------------------------------------------------------*/
 181 static unsigned long is_ecc_enabled(void)
 182 {
 183         unsigned long val;
 184
 185         mfsdram(SDRAM_MCOPT1, val);
 186
 187         return SDRAM_MCOPT1_MCHK_CHK_DECODE(val);
 188 }
 189
 190 /*-----------------------------------------------------------------------------+
 191  * board_add_ram_info
 192  *-----------------------------------------------------------------------------*/
 193 void board_add_ram_info(int use_default)
 194 {
 195         PPC4xx_SYS_INFO board_cfg;
 196         u32 val;
 197
 198         if (is_ecc_enabled())
 199                 puts(" (ECC");
 200         else
 201                 puts(" (ECC not");
 202
 203         get_sys_info(&board_cfg);
 204
 205 #if defined(CONFIG_405EX)
 206         val = board_cfg.freqPLB;
 207 #else
 208         mfsdr(SDR0_DDR0, val);
 209         val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
 210 #endif
 211         printf(" enabled, %d MHz", (val * 2) / 1000000);
 212
 213         mfsdram(SDRAM_MMODE, val);
 214         val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
 215         printf(", CL%d)", val);
 216 }
 217
 218 #if defined(CONFIG_SPD_EEPROM)
 219
 220 /*-----------------------------------------------------------------------------+
 221  * Defines
 222  *-----------------------------------------------------------------------------*/
 223 #define SDRAM_DDR1      1
 224 #define SDRAM_DDR2      2
 225 #define SDRAM_NONE      0
 226
 227 #define MAXDIMMS        2
 228 #define MAX_SPD_BYTES   256   /* Max number of bytes on the DIMM's SPD EEPROM */
 229
 230 #define ONE_BILLION     1000000000
 231
 232 #define CMD_NOP         (7 << 19)
 233 #define CMD_PRECHARGE   (2 << 19)
 234 #define CMD_REFRESH     (1 << 19)
 235 #define CMD_EMR         (0 << 19)
 236 #define CMD_READ        (5 << 19)
 237 #define CMD_WRITE       (4 << 19)
 238
 239 #define SELECT_MR       (0 << 16)
 240 #define SELECT_EMR      (1 << 16)
 241 #define SELECT_EMR2     (2 << 16)
 242 #define SELECT_EMR3     (3 << 16)
 243
 244 /* MR */
 245 #define DLL_RESET       0x00000100
 246
 247 #define WRITE_RECOV_2   (1 << 9)
 248 #define WRITE_RECOV_3   (2 << 9)
 249 #define WRITE_RECOV_4   (3 << 9)
 250 #define WRITE_RECOV_5   (4 << 9)
 251 #define WRITE_RECOV_6   (5 << 9)
 252
 253 #define BURST_LEN_4     0x00000002
 254
 255 /* EMR */
 256 #define ODT_0_OHM       0x00000000
 257 #define ODT_50_OHM      0x00000044
 258 #define ODT_75_OHM      0x00000004
 259 #define ODT_150_OHM     0x00000040
 260
 261 #define ODS_FULL        0x00000000
 262 #define ODS_REDUCED     0x00000002
 263 #define OCD_CALIB_DEF   0x00000380
 264
 265 /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
 266 #define ODT_EB0R        (0x80000000 >> 8)
 267 #define ODT_EB0W        (0x80000000 >> 7)
 268 #define CALC_ODT_R(n)   (ODT_EB0R << (n << 1))
 269 #define CALC_ODT_W(n)   (ODT_EB0W << (n << 1))
 270 #define CALC_ODT_RW(n)  (CALC_ODT_R(n) | CALC_ODT_W(n))
 271
 272 /* Defines for the Read Cycle Delay test */
 273 #define NUMMEMTESTS     8
 274 #define NUMMEMWORDS     8
 275 #define NUMLOOPS        64              /* memory test loops */
 276
 277 /*
 278  * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
 279  * To support such configurations, we "only" map the first 2GB via the TLB's. We
 280  * need some free virtual address space for the remaining peripherals like, SoC
 281  * devices, FLASH etc.
 282  *
 283  * Note that ECC is currently not supported on configurations with more than 2GB
 284  * SDRAM. This is because we only map the first 2GB on such systems, and therefore
 285  * the ECC parity byte of the remaining area can't be written.
 286  */
 287
 288 /*
 289  * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
 290  */
 291 void __spd_ddr_init_hang (void)
 292 {
 293         hang ();
 294 }
 295 void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
 296
 297 /*
 298  * To provide an interface for board specific config values in this common
 299  * DDR setup code, we implement he "weak" default functions here. They return
 300  * the default value back to the caller.
 301  *
 302  * Please see include/configs/yucca.h for an example fora board specific
 303  * implementation.
 304  */
 305 u32 __ddr_wrdtr(u32 default_val)
 306 {
 307         return default_val;
 308 }
 309 u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
 310
 311 u32 __ddr_clktr(u32 default_val)
 312 {
 313         return default_val;
 314 }
 315 u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
 316
 317
 318 /* Private Structure Definitions */
 319
 320 /* enum only to ease code for cas latency setting */
 321 typedef enum ddr_cas_id {
 322         DDR_CAS_2      = 20,
 323         DDR_CAS_2_5    = 25,
 324         DDR_CAS_3      = 30,
 325         DDR_CAS_4      = 40,
 326         DDR_CAS_5      = 50
 327 } ddr_cas_id_t;
 328
 329 /*-----------------------------------------------------------------------------+
 330  * Prototypes
 331  *-----------------------------------------------------------------------------*/
 332 static void get_spd_info(unsigned long *dimm_populated,
 333                          unsigned char *iic0_dimm_addr,
 334                          unsigned long num_dimm_banks);
 335 static void check_mem_type(unsigned long *dimm_populated,
 336                            unsigned char *iic0_dimm_addr,
 337                            unsigned long num_dimm_banks);
 338 static void check_frequency(unsigned long *dimm_populated,
 339                             unsigned char *iic0_dimm_addr,
 340                             unsigned long num_dimm_banks);
 341 static void check_rank_number(unsigned long *dimm_populated,
 342                               unsigned char *iic0_dimm_addr,
 343                               unsigned long num_dimm_banks);
 344 static void check_voltage_type(unsigned long *dimm_populated,
 345                                unsigned char *iic0_dimm_addr,
 346                                unsigned long num_dimm_banks);
 347 static void program_memory_queue(unsigned long *dimm_populated,
 348                                  unsigned char *iic0_dimm_addr,
 349                                  unsigned long num_dimm_banks);
 350 static void program_codt(unsigned long *dimm_populated,
 351                          unsigned char *iic0_dimm_addr,
 352                          unsigned long num_dimm_banks);
 353 static void program_mode(unsigned long *dimm_populated,
 354                          unsigned char *iic0_dimm_addr,
 355                          unsigned long num_dimm_banks,
 356                          ddr_cas_id_t *selected_cas,
 357                          int *write_recovery);
 358 static void program_tr(unsigned long *dimm_populated,
 359                        unsigned char *iic0_dimm_addr,
 360                        unsigned long num_dimm_banks);
 361 static void program_rtr(unsigned long *dimm_populated,
 362                         unsigned char *iic0_dimm_addr,
 363                         unsigned long num_dimm_banks);
 364 static void program_bxcf(unsigned long *dimm_populated,
 365                          unsigned char *iic0_dimm_addr,
 366                          unsigned long num_dimm_banks);
 367 static void program_copt1(unsigned long *dimm_populated,
 368                           unsigned char *iic0_dimm_addr,
 369                           unsigned long num_dimm_banks);
 370 static void program_initplr(unsigned long *dimm_populated,
 371                             unsigned char *iic0_dimm_addr,
 372                             unsigned long num_dimm_banks,
 373                             ddr_cas_id_t selected_cas,
 374                             int write_recovery);
 375 #ifdef CONFIG_DDR_ECC
 376 static void program_ecc(unsigned long *dimm_populated,
 377                         unsigned char *iic0_dimm_addr,
 378                         unsigned long num_dimm_banks,
 379                         unsigned long tlb_word2_i_value);
 380 #endif
 381 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
 382 static void program_DQS_calibration(unsigned long *dimm_populated,
 383                                 unsigned char *iic0_dimm_addr,
 384                                 unsigned long num_dimm_banks);
 385 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
 386 static void     test(void);
 387 #else
 388 static void     DQS_calibration_process(void);
 389 #endif
 390 #endif
 391
 392 static unsigned char spd_read(uchar chip, uint addr)
 393 {
 394         unsigned char data[2];
 395
 396         if (i2c_probe(chip) == 0)
 397                 if (i2c_read(chip, addr, 1, data, 1) == 0)
 398                         return data[0];
 399
 400         return 0;
 401 }
 402
 403 /*-----------------------------------------------------------------------------+
 404  * initdram.  Initializes the 440SP Memory Queue and DDR SDRAM controller.
 405  * Note: This routine runs from flash with a stack set up in the chip's
 406  * sram space.  It is important that the routine does not require .sbss, .bss or
 407  * .data sections.  It also cannot call routines that require these sections.
 408  *-----------------------------------------------------------------------------*/
 409 /*-----------------------------------------------------------------------------
 410  * Function:     initdram
 411  * Description:  Configures SDRAM memory banks for DDR operation.
 412  *               Auto Memory Configuration option reads the DDR SDRAM EEPROMs
 413  *               via the IIC bus and then configures the DDR SDRAM memory
 414  *               banks appropriately. If Auto Memory Configuration is
 415  *               not used, it is assumed that no DIMM is plugged
 416  *-----------------------------------------------------------------------------*/
 417 phys_size_t initdram(int board_type)
 418 {
 419         unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 420         unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE};
 421         unsigned long num_dimm_banks;           /* on board dimm banks */
 422         unsigned long val;
 423         ddr_cas_id_t selected_cas = DDR_CAS_5;  /* preset to silence compiler */
 424         int write_recovery;
 425         phys_size_t dram_size = 0;
 426
 427         if (IS_ENABLED(CONFIG_SYS_RAMBOOT)) {
 428                 /*
 429                  * Reduce RAM size to avoid overwriting memory used by
 430                  * current stack? Not sure what is happening.
 431                  */
 432                 return sdram_memsize() / 2;
 433         }
 434
 435         num_dimm_banks = sizeof(iic0_dimm_addr);
 436
 437         /*------------------------------------------------------------------
 438          * Reset the DDR-SDRAM controller.
 439          *-----------------------------------------------------------------*/
 440         mtsdr(SDR0_SRST, SDR0_SRST0_DMC);
 441         mtsdr(SDR0_SRST, 0x00000000);
 442
 443         /*
 444          * Make sure I2C controller is initialized
 445          * before continuing.
 446          */
 447
 448         /* switch to correct I2C bus */
 449         i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
 450
 451         /*------------------------------------------------------------------
 452          * Clear out the serial presence detect buffers.
 453          * Perform IIC reads from the dimm.  Fill in the spds.
 454          * Check to see if the dimm slots are populated
 455          *-----------------------------------------------------------------*/
 456         get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 457
 458         /*------------------------------------------------------------------
 459          * Check the memory type for the dimms plugged.
 460          *-----------------------------------------------------------------*/
 461         check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 462
 463         /*------------------------------------------------------------------
 464          * Check the frequency supported for the dimms plugged.
 465          *-----------------------------------------------------------------*/
 466         check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 467
 468         /*------------------------------------------------------------------
 469          * Check the total rank number.
 470          *-----------------------------------------------------------------*/
 471         check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 472
 473         /*------------------------------------------------------------------
 474          * Check the voltage type for the dimms plugged.
 475          *-----------------------------------------------------------------*/
 476         check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 477
 478         /*------------------------------------------------------------------
 479          * Program SDRAM controller options 2 register
 480          * Except Enabling of the memory controller.
 481          *-----------------------------------------------------------------*/
 482         mfsdram(SDRAM_MCOPT2, val);
 483         mtsdram(SDRAM_MCOPT2,
 484                 (val &
 485                  ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
 486                    SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
 487                    SDRAM_MCOPT2_ISIE_MASK))
 488                 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
 489                    SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
 490                    SDRAM_MCOPT2_ISIE_ENABLE));
 491
 492         /*------------------------------------------------------------------
 493          * Program SDRAM controller options 1 register
 494          * Note: Does not enable the memory controller.
 495          *-----------------------------------------------------------------*/
 496         program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 497
 498         /*------------------------------------------------------------------
 499          * Set the SDRAM Controller On Die Termination Register
 500          *-----------------------------------------------------------------*/
 501         program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 502
 503         /*------------------------------------------------------------------
 504          * Program SDRAM refresh register.
 505          *-----------------------------------------------------------------*/
 506         program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 507
 508         /*------------------------------------------------------------------
 509          * Program SDRAM mode register.
 510          *-----------------------------------------------------------------*/
 511         program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 512                      &selected_cas, &write_recovery);
 513
 514         /*------------------------------------------------------------------
 515          * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
 516          *-----------------------------------------------------------------*/
 517         mfsdram(SDRAM_WRDTR, val);
 518         mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
 519                 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
 520
 521         /*------------------------------------------------------------------
 522          * Set the SDRAM Clock Timing Register
 523          *-----------------------------------------------------------------*/
 524         mfsdram(SDRAM_CLKTR, val);
 525         mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
 526                 ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
 527
 528         /*------------------------------------------------------------------
 529          * Program the BxCF registers.
 530          *-----------------------------------------------------------------*/
 531         program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 532
 533         /*------------------------------------------------------------------
 534          * Program SDRAM timing registers.
 535          *-----------------------------------------------------------------*/
 536         program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 537
 538         /*------------------------------------------------------------------
 539          * Set the Extended Mode register
 540          *-----------------------------------------------------------------*/
 541         mfsdram(SDRAM_MEMODE, val);
 542         mtsdram(SDRAM_MEMODE,
 543                 (val & ~(SDRAM_MEMODE_DIC_MASK  | SDRAM_MEMODE_DLL_MASK |
 544                          SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
 545                 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
 546                  | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
 547
 548         /*------------------------------------------------------------------
 549          * Program Initialization preload registers.
 550          *-----------------------------------------------------------------*/
 551         program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 552                         selected_cas, write_recovery);
 553
 554         /*------------------------------------------------------------------
 555          * Delay to ensure 200usec have elapsed since reset.
 556          *-----------------------------------------------------------------*/
 557         udelay(400);
 558
 559         /*------------------------------------------------------------------
 560          * Set the memory queue core base addr.
 561          *-----------------------------------------------------------------*/
 562         program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 563
 564         /*------------------------------------------------------------------
 565          * Program SDRAM controller options 2 register
 566          * Enable the memory controller.
 567          *-----------------------------------------------------------------*/
 568         mfsdram(SDRAM_MCOPT2, val);
 569         mtsdram(SDRAM_MCOPT2,
 570                 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
 571                          SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
 572                          SDRAM_MCOPT2_IPTR_EXECUTE);
 573
 574         /*------------------------------------------------------------------
 575          * Wait for IPTR_EXECUTE init sequence to complete.
 576          *-----------------------------------------------------------------*/
 577         do {
 578                 mfsdram(SDRAM_MCSTAT, val);
 579         } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
 580
 581         /* enable the controller only after init sequence completes */
 582         mfsdram(SDRAM_MCOPT2, val);
 583         mtsdram(SDRAM_MCOPT2, (val | SDRAM_MCOPT2_DCEN_ENABLE));
 584
 585         /* Make sure delay-line calibration is done before proceeding */
 586         do {
 587                 mfsdram(SDRAM_DLCR, val);
 588         } while (!(val & SDRAM_DLCR_DLCS_COMPLETE));
 589
 590         /* get installed memory size */
 591         dram_size = sdram_memsize();
 592
 593         /*
 594          * Limit size to 2GB
 595          */
 596         if (dram_size > CONFIG_MAX_MEM_MAPPED)
 597                 dram_size = CONFIG_MAX_MEM_MAPPED;
 598
 599         /* and program tlb entries for this size (dynamic) */
 600
 601         /*
 602          * Program TLB entries with caches enabled, for best performace
 603          * while auto-calibrating and ECC generation
 604          */
 605         program_tlb(0, 0, dram_size, 0);
 606
 607         /*------------------------------------------------------------------
 608          * DQS calibration.
 609          *-----------------------------------------------------------------*/
 610 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
 611         DQS_autocalibration();
 612 #else
 613         program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 614 #endif
 615         /*
 616          * Now complete RDSS configuration as mentioned on page 7 of the AMCC
 617          * PowerPC440SP/SPe DDR2 application note:
 618          * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
 619          */
 620         update_rdcc();
 621
 622 #ifdef CONFIG_DDR_ECC
 623         /*------------------------------------------------------------------
 624          * If ecc is enabled, initialize the parity bits.
 625          *-----------------------------------------------------------------*/
 626         program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
 627 #endif
 628
 629         /*
 630          * Flush the dcache before removing the TLB with caches
 631          * enabled. Otherwise this might lead to problems later on,
 632          * e.g. while booting Linux (as seen on ICON-440SPe).
 633          */
 634         flush_dcache();
 635
 636         /*
 637          * Now after initialization (auto-calibration and ECC generation)
 638          * remove the TLB entries with caches enabled and program again with
 639          * desired cache functionality
 640          */
 641         remove_tlb(0, dram_size);
 642         program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
 643
 644         ppc4xx_ibm_ddr2_register_dump();
 645
 646         /*
 647          * Clear potential errors resulting from auto-calibration.
 648          * If not done, then we could get an interrupt later on when
 649          * exceptions are enabled.
 650          */
 651         set_mcsr(get_mcsr());
 652
 653         return sdram_memsize();
 654 }
 655
 656 static void get_spd_info(unsigned long *dimm_populated,
 657                          unsigned char *iic0_dimm_addr,
 658                          unsigned long num_dimm_banks)
 659 {
 660         unsigned long dimm_num;
 661         unsigned long dimm_found;
 662         unsigned char num_of_bytes;
 663         unsigned char total_size;
 664
 665         dimm_found = false;
 666         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 667                 num_of_bytes = 0;
 668                 total_size = 0;
 669
 670                 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
 671                 debug("\nspd_read(0x%x) returned %d\n",
 672                       iic0_dimm_addr[dimm_num], num_of_bytes);
 673                 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 674                 debug("spd_read(0x%x) returned %d\n",
 675                       iic0_dimm_addr[dimm_num], total_size);
 676
 677                 if ((num_of_bytes != 0) && (total_size != 0)) {
 678                         dimm_populated[dimm_num] = true;
 679                         dimm_found = true;
 680                         debug("DIMM slot %lu: populated\n", dimm_num);
 681                 } else {
 682                         dimm_populated[dimm_num] = false;
 683                         debug("DIMM slot %lu: Not populated\n", dimm_num);
 684                 }
 685         }
 686
 687         if (dimm_found == false) {
 688                 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
 689                 spd_ddr_init_hang ();
 690         }
 691 }
 692
 693
 694 /*------------------------------------------------------------------
 695  * For the memory DIMMs installed, this routine verifies that they
 696  * really are DDR specific DIMMs.
 697  *-----------------------------------------------------------------*/
 698 static void check_mem_type(unsigned long *dimm_populated,
 699                            unsigned char *iic0_dimm_addr,
 700                            unsigned long num_dimm_banks)
 701 {
 702         unsigned long dimm_num;
 703         unsigned long dimm_type;
 704
 705         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 706                 if (dimm_populated[dimm_num] == true) {
 707                         dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
 708                         switch (dimm_type) {
 709                         case 1:
 710                                 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
 711                                        "slot %d.\n", (unsigned int)dimm_num);
 712                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 713                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 714                                 spd_ddr_init_hang ();
 715                                 break;
 716                         case 2:
 717                                 printf("ERROR: EDO DIMM detected in slot %d.\n",
 718                                        (unsigned int)dimm_num);
 719                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 720                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 721                                 spd_ddr_init_hang ();
 722                                 break;
 723                         case 3:
 724                                 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
 725                                        (unsigned int)dimm_num);
 726                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 727                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 728                                 spd_ddr_init_hang ();
 729                                 break;
 730                         case 4:
 731                                 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
 732                                        (unsigned int)dimm_num);
 733                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 734                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 735                                 spd_ddr_init_hang ();
 736                                 break;
 737                         case 5:
 738                                 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
 739                                        (unsigned int)dimm_num);
 740                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 741                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 742                                 spd_ddr_init_hang ();
 743                                 break;
 744                         case 6:
 745                                 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
 746                                        (unsigned int)dimm_num);
 747                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 748                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 749                                 spd_ddr_init_hang ();
 750                                 break;
 751                         case 7:
 752                                 debug("DIMM slot %lu: DDR1 SDRAM detected\n", dimm_num);
 753                                 dimm_populated[dimm_num] = SDRAM_DDR1;
 754                                 break;
 755                         case 8:
 756                                 debug("DIMM slot %lu: DDR2 SDRAM detected\n", dimm_num);
 757                                 dimm_populated[dimm_num] = SDRAM_DDR2;
 758                                 break;
 759                         default:
 760                                 printf("ERROR: Unknown DIMM detected in slot %d.\n",
 761                                        (unsigned int)dimm_num);
 762                                 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
 763                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 764                                 spd_ddr_init_hang ();
 765                                 break;
 766                         }
 767                 }
 768         }
 769         for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
 770                 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
 771                     && (dimm_populated[dimm_num]   != SDRAM_NONE)
 772                     && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
 773                         printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
 774                         spd_ddr_init_hang ();
 775                 }
 776         }
 777 }
 778
 779 /*------------------------------------------------------------------
 780  * For the memory DIMMs installed, this routine verifies that
 781  * frequency previously calculated is supported.
 782  *-----------------------------------------------------------------*/
 783 static void check_frequency(unsigned long *dimm_populated,
 784                             unsigned char *iic0_dimm_addr,
 785                             unsigned long num_dimm_banks)
 786 {
 787         unsigned long dimm_num;
 788         unsigned long tcyc_reg;
 789         unsigned long cycle_time;
 790         unsigned long calc_cycle_time;
 791         unsigned long sdram_freq;
 792         unsigned long sdr_ddrpll;
 793         PPC4xx_SYS_INFO board_cfg;
 794
 795         /*------------------------------------------------------------------
 796          * Get the board configuration info.
 797          *-----------------------------------------------------------------*/
 798         get_sys_info(&board_cfg);
 799
 800         mfsdr(SDR0_DDR0, sdr_ddrpll);
 801         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
 802
 803         /*
 804          * calc_cycle_time is calculated from DDR frequency set by board/chip
 805          * and is expressed in multiple of 10 picoseconds
 806          * to match the way DIMM cycle time is calculated below.
 807          */
 808         calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
 809
 810         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 811                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 812                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
 813                         /*
 814                          * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
 815                          * the higher order nibble (bits 4-7) designates the cycle time
 816                          * to a granularity of 1ns;
 817                          * the value presented by the lower order nibble (bits 0-3)
 818                          * has a granularity of .1ns and is added to the value designated
 819                          * by the higher nibble. In addition, four lines of the lower order
 820                          * nibble are assigned to support +.25,+.33, +.66 and +.75.
 821                          */
 822                          /* Convert from hex to decimal */
 823                         if ((tcyc_reg & 0x0F) == 0x0D)
 824                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
 825                         else if ((tcyc_reg & 0x0F) == 0x0C)
 826                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
 827                         else if ((tcyc_reg & 0x0F) == 0x0B)
 828                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
 829                         else if ((tcyc_reg & 0x0F) == 0x0A)
 830                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
 831                         else
 832                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
 833                                         ((tcyc_reg & 0x0F)*10);
 834                         debug("cycle_time=%lu [10 picoseconds]\n", cycle_time);
 835
 836                         if  (cycle_time > (calc_cycle_time + 10)) {
 837                                 /*
 838                                  * the provided sdram cycle_time is too small
 839                                  * for the available DIMM cycle_time.
 840                                  * The additionnal 100ps is here to accept a small incertainty.
 841                                  */
 842                                 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
 843                                        "slot %d \n while calculated cycle time is %d ps.\n",
 844                                        (unsigned int)(cycle_time*10),
 845                                        (unsigned int)dimm_num,
 846                                        (unsigned int)(calc_cycle_time*10));
 847                                 printf("Replace the DIMM, or change DDR frequency via "
 848                                        "strapping bits.\n\n");
 849                                 spd_ddr_init_hang ();
 850                         }
 851                 }
 852         }
 853 }
 854
 855 /*------------------------------------------------------------------
 856  * For the memory DIMMs installed, this routine verifies two
 857  * ranks/banks maximum are availables.
 858  *-----------------------------------------------------------------*/
 859 static void check_rank_number(unsigned long *dimm_populated,
 860                               unsigned char *iic0_dimm_addr,
 861                               unsigned long num_dimm_banks)
 862 {
 863         unsigned long dimm_num;
 864         unsigned long dimm_rank;
 865         unsigned long total_rank = 0;
 866
 867         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 868                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 869                         dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
 870                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
 871                                 dimm_rank = (dimm_rank & 0x0F) +1;
 872                         else
 873                                 dimm_rank = dimm_rank & 0x0F;
 874
 875
 876                         if (dimm_rank > MAXRANKS) {
 877                                 printf("ERROR: DRAM DIMM detected with %lu ranks in "
 878                                        "slot %lu is not supported.\n", dimm_rank, dimm_num);
 879                                 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 880                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 881                                 spd_ddr_init_hang ();
 882                         } else
 883                                 total_rank += dimm_rank;
 884                 }
 885                 if (total_rank > MAXRANKS) {
 886                         printf("ERROR: DRAM DIMM detected with a total of %d ranks "
 887                                "for all slots.\n", (unsigned int)total_rank);
 888                         printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 889                         printf("Remove one of the DIMM modules.\n\n");
 890                         spd_ddr_init_hang ();
 891                 }
 892         }
 893 }
 894
 895 /*------------------------------------------------------------------
 896  * only support 2.5V modules.
 897  * This routine verifies this.
 898  *-----------------------------------------------------------------*/
 899 static void check_voltage_type(unsigned long *dimm_populated,
 900                                unsigned char *iic0_dimm_addr,
 901                                unsigned long num_dimm_banks)
 902 {
 903         unsigned long dimm_num;
 904         unsigned long voltage_type;
 905
 906         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 907                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 908                         voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
 909                         switch (voltage_type) {
 910                         case 0x00:
 911                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 912                                 printf("This DIMM is 5.0 Volt/TTL.\n");
 913                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 914                                        (unsigned int)dimm_num);
 915                                 spd_ddr_init_hang ();
 916                                 break;
 917                         case 0x01:
 918                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 919                                 printf("This DIMM is LVTTL.\n");
 920                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 921                                        (unsigned int)dimm_num);
 922                                 spd_ddr_init_hang ();
 923                                 break;
 924                         case 0x02:
 925                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 926                                 printf("This DIMM is 1.5 Volt.\n");
 927                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 928                                        (unsigned int)dimm_num);
 929                                 spd_ddr_init_hang ();
 930                                 break;
 931                         case 0x03:
 932                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 933                                 printf("This DIMM is 3.3 Volt/TTL.\n");
 934                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 935                                        (unsigned int)dimm_num);
 936                                 spd_ddr_init_hang ();
 937                                 break;
 938                         case 0x04:
 939                                 /* 2.5 Voltage only for DDR1 */
 940                                 break;
 941                         case 0x05:
 942                                 /* 1.8 Voltage only for DDR2 */
 943                                 break;
 944                         default:
 945                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 946                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 947                                        (unsigned int)dimm_num);
 948                                 spd_ddr_init_hang ();
 949                                 break;
 950                         }
 951                 }
 952         }
 953 }
 954
 955 /*-----------------------------------------------------------------------------+
 956  * program_copt1.
 957  *-----------------------------------------------------------------------------*/
 958 static void program_copt1(unsigned long *dimm_populated,
 959                           unsigned char *iic0_dimm_addr,
 960                           unsigned long num_dimm_banks)
 961 {
 962         unsigned long dimm_num;
 963         unsigned long mcopt1;
 964         unsigned long ecc_enabled;
 965         unsigned long ecc = 0;
 966         unsigned long data_width = 0;
 967         unsigned long dimm_32bit;
 968         unsigned long dimm_64bit;
 969         unsigned long registered = 0;
 970         unsigned long attribute = 0;
 971         unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
 972         unsigned long bankcount;
 973         unsigned long val;
 974
 975 #ifdef CONFIG_DDR_ECC
 976         ecc_enabled = true;
 977 #else
 978         ecc_enabled = false;
 979 #endif
 980         dimm_32bit = false;
 981         dimm_64bit = false;
 982         buf0 = false;
 983         buf1 = false;
 984
 985         /*------------------------------------------------------------------
 986          * Set memory controller options reg 1, SDRAM_MCOPT1.
 987          *-----------------------------------------------------------------*/
 988         mfsdram(SDRAM_MCOPT1, val);
 989         mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
 990                          SDRAM_MCOPT1_PMU_MASK  | SDRAM_MCOPT1_DMWD_MASK |
 991                          SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
 992                          SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
 993                          SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
 994                          SDRAM_MCOPT1_DREF_MASK);
 995
 996         mcopt1 |= SDRAM_MCOPT1_QDEP;
 997         mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
 998         mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
 999         mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
1000         mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
1001         mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
1002
1003         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1004                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1005                         /* test ecc support */
1006                         ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
1007                         if (ecc != 0x02) /* ecc not supported */
1008                                 ecc_enabled = false;
1009
1010                         /* test bank count */
1011                         bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
1012                         if (bankcount == 0x04) /* bank count = 4 */
1013                                 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
1014                         else /* bank count = 8 */
1015                                 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
1016
1017                         /* test for buffered/unbuffered, registered, differential clocks */
1018                         registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
1019                         attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
1020
1021                         /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
1022                         if (dimm_num == 0) {
1023                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1024                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1025                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1026                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1027                                 if (registered == 1) { /* DDR2 always buffered */
1028                                         /* TODO: what about above  comments ? */
1029                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
1030                                         buf0 = true;
1031                                 } else {
1032                                         /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
1033                                         if ((attribute & 0x02) == 0x00) {
1034                                                 /* buffered not supported */
1035                                                 buf0 = false;
1036                                         } else {
1037                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
1038                                                 buf0 = true;
1039                                         }
1040                                 }
1041                         }
1042                         else if (dimm_num == 1) {
1043                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1044                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1045                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1046                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1047                                 if (registered == 1) {
1048                                         /* DDR2 always buffered */
1049                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
1050                                         buf1 = true;
1051                                 } else {
1052                                         if ((attribute & 0x02) == 0x00) {
1053                                                 /* buffered not supported */
1054                                                 buf1 = false;
1055                                         } else {
1056                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
1057                                                 buf1 = true;
1058                                         }
1059                                 }
1060                         }
1061
1062                         /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
1063                         data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
1064                                 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
1065
1066                         switch (data_width) {
1067                         case 72:
1068                         case 64:
1069                                 dimm_64bit = true;
1070                                 break;
1071                         case 40:
1072                         case 32:
1073                                 dimm_32bit = true;
1074                                 break;
1075                         default:
1076                                 printf("WARNING: Detected a DIMM with a data width of %lu bits.\n",
1077                                        data_width);
1078                                 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
1079                                 break;
1080                         }
1081                 }
1082         }
1083
1084         /* verify matching properties */
1085         if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
1086                 if (buf0 != buf1) {
1087                         printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
1088                         spd_ddr_init_hang ();
1089                 }
1090         }
1091
1092         if ((dimm_64bit == true) && (dimm_32bit == true)) {
1093                 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
1094                 spd_ddr_init_hang ();
1095         } else if ((dimm_64bit == true) && (dimm_32bit == false)) {
1096                 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1097         } else if ((dimm_64bit == false) && (dimm_32bit == true)) {
1098                 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1099         } else {
1100                 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
1101                 spd_ddr_init_hang ();
1102         }
1103
1104         if (ecc_enabled == true)
1105                 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1106         else
1107                 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1108
1109         mtsdram(SDRAM_MCOPT1, mcopt1);
1110 }
1111
1112 /*-----------------------------------------------------------------------------+
1113  * program_codt.
1114  *-----------------------------------------------------------------------------*/
1115 static void program_codt(unsigned long *dimm_populated,
1116                          unsigned char *iic0_dimm_addr,
1117                          unsigned long num_dimm_banks)
1118 {
1119         unsigned long codt;
1120         unsigned long modt0 = 0;
1121         unsigned long modt1 = 0;
1122         unsigned long modt2 = 0;
1123         unsigned long modt3 = 0;
1124         unsigned char dimm_num;
1125         unsigned char dimm_rank;
1126         unsigned char total_rank = 0;
1127         unsigned char total_dimm = 0;
1128         unsigned char dimm_type = 0;
1129         unsigned char firstSlot = 0;
1130
1131         /*------------------------------------------------------------------
1132          * Set the SDRAM Controller On Die Termination Register
1133          *-----------------------------------------------------------------*/
1134         mfsdram(SDRAM_CODT, codt);
1135         codt &= ~(SDRAM_CODT_DQS_SINGLE_END | SDRAM_CODT_CKSE_SINGLE_END);
1136         codt |= SDRAM_CODT_IO_NMODE;
1137
1138         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1139                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1140                         dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1141                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1142                                 dimm_rank = (dimm_rank & 0x0F) + 1;
1143                                 dimm_type = SDRAM_DDR2;
1144                         } else {
1145                                 dimm_rank = dimm_rank & 0x0F;
1146                                 dimm_type = SDRAM_DDR1;
1147                         }
1148
1149                         total_rank += dimm_rank;
1150                         total_dimm++;
1151                         if ((dimm_num == 0) && (total_dimm == 1))
1152                                 firstSlot = true;
1153                         else
1154                                 firstSlot = false;
1155                 }
1156         }
1157         if (dimm_type == SDRAM_DDR2) {
1158                 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1159                 if ((total_dimm == 1) && (firstSlot == true)) {
1160                         if (total_rank == 1) {  /* PUUU */
1161                                 codt |= CALC_ODT_R(0);
1162                                 modt0 = CALC_ODT_W(0);
1163                                 modt1 = 0x00000000;
1164                                 modt2 = 0x00000000;
1165                                 modt3 = 0x00000000;
1166                         }
1167                         if (total_rank == 2) {  /* PPUU */
1168                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
1169                                 modt0 = CALC_ODT_W(0) | CALC_ODT_W(1);
1170                                 modt1 = 0x00000000;
1171                                 modt2 = 0x00000000;
1172                                 modt3 = 0x00000000;
1173                         }
1174                 } else if ((total_dimm == 1) && (firstSlot != true)) {
1175                         if (total_rank == 1) {  /* UUPU */
1176                                 codt |= CALC_ODT_R(2);
1177                                 modt0 = 0x00000000;
1178                                 modt1 = 0x00000000;
1179                                 modt2 = CALC_ODT_W(2);
1180                                 modt3 = 0x00000000;
1181                         }
1182                         if (total_rank == 2) {  /* UUPP */
1183                                 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1184                                 modt0 = 0x00000000;
1185                                 modt1 = 0x00000000;
1186                                 modt2 = CALC_ODT_W(2) | CALC_ODT_W(3);
1187                                 modt3 = 0x00000000;
1188                         }
1189                 }
1190                 if (total_dimm == 2) {
1191                         if (total_rank == 2) {  /* PUPU */
1192                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1193                                 modt0 = CALC_ODT_RW(2);
1194                                 modt1 = 0x00000000;
1195                                 modt2 = CALC_ODT_RW(0);
1196                                 modt3 = 0x00000000;
1197                         }
1198                         if (total_rank == 4) {  /* PPPP */
1199                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
1200                                         CALC_ODT_R(2) | CALC_ODT_R(3);
1201                                 modt0 = CALC_ODT_RW(2) | CALC_ODT_RW(3);
1202                                 modt1 = 0x00000000;
1203                                 modt2 = CALC_ODT_RW(0) | CALC_ODT_RW(1);
1204                                 modt3 = 0x00000000;
1205                         }
1206                 }
1207         } else {
1208                 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1209                 modt0 = 0x00000000;
1210                 modt1 = 0x00000000;
1211                 modt2 = 0x00000000;
1212                 modt3 = 0x00000000;
1213
1214                 if (total_dimm == 1) {
1215                         if (total_rank == 1)
1216                                 codt |= 0x00800000;
1217                         if (total_rank == 2)
1218                                 codt |= 0x02800000;
1219                 }
1220                 if (total_dimm == 2) {
1221                         if (total_rank == 2)
1222                                 codt |= 0x08800000;
1223                         if (total_rank == 4)
1224                                 codt |= 0x2a800000;
1225                 }
1226         }
1227
1228         debug("nb of dimm %d\n", total_dimm);
1229         debug("nb of rank %d\n", total_rank);
1230         if (total_dimm == 1)
1231                 debug("dimm in slot %d\n", firstSlot);
1232
1233         mtsdram(SDRAM_CODT, codt);
1234         mtsdram(SDRAM_MODT0, modt0);
1235         mtsdram(SDRAM_MODT1, modt1);
1236         mtsdram(SDRAM_MODT2, modt2);
1237         mtsdram(SDRAM_MODT3, modt3);
1238 }
1239
1240 /*-----------------------------------------------------------------------------+
1241  * program_initplr.
1242  *-----------------------------------------------------------------------------*/
1243 static void program_initplr(unsigned long *dimm_populated,
1244                             unsigned char *iic0_dimm_addr,
1245                             unsigned long num_dimm_banks,
1246                             ddr_cas_id_t selected_cas,
1247                             int write_recovery)
1248 {
1249         u32 cas = 0;
1250         u32 odt = 0;
1251         u32 ods = 0;
1252         u32 mr;
1253         u32 wr;
1254         u32 emr;
1255         u32 emr2;
1256         u32 emr3;
1257         int dimm_num;
1258         int total_dimm = 0;
1259
1260         /******************************************************
1261          ** Assumption: if more than one DIMM, all DIMMs are the same
1262          **             as already checked in check_memory_type
1263          ******************************************************/
1264
1265         if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1266                 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1267                 mtsdram(SDRAM_INITPLR1, 0x81900400);
1268                 mtsdram(SDRAM_INITPLR2, 0x81810000);
1269                 mtsdram(SDRAM_INITPLR3, 0xff800162);
1270                 mtsdram(SDRAM_INITPLR4, 0x81900400);
1271                 mtsdram(SDRAM_INITPLR5, 0x86080000);
1272                 mtsdram(SDRAM_INITPLR6, 0x86080000);
1273                 mtsdram(SDRAM_INITPLR7, 0x81000062);
1274         } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1275                 switch (selected_cas) {
1276                 case DDR_CAS_3:
1277                         cas = 3 << 4;
1278                         break;
1279                 case DDR_CAS_4:
1280                         cas = 4 << 4;
1281                         break;
1282                 case DDR_CAS_5:
1283                         cas = 5 << 4;
1284                         break;
1285                 default:
1286                         printf("ERROR: ucode error on selected_cas value %d", selected_cas);
1287                         spd_ddr_init_hang ();
1288                         break;
1289                 }
1290
1291 #if 0
1292                 /*
1293                  * ToDo - Still a problem with the write recovery:
1294                  * On the Corsair CM2X512-5400C4 module, setting write recovery
1295                  * in the INITPLR reg to the value calculated in program_mode()
1296                  * results in not correctly working DDR2 memory (crash after
1297                  * relocation).
1298                  *
1299                  * So for now, set the write recovery to 3. This seems to work
1300                  * on the Corair module too.
1301                  *
1302                  * 2007-03-01, sr
1303                  */
1304                 switch (write_recovery) {
1305                 case 3:
1306                         wr = WRITE_RECOV_3;
1307                         break;
1308                 case 4:
1309                         wr = WRITE_RECOV_4;
1310                         break;
1311                 case 5:
1312                         wr = WRITE_RECOV_5;
1313                         break;
1314                 case 6:
1315                         wr = WRITE_RECOV_6;
1316                         break;
1317                 default:
1318                         printf("ERROR: write recovery not support (%d)", write_recovery);
1319                         spd_ddr_init_hang ();
1320                         break;
1321                 }
1322 #else
1323                 wr = WRITE_RECOV_3; /* test-only, see description above */
1324 #endif
1325
1326                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1327                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1328                                 total_dimm++;
1329                 if (total_dimm == 1) {
1330                         odt = ODT_150_OHM;
1331                         ods = ODS_FULL;
1332                 } else if (total_dimm == 2) {
1333                         odt = ODT_75_OHM;
1334                         ods = ODS_REDUCED;
1335                 } else {
1336                         printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
1337                         spd_ddr_init_hang ();
1338                 }
1339
1340                 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1341                 emr = CMD_EMR | SELECT_EMR | odt | ods;
1342                 emr2 = CMD_EMR | SELECT_EMR2;
1343                 emr3 = CMD_EMR | SELECT_EMR3;
1344                 /* NOP - Wait 106 MemClk cycles */
1345                 mtsdram(SDRAM_INITPLR0, SDRAM_INITPLR_ENABLE | CMD_NOP |
1346                                         SDRAM_INITPLR_IMWT_ENCODE(106));
1347                 udelay(1000);
1348                 /* precharge 4 MemClk cycles */
1349                 mtsdram(SDRAM_INITPLR1, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1350                                         SDRAM_INITPLR_IMWT_ENCODE(4));
1351                 /* EMR2 - Wait tMRD (2 MemClk cycles) */
1352                 mtsdram(SDRAM_INITPLR2, SDRAM_INITPLR_ENABLE | emr2 |
1353                                         SDRAM_INITPLR_IMWT_ENCODE(2));
1354                 /* EMR3 - Wait tMRD (2 MemClk cycles) */
1355                 mtsdram(SDRAM_INITPLR3, SDRAM_INITPLR_ENABLE | emr3 |
1356                                         SDRAM_INITPLR_IMWT_ENCODE(2));
1357                 /* EMR DLL ENABLE - Wait tMRD (2 MemClk cycles) */
1358                 mtsdram(SDRAM_INITPLR4, SDRAM_INITPLR_ENABLE | emr |
1359                                         SDRAM_INITPLR_IMWT_ENCODE(2));
1360                 /* MR w/ DLL reset - 200 cycle wait for DLL reset */
1361                 mtsdram(SDRAM_INITPLR5, SDRAM_INITPLR_ENABLE | mr | DLL_RESET |
1362                                         SDRAM_INITPLR_IMWT_ENCODE(200));
1363                 udelay(1000);
1364                 /* precharge 4 MemClk cycles */
1365                 mtsdram(SDRAM_INITPLR6, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1366                                         SDRAM_INITPLR_IMWT_ENCODE(4));
1367                 /* Refresh 25 MemClk cycles */
1368                 mtsdram(SDRAM_INITPLR7, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1369                                         SDRAM_INITPLR_IMWT_ENCODE(25));
1370                 /* Refresh 25 MemClk cycles */
1371                 mtsdram(SDRAM_INITPLR8, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1372                                         SDRAM_INITPLR_IMWT_ENCODE(25));
1373                 /* Refresh 25 MemClk cycles */
1374                 mtsdram(SDRAM_INITPLR9, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1375                                         SDRAM_INITPLR_IMWT_ENCODE(25));
1376                 /* Refresh 25 MemClk cycles */
1377                 mtsdram(SDRAM_INITPLR10, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1378                                          SDRAM_INITPLR_IMWT_ENCODE(25));
1379                 /* MR w/o DLL reset - Wait tMRD (2 MemClk cycles) */
1380                 mtsdram(SDRAM_INITPLR11, SDRAM_INITPLR_ENABLE | mr |
1381                                          SDRAM_INITPLR_IMWT_ENCODE(2));
1382                 /* EMR OCD Default - Wait tMRD (2 MemClk cycles) */
1383                 mtsdram(SDRAM_INITPLR12, SDRAM_INITPLR_ENABLE | OCD_CALIB_DEF |
1384                                          SDRAM_INITPLR_IMWT_ENCODE(2) | emr);
1385                 /* EMR OCD Exit */
1386                 mtsdram(SDRAM_INITPLR13, SDRAM_INITPLR_ENABLE | emr |
1387                                          SDRAM_INITPLR_IMWT_ENCODE(2));
1388         } else {
1389                 printf("ERROR: ucode error as unknown DDR type in program_initplr");
1390                 spd_ddr_init_hang ();
1391         }
1392 }
1393
1394 /*------------------------------------------------------------------
1395  * This routine programs the SDRAM_MMODE register.
1396  * the selected_cas is an output parameter, that will be passed
1397  * by caller to call the above program_initplr( )
1398  *-----------------------------------------------------------------*/
1399 static void program_mode(unsigned long *dimm_populated,
1400                          unsigned char *iic0_dimm_addr,
1401                          unsigned long num_dimm_banks,
1402                          ddr_cas_id_t *selected_cas,
1403                          int *write_recovery)
1404 {
1405         unsigned long dimm_num;
1406         unsigned long sdram_ddr1;
1407         unsigned long t_wr_ns;
1408         unsigned long t_wr_clk;
1409         unsigned long cas_bit;
1410         unsigned long cas_index;
1411         unsigned long sdram_freq;
1412         unsigned long ddr_check;
1413         unsigned long mmode;
1414         unsigned long tcyc_reg;
1415         unsigned long cycle_2_0_clk;
1416         unsigned long cycle_2_5_clk;
1417         unsigned long cycle_3_0_clk;
1418         unsigned long cycle_4_0_clk;
1419         unsigned long cycle_5_0_clk;
1420         unsigned long max_2_0_tcyc_ns_x_100;
1421         unsigned long max_2_5_tcyc_ns_x_100;
1422         unsigned long max_3_0_tcyc_ns_x_100;
1423         unsigned long max_4_0_tcyc_ns_x_100;
1424         unsigned long max_5_0_tcyc_ns_x_100;
1425         unsigned long cycle_time_ns_x_100[3];
1426         PPC4xx_SYS_INFO board_cfg;
1427         unsigned char cas_2_0_available;
1428         unsigned char cas_2_5_available;
1429         unsigned char cas_3_0_available;
1430         unsigned char cas_4_0_available;
1431         unsigned char cas_5_0_available;
1432         unsigned long sdr_ddrpll;
1433
1434         /*------------------------------------------------------------------
1435          * Get the board configuration info.
1436          *-----------------------------------------------------------------*/
1437         get_sys_info(&board_cfg);
1438
1439         mfsdr(SDR0_DDR0, sdr_ddrpll);
1440         sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
1441         debug("sdram_freq=%lu\n", sdram_freq);
1442
1443         /*------------------------------------------------------------------
1444          * Handle the timing.  We need to find the worst case timing of all
1445          * the dimm modules installed.
1446          *-----------------------------------------------------------------*/
1447         t_wr_ns = 0;
1448         cas_2_0_available = true;
1449         cas_2_5_available = true;
1450         cas_3_0_available = true;
1451         cas_4_0_available = true;
1452         cas_5_0_available = true;
1453         max_2_0_tcyc_ns_x_100 = 10;
1454         max_2_5_tcyc_ns_x_100 = 10;
1455         max_3_0_tcyc_ns_x_100 = 10;
1456         max_4_0_tcyc_ns_x_100 = 10;
1457         max_5_0_tcyc_ns_x_100 = 10;
1458         sdram_ddr1 = true;
1459
1460         /* loop through all the DIMM slots on the board */
1461         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1462                 /* If a dimm is installed in a particular slot ... */
1463                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1464                         if (dimm_populated[dimm_num] == SDRAM_DDR1)
1465                                 sdram_ddr1 = true;
1466                         else
1467                                 sdram_ddr1 = false;
1468
1469                         cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1470                         debug("cas_bit[SPD byte 18]=%02lx\n", cas_bit);
1471
1472                         /* For a particular DIMM, grab the three CAS values it supports */
1473                         for (cas_index = 0; cas_index < 3; cas_index++) {
1474                                 switch (cas_index) {
1475                                 case 0:
1476                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1477                                         break;
1478                                 case 1:
1479                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1480                                         break;
1481                                 default:
1482                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1483                                         break;
1484                                 }
1485
1486                                 if ((tcyc_reg & 0x0F) >= 10) {
1487                                         if ((tcyc_reg & 0x0F) == 0x0D) {
1488                                                 /* Convert from hex to decimal */
1489                                                 cycle_time_ns_x_100[cas_index] =
1490                                                         (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
1491                                         } else {
1492                                                 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1493                                                        "in slot %d\n", (unsigned int)dimm_num);
1494                                                 spd_ddr_init_hang ();
1495                                         }
1496                                 } else {
1497                                         /* Convert from hex to decimal */
1498                                         cycle_time_ns_x_100[cas_index] =
1499                                                 (((tcyc_reg & 0xF0) >> 4) * 100) +
1500                                                 ((tcyc_reg & 0x0F)*10);
1501                                 }
1502                                 debug("cas_index=%lu: cycle_time_ns_x_100=%lu\n", cas_index,
1503                                       cycle_time_ns_x_100[cas_index]);
1504                         }
1505
1506                         /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1507                         /* supported for a particular DIMM. */
1508                         cas_index = 0;
1509
1510                         if (sdram_ddr1) {
1511                                 /*
1512                                  * DDR devices use the following bitmask for CAS latency:
1513                                  *  Bit   7    6    5    4    3    2    1    0
1514                                  *       TBD  4.0  3.5  3.0  2.5  2.0  1.5  1.0
1515                                  */
1516                                 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
1517                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1518                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1519                                                                     cycle_time_ns_x_100[cas_index]);
1520                                         cas_index++;
1521                                 } else {
1522                                         if (cas_index != 0)
1523                                                 cas_index++;
1524                                         cas_4_0_available = false;
1525                                 }
1526
1527                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1528                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1529                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1530                                                                     cycle_time_ns_x_100[cas_index]);
1531                                         cas_index++;
1532                                 } else {
1533                                         if (cas_index != 0)
1534                                                 cas_index++;
1535                                         cas_3_0_available = false;
1536                                 }
1537
1538                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1539                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1540                                         max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
1541                                                                     cycle_time_ns_x_100[cas_index]);
1542                                         cas_index++;
1543                                 } else {
1544                                         if (cas_index != 0)
1545                                                 cas_index++;
1546                                         cas_2_5_available = false;
1547                                 }
1548
1549                                 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
1550                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1551                                         max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
1552                                                                     cycle_time_ns_x_100[cas_index]);
1553                                         cas_index++;
1554                                 } else {
1555                                         if (cas_index != 0)
1556                                                 cas_index++;
1557                                         cas_2_0_available = false;
1558                                 }
1559                         } else {
1560                                 /*
1561                                  * DDR2 devices use the following bitmask for CAS latency:
1562                                  *  Bit   7    6    5    4    3    2    1    0
1563                                  *       TBD  6.0  5.0  4.0  3.0  2.0  TBD  TBD
1564                                  */
1565                                 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
1566                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1567                                         max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
1568                                                                     cycle_time_ns_x_100[cas_index]);
1569                                         cas_index++;
1570                                 } else {
1571                                         if (cas_index != 0)
1572                                                 cas_index++;
1573                                         cas_5_0_available = false;
1574                                 }
1575
1576                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1577                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1578                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1579                                                                     cycle_time_ns_x_100[cas_index]);
1580                                         cas_index++;
1581                                 } else {
1582                                         if (cas_index != 0)
1583                                                 cas_index++;
1584                                         cas_4_0_available = false;
1585                                 }
1586
1587                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1588                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1589                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1590                                                                     cycle_time_ns_x_100[cas_index]);
1591                                         cas_index++;
1592                                 } else {
1593                                         if (cas_index != 0)
1594                                                 cas_index++;
1595                                         cas_3_0_available = false;
1596                                 }
1597                         }
1598                 }
1599         }
1600
1601         /*------------------------------------------------------------------
1602          * Set the SDRAM mode, SDRAM_MMODE
1603          *-----------------------------------------------------------------*/
1604         mfsdram(SDRAM_MMODE, mmode);
1605         mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1606
1607         /* add 10 here because of rounding problems */
1608         cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1609         cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1610         cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1611         cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1612         cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
1613         debug("cycle_3_0_clk=%lu\n", cycle_3_0_clk);
1614         debug("cycle_4_0_clk=%lu\n", cycle_4_0_clk);
1615         debug("cycle_5_0_clk=%lu\n", cycle_5_0_clk);
1616
1617         if (sdram_ddr1 == true) { /* DDR1 */
1618                 if ((cas_2_0_available == true) &&
1619                         (sdram_freq <= cycle_2_0_clk)) {
1620                         mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1621                         *selected_cas = DDR_CAS_2;
1622                 } else if ((cas_2_5_available == true) &&
1623                         (sdram_freq <= cycle_2_5_clk)) {
1624                         mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1625                         *selected_cas = DDR_CAS_2_5;
1626                 } else if ((cas_3_0_available == true) &&
1627                         (sdram_freq <= cycle_3_0_clk)) {
1628                         mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1629                         *selected_cas = DDR_CAS_3;
1630                 } else {
1631                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1632                         printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1633                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1634                         spd_ddr_init_hang ();
1635                 }
1636         } else { /* DDR2 */
1637                 debug("cas_3_0_available=%d\n", cas_3_0_available);
1638                 debug("cas_4_0_available=%d\n", cas_4_0_available);
1639                 debug("cas_5_0_available=%d\n", cas_5_0_available);
1640                 if ((cas_3_0_available == true) &&
1641                         (sdram_freq <= cycle_3_0_clk)) {
1642                         mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1643                         *selected_cas = DDR_CAS_3;
1644                 } else if ((cas_4_0_available == true) &&
1645                         (sdram_freq <= cycle_4_0_clk)) {
1646                         mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1647                         *selected_cas = DDR_CAS_4;
1648                 } else if ((cas_5_0_available == true) &&
1649                         (sdram_freq <= cycle_5_0_clk)) {
1650                         mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1651                         *selected_cas = DDR_CAS_5;
1652                 } else {
1653                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1654                         printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
1655                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1656                         printf("cas3=%d cas4=%d cas5=%d\n",
1657                                cas_3_0_available, cas_4_0_available, cas_5_0_available);
1658                         printf("sdram_freq=%lu cycle3=%lu cycle4=%lu cycle5=%lu\n\n",
1659                                sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
1660                         spd_ddr_init_hang ();
1661                 }
1662         }
1663
1664         if (sdram_ddr1 == true)
1665                 mmode |= SDRAM_MMODE_WR_DDR1;
1666         else {
1667
1668                 /* loop through all the DIMM slots on the board */
1669                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1670                         /* If a dimm is installed in a particular slot ... */
1671                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1672                                 t_wr_ns = max(t_wr_ns, (unsigned long)
1673                                               spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1674                 }
1675
1676                 /*
1677                  * convert from nanoseconds to ddr clocks
1678                  * round up if necessary
1679                  */
1680                 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1681                 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1682                 if (sdram_freq != ddr_check)
1683                         t_wr_clk++;
1684
1685                 switch (t_wr_clk) {
1686                 case 0:
1687                 case 1:
1688                 case 2:
1689                 case 3:
1690                         mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1691                         break;
1692                 case 4:
1693                         mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1694                         break;
1695                 case 5:
1696                         mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1697                         break;
1698                 default:
1699                         mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1700                         break;
1701                 }
1702                 *write_recovery = t_wr_clk;
1703         }
1704
1705         debug("CAS latency = %d\n", *selected_cas);
1706         debug("Write recovery = %d\n", *write_recovery);
1707
1708         mtsdram(SDRAM_MMODE, mmode);
1709 }
1710
1711 /*-----------------------------------------------------------------------------+
1712  * program_rtr.
1713  *-----------------------------------------------------------------------------*/
1714 static void program_rtr(unsigned long *dimm_populated,
1715                         unsigned char *iic0_dimm_addr,
1716                         unsigned long num_dimm_banks)
1717 {
1718         PPC4xx_SYS_INFO board_cfg;
1719         unsigned long max_refresh_rate;
1720         unsigned long dimm_num;
1721         unsigned long refresh_rate_type;
1722         unsigned long refresh_rate;
1723         unsigned long rint;
1724         unsigned long sdram_freq;
1725         unsigned long sdr_ddrpll;
1726         unsigned long val;
1727
1728         /*------------------------------------------------------------------
1729          * Get the board configuration info.
1730          *-----------------------------------------------------------------*/
1731         get_sys_info(&board_cfg);
1732
1733         /*------------------------------------------------------------------
1734          * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1735          *-----------------------------------------------------------------*/
1736         mfsdr(SDR0_DDR0, sdr_ddrpll);
1737         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1738
1739         max_refresh_rate = 0;
1740         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1741                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1742
1743                         refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1744                         refresh_rate_type &= 0x7F;
1745                         switch (refresh_rate_type) {
1746                         case 0:
1747                                 refresh_rate =  15625;
1748                                 break;
1749                         case 1:
1750                                 refresh_rate =   3906;
1751                                 break;
1752                         case 2:
1753                                 refresh_rate =   7812;
1754                                 break;
1755                         case 3:
1756                                 refresh_rate =  31250;
1757                                 break;
1758                         case 4:
1759                                 refresh_rate =  62500;
1760                                 break;
1761                         case 5:
1762                                 refresh_rate = 125000;
1763                                 break;
1764                         default:
1765                                 refresh_rate = 0;
1766                                 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1767                                        (unsigned int)dimm_num);
1768                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1769                                 spd_ddr_init_hang ();
1770                                 break;
1771                         }
1772
1773                         max_refresh_rate = max(max_refresh_rate, refresh_rate);
1774                 }
1775         }
1776
1777         rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1778         mfsdram(SDRAM_RTR, val);
1779         mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1780                 (SDRAM_RTR_RINT_ENCODE(rint)));
1781 }
1782
1783 /*------------------------------------------------------------------
1784  * This routine programs the SDRAM_TRx registers.
1785  *-----------------------------------------------------------------*/
1786 static void program_tr(unsigned long *dimm_populated,
1787                        unsigned char *iic0_dimm_addr,
1788                        unsigned long num_dimm_banks)
1789 {
1790         unsigned long dimm_num;
1791         unsigned long sdram_ddr1;
1792         unsigned long t_rp_ns;
1793         unsigned long t_rcd_ns;
1794         unsigned long t_rrd_ns;
1795         unsigned long t_ras_ns;
1796         unsigned long t_rc_ns;
1797         unsigned long t_rfc_ns;
1798         unsigned long t_wpc_ns;
1799         unsigned long t_wtr_ns;
1800         unsigned long t_rpc_ns;
1801         unsigned long t_rp_clk;
1802         unsigned long t_rcd_clk;
1803         unsigned long t_rrd_clk;
1804         unsigned long t_ras_clk;
1805         unsigned long t_rc_clk;
1806         unsigned long t_rfc_clk;
1807         unsigned long t_wpc_clk;
1808         unsigned long t_wtr_clk;
1809         unsigned long t_rpc_clk;
1810         unsigned long sdtr1, sdtr2, sdtr3;
1811         unsigned long ddr_check;
1812         unsigned long sdram_freq;
1813         unsigned long sdr_ddrpll;
1814
1815         PPC4xx_SYS_INFO board_cfg;
1816
1817         /*------------------------------------------------------------------
1818          * Get the board configuration info.
1819          *-----------------------------------------------------------------*/
1820         get_sys_info(&board_cfg);
1821
1822         mfsdr(SDR0_DDR0, sdr_ddrpll);
1823         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1824
1825         /*------------------------------------------------------------------
1826          * Handle the timing.  We need to find the worst case timing of all
1827          * the dimm modules installed.
1828          *-----------------------------------------------------------------*/
1829         t_rp_ns = 0;
1830         t_rrd_ns = 0;
1831         t_rcd_ns = 0;
1832         t_ras_ns = 0;
1833         t_rc_ns = 0;
1834         t_rfc_ns = 0;
1835         t_wpc_ns = 0;
1836         t_wtr_ns = 0;
1837         t_rpc_ns = 0;
1838         sdram_ddr1 = true;
1839
1840         /* loop through all the DIMM slots on the board */
1841         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1842                 /* If a dimm is installed in a particular slot ... */
1843                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1844                         if (dimm_populated[dimm_num] == SDRAM_DDR2)
1845                                 sdram_ddr1 = true;
1846                         else
1847                                 sdram_ddr1 = false;
1848
1849                         t_rcd_ns = max(t_rcd_ns,
1850                                        (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1851                         t_rrd_ns = max(t_rrd_ns,
1852                                        (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1853                         t_rp_ns  = max(t_rp_ns,
1854                                        (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1855                         t_ras_ns = max(t_ras_ns,
1856                                        (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 30));
1857                         t_rc_ns  = max(t_rc_ns,
1858                                        (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 41));
1859                         t_rfc_ns = max(t_rfc_ns,
1860                                        (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 42));
1861                 }
1862         }
1863
1864         /*------------------------------------------------------------------
1865          * Set the SDRAM Timing Reg 1, SDRAM_TR1
1866          *-----------------------------------------------------------------*/
1867         mfsdram(SDRAM_SDTR1, sdtr1);
1868         sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1869                    SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1870
1871         /* default values */
1872         sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1873         sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1874
1875         /* normal operations */
1876         sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1877         sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1878
1879         mtsdram(SDRAM_SDTR1, sdtr1);
1880
1881         /*------------------------------------------------------------------
1882          * Set the SDRAM Timing Reg 2, SDRAM_TR2
1883          *-----------------------------------------------------------------*/
1884         mfsdram(SDRAM_SDTR2, sdtr2);
1885         sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK  | SDRAM_SDTR2_WTR_MASK |
1886                    SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1887                    SDRAM_SDTR2_RPC_MASK  | SDRAM_SDTR2_RP_MASK  |
1888                    SDRAM_SDTR2_RRD_MASK);
1889
1890         /*
1891          * convert t_rcd from nanoseconds to ddr clocks
1892          * round up if necessary
1893          */
1894         t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1895         ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1896         if (sdram_freq != ddr_check)
1897                 t_rcd_clk++;
1898
1899         switch (t_rcd_clk) {
1900         case 0:
1901         case 1:
1902                 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1903                 break;
1904         case 2:
1905                 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1906                 break;
1907         case 3:
1908                 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1909                 break;
1910         case 4:
1911                 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1912                 break;
1913         default:
1914                 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1915                 break;
1916         }
1917
1918         if (sdram_ddr1 == true) { /* DDR1 */
1919                 if (sdram_freq < 200000000) {
1920                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1921                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1922                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1923                 } else {
1924                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1925                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1926                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1927                 }
1928         } else { /* DDR2 */
1929                 /* loop through all the DIMM slots on the board */
1930                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1931                         /* If a dimm is installed in a particular slot ... */
1932                         if (dimm_populated[dimm_num] != SDRAM_NONE) {
1933                                 t_wpc_ns = max(t_wtr_ns,
1934                                                (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1935                                 t_wtr_ns = max(t_wtr_ns,
1936                                                (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1937                                 t_rpc_ns = max(t_rpc_ns,
1938                                                (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1939                         }
1940                 }
1941
1942                 /*
1943                  * convert from nanoseconds to ddr clocks
1944                  * round up if necessary
1945                  */
1946                 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1947                 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1948                 if (sdram_freq != ddr_check)
1949                         t_wpc_clk++;
1950
1951                 switch (t_wpc_clk) {
1952                 case 0:
1953                 case 1:
1954                 case 2:
1955                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1956                         break;
1957                 case 3:
1958                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1959                         break;
1960                 case 4:
1961                         sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1962                         break;
1963                 case 5:
1964                         sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1965                         break;
1966                 default:
1967                         sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1968                         break;
1969                 }
1970
1971                 /*
1972                  * convert from nanoseconds to ddr clocks
1973                  * round up if necessary
1974                  */
1975                 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1976                 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1977                 if (sdram_freq != ddr_check)
1978                         t_wtr_clk++;
1979
1980                 switch (t_wtr_clk) {
1981                 case 0:
1982                 case 1:
1983                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1984                         break;
1985                 case 2:
1986                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1987                         break;
1988                 case 3:
1989                         sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
1990                         break;
1991                 default:
1992                         sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
1993                         break;
1994                 }
1995
1996                 /*
1997                  * convert from nanoseconds to ddr clocks
1998                  * round up if necessary
1999                  */
2000                 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
2001                 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
2002                 if (sdram_freq != ddr_check)
2003                         t_rpc_clk++;
2004
2005                 switch (t_rpc_clk) {
2006                 case 0:
2007                 case 1:
2008                 case 2:
2009                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
2010                         break;
2011                 case 3:
2012                         sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
2013                         break;
2014                 default:
2015                         sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
2016                         break;
2017                 }
2018         }
2019
2020         /* default value */
2021         sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
2022
2023         /*
2024          * convert t_rrd from nanoseconds to ddr clocks
2025          * round up if necessary
2026          */
2027         t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
2028         ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
2029         if (sdram_freq != ddr_check)
2030                 t_rrd_clk++;
2031
2032         if (t_rrd_clk == 3)
2033                 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
2034         else
2035                 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
2036
2037         /*
2038          * convert t_rp from nanoseconds to ddr clocks
2039          * round up if necessary
2040          */
2041         t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
2042         ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
2043         if (sdram_freq != ddr_check)
2044                 t_rp_clk++;
2045
2046         switch (t_rp_clk) {
2047         case 0:
2048         case 1:
2049         case 2:
2050         case 3:
2051                 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
2052                 break;
2053         case 4:
2054                 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
2055                 break;
2056         case 5:
2057                 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
2058                 break;
2059         case 6:
2060                 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
2061                 break;
2062         default:
2063                 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
2064                 break;
2065         }
2066
2067         mtsdram(SDRAM_SDTR2, sdtr2);
2068
2069         /*------------------------------------------------------------------
2070          * Set the SDRAM Timing Reg 3, SDRAM_TR3
2071          *-----------------------------------------------------------------*/
2072         mfsdram(SDRAM_SDTR3, sdtr3);
2073         sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK  | SDRAM_SDTR3_RC_MASK |
2074                    SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
2075
2076         /*
2077          * convert t_ras from nanoseconds to ddr clocks
2078          * round up if necessary
2079          */
2080         t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
2081         ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
2082         if (sdram_freq != ddr_check)
2083                 t_ras_clk++;
2084
2085         sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
2086
2087         /*
2088          * convert t_rc from nanoseconds to ddr clocks
2089          * round up if necessary
2090          */
2091         t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
2092         ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
2093         if (sdram_freq != ddr_check)
2094                 t_rc_clk++;
2095
2096         sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
2097
2098         /* default xcs value */
2099         sdtr3 |= SDRAM_SDTR3_XCS;
2100
2101         /*
2102          * convert t_rfc from nanoseconds to ddr clocks
2103          * round up if necessary
2104          */
2105         t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
2106         ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
2107         if (sdram_freq != ddr_check)
2108                 t_rfc_clk++;
2109
2110         sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
2111
2112         mtsdram(SDRAM_SDTR3, sdtr3);
2113 }
2114
2115 /*-----------------------------------------------------------------------------+
2116  * program_bxcf.
2117  *-----------------------------------------------------------------------------*/
2118 static void program_bxcf(unsigned long *dimm_populated,
2119                          unsigned char *iic0_dimm_addr,
2120                          unsigned long num_dimm_banks)
2121 {
2122         unsigned long dimm_num;
2123         unsigned long num_col_addr;
2124         unsigned long num_ranks;
2125         unsigned long num_banks;
2126         unsigned long mode;
2127         unsigned long ind_rank;
2128         unsigned long ind;
2129         unsigned long ind_bank;
2130         unsigned long bank_0_populated;
2131
2132         /*------------------------------------------------------------------
2133          * Set the BxCF regs.  First, wipe out the bank config registers.
2134          *-----------------------------------------------------------------*/
2135         mtsdram(SDRAM_MB0CF, 0x00000000);
2136         mtsdram(SDRAM_MB1CF, 0x00000000);
2137         mtsdram(SDRAM_MB2CF, 0x00000000);
2138         mtsdram(SDRAM_MB3CF, 0x00000000);
2139
2140         mode = SDRAM_BXCF_M_BE_ENABLE;
2141
2142         bank_0_populated = 0;
2143
2144         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2145                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2146                         num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
2147                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2148                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2149                                 num_ranks = (num_ranks & 0x0F) +1;
2150                         else
2151                                 num_ranks = num_ranks & 0x0F;
2152
2153                         num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
2154
2155                         for (ind_bank = 0; ind_bank < 2; ind_bank++) {
2156                                 if (num_banks == 4)
2157                                         ind = 0;
2158                                 else
2159                                         ind = 5 << 8;
2160                                 switch (num_col_addr) {
2161                                 case 0x08:
2162                                         mode |= (SDRAM_BXCF_M_AM_0 + ind);
2163                                         break;
2164                                 case 0x09:
2165                                         mode |= (SDRAM_BXCF_M_AM_1 + ind);
2166                                         break;
2167                                 case 0x0A:
2168                                         mode |= (SDRAM_BXCF_M_AM_2 + ind);
2169                                         break;
2170                                 case 0x0B:
2171                                         mode |= (SDRAM_BXCF_M_AM_3 + ind);
2172                                         break;
2173                                 case 0x0C:
2174                                         mode |= (SDRAM_BXCF_M_AM_4 + ind);
2175                                         break;
2176                                 default:
2177                                         printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2178                                                (unsigned int)dimm_num);
2179                                         printf("ERROR: Unsupported value for number of "
2180                                                "column addresses: %d.\n", (unsigned int)num_col_addr);
2181                                         printf("Replace the DIMM module with a supported DIMM.\n\n");
2182                                         spd_ddr_init_hang ();
2183                                 }
2184                         }
2185
2186                         if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2187                                 bank_0_populated = 1;
2188
2189                         for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
2190                                 mtsdram(SDRAM_MB0CF +
2191                                         ((dimm_num + bank_0_populated + ind_rank) << 2),
2192                                         mode);
2193                         }
2194                 }
2195         }
2196 }
2197
2198 /*------------------------------------------------------------------
2199  * program memory queue.
2200  *-----------------------------------------------------------------*/
2201 static void program_memory_queue(unsigned long *dimm_populated,
2202                                  unsigned char *iic0_dimm_addr,
2203                                  unsigned long num_dimm_banks)
2204 {
2205         unsigned long dimm_num;
2206         phys_size_t rank_base_addr;
2207         unsigned long rank_reg;
2208         phys_size_t rank_size_bytes;
2209         unsigned long rank_size_id;
2210         unsigned long num_ranks;
2211         unsigned long baseadd_size;
2212         unsigned long i;
2213         unsigned long bank_0_populated = 0;
2214         phys_size_t total_size = 0;
2215
2216         /*------------------------------------------------------------------
2217          * Reset the rank_base_address.
2218          *-----------------------------------------------------------------*/
2219         rank_reg   = SDRAM_R0BAS;
2220
2221         rank_base_addr = 0x00000000;
2222
2223         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2224                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2225                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2226                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2227                                 num_ranks = (num_ranks & 0x0F) + 1;
2228                         else
2229                                 num_ranks = num_ranks & 0x0F;
2230
2231                         rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2232
2233                         /*------------------------------------------------------------------
2234                          * Set the sizes
2235                          *-----------------------------------------------------------------*/
2236                         baseadd_size = 0;
2237                         switch (rank_size_id) {
2238                         case 0x01:
2239                                 baseadd_size |= SDRAM_RXBAS_SDSZ_1024;
2240                                 total_size = 1024;
2241                                 break;
2242                         case 0x02:
2243                                 baseadd_size |= SDRAM_RXBAS_SDSZ_2048;
2244                                 total_size = 2048;
2245                                 break;
2246                         case 0x04:
2247                                 baseadd_size |= SDRAM_RXBAS_SDSZ_4096;
2248                                 total_size = 4096;
2249                                 break;
2250                         case 0x08:
2251                                 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
2252                                 total_size = 32;
2253                                 break;
2254                         case 0x10:
2255                                 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
2256                                 total_size = 64;
2257                                 break;
2258                         case 0x20:
2259                                 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
2260                                 total_size = 128;
2261                                 break;
2262                         case 0x40:
2263                                 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
2264                                 total_size = 256;
2265                                 break;
2266                         case 0x80:
2267                                 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
2268                                 total_size = 512;
2269                                 break;
2270                         default:
2271                                 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2272                                        (unsigned int)dimm_num);
2273                                 printf("ERROR: Unsupported value for the banksize: %d.\n",
2274                                        (unsigned int)rank_size_id);
2275                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
2276                                 spd_ddr_init_hang ();
2277                         }
2278                         rank_size_bytes = total_size << 20;
2279
2280                         if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2281                                 bank_0_populated = 1;
2282
2283                         for (i = 0; i < num_ranks; i++) {
2284                                 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
2285                                           (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2286                                            baseadd_size));
2287                                 rank_base_addr += rank_size_bytes;
2288                         }
2289                 }
2290         }
2291
2292 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
2293     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
2294     defined(CONFIG_460SX)
2295         /*
2296          * Enable high bandwidth access
2297          * This is currently not used, but with this setup
2298          * it is possible to use it later on in e.g. the Linux
2299          * EMAC driver for performance gain.
2300          */
2301         mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
2302         mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
2303
2304         /*
2305          * Set optimal value for Memory Queue HB/LL Configuration registers
2306          */
2307         mtdcr(SDRAM_CONF1HB, (mfdcr(SDRAM_CONF1HB) & ~SDRAM_CONF1HB_MASK) |
2308               SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE |
2309               SDRAM_CONF1HB_RPLM | SDRAM_CONF1HB_WRCL);
2310         mtdcr(SDRAM_CONF1LL, (mfdcr(SDRAM_CONF1LL) & ~SDRAM_CONF1LL_MASK) |
2311               SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE |
2312               SDRAM_CONF1LL_RPLM);
2313         mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
2314 #endif
2315 }
2316
2317 #ifdef CONFIG_DDR_ECC
2318 /*-----------------------------------------------------------------------------+
2319  * program_ecc.
2320  *-----------------------------------------------------------------------------*/
2321 static void program_ecc(unsigned long *dimm_populated,
2322                         unsigned char *iic0_dimm_addr,
2323                         unsigned long num_dimm_banks,
2324                         unsigned long tlb_word2_i_value)
2325 {
2326         unsigned long dimm_num;
2327         unsigned long ecc;
2328
2329         ecc = 0;
2330         /* loop through all the DIMM slots on the board */
2331         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2332                 /* If a dimm is installed in a particular slot ... */
2333                 if (dimm_populated[dimm_num] != SDRAM_NONE)
2334                         ecc = max(ecc,
2335                                   (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11));
2336         }
2337         if (ecc == 0)
2338                 return;
2339
2340         do_program_ecc(tlb_word2_i_value);
2341 }
2342 #endif
2343
2344 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
2345 /*-----------------------------------------------------------------------------+
2346  * program_DQS_calibration.
2347  *-----------------------------------------------------------------------------*/
2348 static void program_DQS_calibration(unsigned long *dimm_populated,
2349                                     unsigned char *iic0_dimm_addr,
2350                                     unsigned long num_dimm_banks)
2351 {
2352         unsigned long val;
2353
2354 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2355         mtsdram(SDRAM_RQDC, 0x80000037);
2356         mtsdram(SDRAM_RDCC, 0x40000000);
2357         mtsdram(SDRAM_RFDC, 0x000001DF);
2358
2359         test();
2360 #else
2361         /*------------------------------------------------------------------
2362          * Program RDCC register
2363          * Read sample cycle auto-update enable
2364          *-----------------------------------------------------------------*/
2365
2366         mfsdram(SDRAM_RDCC, val);
2367         mtsdram(SDRAM_RDCC,
2368                 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
2369                 | SDRAM_RDCC_RSAE_ENABLE);
2370
2371         /*------------------------------------------------------------------
2372          * Program RQDC register
2373          * Internal DQS delay mechanism enable
2374          *-----------------------------------------------------------------*/
2375         mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2376
2377         /*------------------------------------------------------------------
2378          * Program RFDC register
2379          * Set Feedback Fractional Oversample
2380          * Auto-detect read sample cycle enable
2381          * Set RFOS to 1/4 of memclk cycle (0x3f)
2382          *-----------------------------------------------------------------*/
2383         mfsdram(SDRAM_RFDC, val);
2384         mtsdram(SDRAM_RFDC,
2385                 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2386                          SDRAM_RFDC_RFFD_MASK))
2387                 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0x3f) |
2388                    SDRAM_RFDC_RFFD_ENCODE(0)));
2389
2390         DQS_calibration_process();
2391 #endif
2392 }
2393
2394 static int short_mem_test(void)
2395 {
2396         u32 *membase;
2397         u32 bxcr_num;
2398         u32 bxcf;
2399         int i;
2400         int j;
2401         phys_size_t base_addr;
2402         u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2403                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2404                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2405                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2406                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2407                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2408                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2409                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2410                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2411                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2412                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2413                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2414                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2415                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2416                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2417                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2418                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2419         int l;
2420
2421         for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2422                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2423
2424                 /* Banks enabled */
2425                 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2426                         /* Bank is enabled */
2427
2428                         /*
2429                          * Only run test on accessable memory (below 2GB)
2430                          */
2431                         base_addr = SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num));
2432                         if (base_addr >= CONFIG_MAX_MEM_MAPPED)
2433                                 continue;
2434
2435                         /*------------------------------------------------------------------
2436                          * Run the short memory test.
2437                          *-----------------------------------------------------------------*/
2438                         membase = (u32 *)(u32)base_addr;
2439
2440                         for (i = 0; i < NUMMEMTESTS; i++) {
2441                                 for (j = 0; j < NUMMEMWORDS; j++) {
2442                                         membase[j] = test[i][j];
2443                                         ppcDcbf((u32)&(membase[j]));
2444                                 }
2445                                 sync();
2446                                 for (l=0; l<NUMLOOPS; l++) {
2447                                         for (j = 0; j < NUMMEMWORDS; j++) {
2448                                                 if (membase[j] != test[i][j]) {
2449                                                         ppcDcbf((u32)&(membase[j]));
2450                                                         return 0;
2451                                                 }
2452                                                 ppcDcbf((u32)&(membase[j]));
2453                                         }
2454                                         sync();
2455                                 }
2456                         }
2457                 }       /* if bank enabled */
2458         }               /* for bxcf_num */
2459
2460         return 1;
2461 }
2462
2463 #ifndef HARD_CODED_DQS
2464 /*-----------------------------------------------------------------------------+
2465  * DQS_calibration_process.
2466  *-----------------------------------------------------------------------------*/
2467 static void DQS_calibration_process(void)
2468 {
2469         unsigned long rfdc_reg;
2470         unsigned long rffd;
2471         unsigned long val;
2472         long rffd_average;
2473         long max_start;
2474         unsigned long dlycal;
2475         unsigned long dly_val;
2476         unsigned long max_pass_length;
2477         unsigned long current_pass_length;
2478         unsigned long current_fail_length;
2479         unsigned long current_start;
2480         long max_end;
2481         unsigned char fail_found;
2482         unsigned char pass_found;
2483 #if !defined(CONFIG_DDR_RQDC_FIXED)
2484         int window_found;
2485         u32 rqdc_reg;
2486         u32 rqfd;
2487         u32 rqfd_start;
2488         u32 rqfd_average;
2489         int loopi = 0;
2490         char str[] = "Auto calibration -";
2491         char slash[] = "\\|/-\\|/-";
2492
2493         /*------------------------------------------------------------------
2494          * Test to determine the best read clock delay tuning bits.
2495          *
2496          * Before the DDR controller can be used, the read clock delay needs to be
2497          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2498          * This value cannot be hardcoded into the program because it changes
2499          * depending on the board's setup and environment.
2500          * To do this, all delay values are tested to see if they
2501          * work or not.  By doing this, you get groups of fails with groups of
2502          * passing values.  The idea is to find the start and end of a passing
2503          * window and take the center of it to use as the read clock delay.
2504          *
2505          * A failure has to be seen first so that when we hit a pass, we know
2506          * that it is truely the start of the window.  If we get passing values
2507          * to start off with, we don't know if we are at the start of the window.
2508          *
2509          * The code assumes that a failure will always be found.
2510          * If a failure is not found, there is no easy way to get the middle
2511          * of the passing window.  I guess we can pretty much pick any value
2512          * but some values will be better than others.  Since the lowest speed
2513          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2514          * from experimentation it is safe to say you will always have a failure.
2515          *-----------------------------------------------------------------*/
2516
2517         /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2518         rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
2519
2520         puts(str);
2521
2522 calibration_loop:
2523         mfsdram(SDRAM_RQDC, rqdc_reg);
2524         mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2525                 SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
2526 #else /* CONFIG_DDR_RQDC_FIXED */
2527         /*
2528          * On Katmai the complete auto-calibration somehow doesn't seem to
2529          * produce the best results, meaning optimal values for RQFD/RFFD.
2530          * This was discovered by GDA using a high bandwidth scope,
2531          * analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
2532          * so now on Katmai "only" RFFD is auto-calibrated.
2533          */
2534         mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
2535 #endif /* CONFIG_DDR_RQDC_FIXED */
2536
2537         max_start = 0;
2538
2539         max_pass_length = 0;
2540         max_start = 0;
2541         max_end = 0;
2542         current_pass_length = 0;
2543         current_fail_length = 0;
2544         current_start = 0;
2545         fail_found = false;
2546         pass_found = false;
2547
2548         /*
2549          * get the delay line calibration register value
2550          */
2551         mfsdram(SDRAM_DLCR, dlycal);
2552         dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2553
2554         for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2555                 mfsdram(SDRAM_RFDC, rfdc_reg);
2556                 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2557
2558                 /*------------------------------------------------------------------
2559                  * Set the timing reg for the test.
2560                  *-----------------------------------------------------------------*/
2561                 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2562
2563                 /*------------------------------------------------------------------
2564                  * See if the rffd value passed.
2565                  *-----------------------------------------------------------------*/
2566                 if (short_mem_test()) {
2567                         if (fail_found == true) {
2568                                 pass_found = true;
2569                                 if (current_pass_length == 0)
2570                                         current_start = rffd;
2571
2572                                 current_fail_length = 0;
2573                                 current_pass_length++;
2574
2575                                 if (current_pass_length > max_pass_length) {
2576                                         max_pass_length = current_pass_length;
2577                                         max_start = current_start;
2578                                         max_end = rffd;
2579                                 }
2580                         }
2581                 } else {
2582                         current_pass_length = 0;
2583                         current_fail_length++;
2584
2585                         if (current_fail_length >= (dly_val >> 2)) {
2586                                 if (fail_found == false)
2587                                         fail_found = true;
2588                                 else if (pass_found == true)
2589                                         break;
2590                         }
2591                 }
2592         }               /* for rffd */
2593
2594         /*------------------------------------------------------------------
2595          * Set the average RFFD value
2596          *-----------------------------------------------------------------*/
2597         rffd_average = ((max_start + max_end) >> 1);
2598
2599         if (rffd_average < 0)
2600                 rffd_average = 0;
2601
2602         if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2603                 rffd_average = SDRAM_RFDC_RFFD_MAX;
2604         /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2605         mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2606
2607 #if !defined(CONFIG_DDR_RQDC_FIXED)
2608         max_pass_length = 0;
2609         max_start = 0;
2610         max_end = 0;
2611         current_pass_length = 0;
2612         current_fail_length = 0;
2613         current_start = 0;
2614         window_found = false;
2615         fail_found = false;
2616         pass_found = false;
2617
2618         for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2619                 mfsdram(SDRAM_RQDC, rqdc_reg);
2620                 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2621
2622                 /*------------------------------------------------------------------
2623                  * Set the timing reg for the test.
2624                  *-----------------------------------------------------------------*/
2625                 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2626
2627                 /*------------------------------------------------------------------
2628                  * See if the rffd value passed.
2629                  *-----------------------------------------------------------------*/
2630                 if (short_mem_test()) {
2631                         if (fail_found == true) {
2632                                 pass_found = true;
2633                                 if (current_pass_length == 0)
2634                                         current_start = rqfd;
2635
2636                                 current_fail_length = 0;
2637                                 current_pass_length++;
2638
2639                                 if (current_pass_length > max_pass_length) {
2640                                         max_pass_length = current_pass_length;
2641                                         max_start = current_start;
2642                                         max_end = rqfd;
2643                                 }
2644                         }
2645                 } else {
2646                         current_pass_length = 0;
2647                         current_fail_length++;
2648
2649                         if (fail_found == false) {
2650                                 fail_found = true;
2651                         } else if (pass_found == true) {
2652                                 window_found = true;
2653                                 break;
2654                         }
2655                 }
2656         }
2657
2658         rqfd_average = ((max_start + max_end) >> 1);
2659
2660         /*------------------------------------------------------------------
2661          * Make sure we found the valid read passing window.  Halt if not
2662          *-----------------------------------------------------------------*/
2663         if (window_found == false) {
2664                 if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
2665                         putc('\b');
2666                         putc(slash[loopi++ % 8]);
2667
2668                         /* try again from with a different RQFD start value */
2669                         rqfd_start++;
2670                         goto calibration_loop;
2671                 }
2672
2673                 printf("\nERROR: Cannot determine a common read delay for the "
2674                        "DIMM(s) installed.\n");
2675                 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2676                 ppc4xx_ibm_ddr2_register_dump();
2677                 spd_ddr_init_hang ();
2678         }
2679
2680         if (rqfd_average < 0)
2681                 rqfd_average = 0;
2682
2683         if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2684                 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2685
2686         mtsdram(SDRAM_RQDC,
2687                 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2688                 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2689
2690         blank_string(strlen(str));
2691 #endif /* CONFIG_DDR_RQDC_FIXED */
2692
2693         mfsdram(SDRAM_DLCR, val);
2694         debug("%s[%d] DLCR: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2695         mfsdram(SDRAM_RQDC, val);
2696         debug("%s[%d] RQDC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2697         mfsdram(SDRAM_RFDC, val);
2698         debug("%s[%d] RFDC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2699         mfsdram(SDRAM_RDCC, val);
2700         debug("%s[%d] RDCC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2701 }
2702 #else /* calibration test with hardvalues */
2703 /*-----------------------------------------------------------------------------+
2704  * DQS_calibration_process.
2705  *-----------------------------------------------------------------------------*/
2706 static void test(void)
2707 {
2708         unsigned long dimm_num;
2709         unsigned long ecc_temp;
2710         unsigned long i, j;
2711         unsigned long *membase;
2712         unsigned long bxcf[MAXRANKS];
2713         unsigned long val;
2714         char window_found;
2715         char begin_found[MAXDIMMS];
2716         char end_found[MAXDIMMS];
2717         char search_end[MAXDIMMS];
2718         unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2719                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2720                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2721                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2722                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2723                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2724                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2725                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2726                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2727                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2728                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2729                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2730                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2731                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2732                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2733                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2734                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2735
2736         /*------------------------------------------------------------------
2737          * Test to determine the best read clock delay tuning bits.
2738          *
2739          * Before the DDR controller can be used, the read clock delay needs to be
2740          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2741          * This value cannot be hardcoded into the program because it changes
2742          * depending on the board's setup and environment.
2743          * To do this, all delay values are tested to see if they
2744          * work or not.  By doing this, you get groups of fails with groups of
2745          * passing values.  The idea is to find the start and end of a passing
2746          * window and take the center of it to use as the read clock delay.
2747          *
2748          * A failure has to be seen first so that when we hit a pass, we know
2749          * that it is truely the start of the window.  If we get passing values
2750          * to start off with, we don't know if we are at the start of the window.
2751          *
2752          * The code assumes that a failure will always be found.
2753          * If a failure is not found, there is no easy way to get the middle
2754          * of the passing window.  I guess we can pretty much pick any value
2755          * but some values will be better than others.  Since the lowest speed
2756          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2757          * from experimentation it is safe to say you will always have a failure.
2758          *-----------------------------------------------------------------*/
2759         mfsdram(SDRAM_MCOPT1, ecc_temp);
2760         ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2761         mfsdram(SDRAM_MCOPT1, val);
2762         mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2763                 SDRAM_MCOPT1_MCHK_NON);
2764
2765         window_found = false;
2766         begin_found[0] = false;
2767         end_found[0] = false;
2768         search_end[0] = false;
2769         begin_found[1] = false;
2770         end_found[1] = false;
2771         search_end[1] = false;
2772
2773         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2774                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2775
2776                 /* Banks enabled */
2777                 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2778
2779                         /* Bank is enabled */
2780                         membase =
2781                                 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2782
2783                         /*------------------------------------------------------------------
2784                          * Run the short memory test.
2785                          *-----------------------------------------------------------------*/
2786                         for (i = 0; i < NUMMEMTESTS; i++) {
2787                                 for (j = 0; j < NUMMEMWORDS; j++) {
2788                                         membase[j] = test[i][j];
2789                                         ppcDcbf((u32)&(membase[j]));
2790                                 }
2791                                 sync();
2792                                 for (j = 0; j < NUMMEMWORDS; j++) {
2793                                         if (membase[j] != test[i][j]) {
2794                                                 ppcDcbf((u32)&(membase[j]));
2795                                                 break;
2796                                         }
2797                                         ppcDcbf((u32)&(membase[j]));
2798                                 }
2799                                 sync();
2800                                 if (j < NUMMEMWORDS)
2801                                         break;
2802                         }
2803
2804                         /*------------------------------------------------------------------
2805                          * See if the rffd value passed.
2806                          *-----------------------------------------------------------------*/
2807                         if (i < NUMMEMTESTS) {
2808                                 if ((end_found[dimm_num] == false) &&
2809                                     (search_end[dimm_num] == true)) {
2810                                         end_found[dimm_num] = true;
2811                                 }
2812                                 if ((end_found[0] == true) &&
2813                                     (end_found[1] == true))
2814                                         break;
2815                         } else {
2816                                 if (begin_found[dimm_num] == false) {
2817                                         begin_found[dimm_num] = true;
2818                                         search_end[dimm_num] = true;
2819                                 }
2820                         }
2821                 } else {
2822                         begin_found[dimm_num] = true;
2823                         end_found[dimm_num] = true;
2824                 }
2825         }
2826
2827         if ((begin_found[0] == true) && (begin_found[1] == true))
2828                 window_found = true;
2829
2830         /*------------------------------------------------------------------
2831          * Make sure we found the valid read passing window.  Halt if not
2832          *-----------------------------------------------------------------*/
2833         if (window_found == false) {
2834                 printf("ERROR: Cannot determine a common read delay for the "
2835                        "DIMM(s) installed.\n");
2836                 spd_ddr_init_hang ();
2837         }
2838
2839         /*------------------------------------------------------------------
2840          * Restore the ECC variable to what it originally was
2841          *-----------------------------------------------------------------*/
2842         mtsdram(SDRAM_MCOPT1,
2843                 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2844                 | ecc_temp);
2845 }
2846 #endif /* !HARD_CODED_DQS */
2847 #endif /* !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) */
2848
2849 #else /* CONFIG_SPD_EEPROM */
2850
2851 /*-----------------------------------------------------------------------------
2852  * Function:    initdram
2853  * Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller.
2854  *              The configuration is performed using static, compile-
2855  *              time parameters.
2856  *              Configures the PPC405EX(r) and PPC460EX/GT
2857  *---------------------------------------------------------------------------*/
2858 phys_size_t initdram(int board_type)
2859 {
2860         unsigned long val;
2861
2862 #if defined(CONFIG_440)
2863         mtdcr(SDRAM_R0BAS,      CONFIG_SYS_SDRAM_R0BAS);
2864         mtdcr(SDRAM_R1BAS,      CONFIG_SYS_SDRAM_R1BAS);
2865         mtdcr(SDRAM_R2BAS,      CONFIG_SYS_SDRAM_R2BAS);
2866         mtdcr(SDRAM_R3BAS,      CONFIG_SYS_SDRAM_R3BAS);
2867         mtdcr(SDRAM_PLBADDULL,  CONFIG_SYS_SDRAM_PLBADDULL);    /* MQ0_BAUL */
2868         mtdcr(SDRAM_PLBADDUHB,  CONFIG_SYS_SDRAM_PLBADDUHB);    /* MQ0_BAUH */
2869         mtdcr(SDRAM_CONF1LL,    CONFIG_SYS_SDRAM_CONF1LL);
2870         mtdcr(SDRAM_CONF1HB,    CONFIG_SYS_SDRAM_CONF1HB);
2871         mtdcr(SDRAM_CONFPATHB,  CONFIG_SYS_SDRAM_CONFPATHB);
2872 #endif
2873
2874         /* Set Memory Bank Configuration Registers */
2875
2876         mtsdram(SDRAM_MB0CF, CONFIG_SYS_SDRAM0_MB0CF);
2877         mtsdram(SDRAM_MB1CF, CONFIG_SYS_SDRAM0_MB1CF);
2878         mtsdram(SDRAM_MB2CF, CONFIG_SYS_SDRAM0_MB2CF);
2879         mtsdram(SDRAM_MB3CF, CONFIG_SYS_SDRAM0_MB3CF);
2880
2881         /* Set Memory Clock Timing Register */
2882
2883         mtsdram(SDRAM_CLKTR, CONFIG_SYS_SDRAM0_CLKTR);
2884
2885         /* Set Refresh Time Register */
2886
2887         mtsdram(SDRAM_RTR, CONFIG_SYS_SDRAM0_RTR);
2888
2889         /* Set SDRAM Timing Registers */
2890
2891         mtsdram(SDRAM_SDTR1, CONFIG_SYS_SDRAM0_SDTR1);
2892         mtsdram(SDRAM_SDTR2, CONFIG_SYS_SDRAM0_SDTR2);
2893         mtsdram(SDRAM_SDTR3, CONFIG_SYS_SDRAM0_SDTR3);
2894
2895         /* Set Mode and Extended Mode Registers */
2896
2897         mtsdram(SDRAM_MMODE, CONFIG_SYS_SDRAM0_MMODE);
2898         mtsdram(SDRAM_MEMODE, CONFIG_SYS_SDRAM0_MEMODE);
2899
2900         /* Set Memory Controller Options 1 Register */
2901
2902         mtsdram(SDRAM_MCOPT1, CONFIG_SYS_SDRAM0_MCOPT1);
2903
2904         /* Set Manual Initialization Control Registers */
2905
2906         mtsdram(SDRAM_INITPLR0, CONFIG_SYS_SDRAM0_INITPLR0);
2907         mtsdram(SDRAM_INITPLR1, CONFIG_SYS_SDRAM0_INITPLR1);
2908         mtsdram(SDRAM_INITPLR2, CONFIG_SYS_SDRAM0_INITPLR2);
2909         mtsdram(SDRAM_INITPLR3, CONFIG_SYS_SDRAM0_INITPLR3);
2910         mtsdram(SDRAM_INITPLR4, CONFIG_SYS_SDRAM0_INITPLR4);
2911         mtsdram(SDRAM_INITPLR5, CONFIG_SYS_SDRAM0_INITPLR5);
2912         mtsdram(SDRAM_INITPLR6, CONFIG_SYS_SDRAM0_INITPLR6);
2913         mtsdram(SDRAM_INITPLR7, CONFIG_SYS_SDRAM0_INITPLR7);
2914         mtsdram(SDRAM_INITPLR8, CONFIG_SYS_SDRAM0_INITPLR8);
2915         mtsdram(SDRAM_INITPLR9, CONFIG_SYS_SDRAM0_INITPLR9);
2916         mtsdram(SDRAM_INITPLR10, CONFIG_SYS_SDRAM0_INITPLR10);
2917         mtsdram(SDRAM_INITPLR11, CONFIG_SYS_SDRAM0_INITPLR11);
2918         mtsdram(SDRAM_INITPLR12, CONFIG_SYS_SDRAM0_INITPLR12);
2919         mtsdram(SDRAM_INITPLR13, CONFIG_SYS_SDRAM0_INITPLR13);
2920         mtsdram(SDRAM_INITPLR14, CONFIG_SYS_SDRAM0_INITPLR14);
2921         mtsdram(SDRAM_INITPLR15, CONFIG_SYS_SDRAM0_INITPLR15);
2922
2923         /* Set On-Die Termination Registers */
2924
2925         mtsdram(SDRAM_CODT, CONFIG_SYS_SDRAM0_CODT);
2926         mtsdram(SDRAM_MODT0, CONFIG_SYS_SDRAM0_MODT0);
2927         mtsdram(SDRAM_MODT1, CONFIG_SYS_SDRAM0_MODT1);
2928
2929         /* Set Write Timing Register */
2930
2931         mtsdram(SDRAM_WRDTR, CONFIG_SYS_SDRAM0_WRDTR);
2932
2933         /*
2934          * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
2935          * SDRAM0_MCOPT2[IPTR] = 1
2936          */
2937
2938         mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT |
2939                                SDRAM_MCOPT2_IPTR_EXECUTE));
2940
2941         /*
2942          * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
2943          * completion of initialization.
2944          */
2945
2946         do {
2947                 mfsdram(SDRAM_MCSTAT, val);
2948         } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
2949
2950         /* Set Delay Control Registers */
2951
2952         mtsdram(SDRAM_DLCR, CONFIG_SYS_SDRAM0_DLCR);
2953
2954 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
2955         mtsdram(SDRAM_RDCC, CONFIG_SYS_SDRAM0_RDCC);
2956         mtsdram(SDRAM_RQDC, CONFIG_SYS_SDRAM0_RQDC);
2957         mtsdram(SDRAM_RFDC, CONFIG_SYS_SDRAM0_RFDC);
2958 #endif /* !CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
2959
2960         /*
2961          * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
2962          */
2963
2964         mfsdram(SDRAM_MCOPT2, val);
2965         mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
2966
2967 #if defined(CONFIG_440)
2968         /*
2969          * Program TLB entries with caches enabled, for best performace
2970          * while auto-calibrating and ECC generation
2971          */
2972         program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), 0);
2973 #endif
2974
2975 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
2976         /*------------------------------------------------------------------
2977          | DQS calibration.
2978          +-----------------------------------------------------------------*/
2979         DQS_autocalibration();
2980 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
2981
2982         /*
2983          * Now complete RDSS configuration as mentioned on page 7 of the AMCC
2984          * PowerPC440SP/SPe DDR2 application note:
2985          * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
2986          */
2987         update_rdcc();
2988
2989 #if defined(CONFIG_DDR_ECC)
2990         do_program_ecc(0);
2991 #endif /* defined(CONFIG_DDR_ECC) */
2992
2993 #if defined(CONFIG_440)
2994         /*
2995          * Now after initialization (auto-calibration and ECC generation)
2996          * remove the TLB entries with caches enabled and program again with
2997          * desired cache functionality
2998          */
2999         remove_tlb(0, (CONFIG_SYS_MBYTES_SDRAM << 20));
3000         program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), MY_TLB_WORD2_I_ENABLE);
3001 #endif
3002
3003         ppc4xx_ibm_ddr2_register_dump();
3004
3005 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
3006         /*
3007          * Clear potential errors resulting from auto-calibration.
3008          * If not done, then we could get an interrupt later on when
3009          * exceptions are enabled.
3010          */
3011         set_mcsr(get_mcsr());
3012 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3013
3014         return (CONFIG_SYS_MBYTES_SDRAM << 20);
3015 }
3016 #endif /* CONFIG_SPD_EEPROM */
3017
3018 #if defined(CONFIG_440)
3019 u32 mfdcr_any(u32 dcr)
3020 {
3021         u32 val;
3022
3023         switch (dcr) {
3024         case SDRAM_R0BAS + 0:
3025                 val = mfdcr(SDRAM_R0BAS + 0);
3026                 break;
3027         case SDRAM_R0BAS + 1:
3028                 val = mfdcr(SDRAM_R0BAS + 1);
3029                 break;
3030         case SDRAM_R0BAS + 2:
3031                 val = mfdcr(SDRAM_R0BAS + 2);
3032                 break;
3033         case SDRAM_R0BAS + 3:
3034                 val = mfdcr(SDRAM_R0BAS + 3);
3035                 break;
3036         default:
3037                 printf("DCR %d not defined in case statement!!!\n", dcr);
3038                 val = 0; /* just to satisfy the compiler */
3039         }
3040
3041         return val;
3042 }
3043
3044 void mtdcr_any(u32 dcr, u32 val)
3045 {
3046         switch (dcr) {
3047         case SDRAM_R0BAS + 0:
3048                 mtdcr(SDRAM_R0BAS + 0, val);
3049                 break;
3050         case SDRAM_R0BAS + 1:
3051                 mtdcr(SDRAM_R0BAS + 1, val);
3052                 break;
3053         case SDRAM_R0BAS + 2:
3054                 mtdcr(SDRAM_R0BAS + 2, val);
3055                 break;
3056         case SDRAM_R0BAS + 3:
3057                 mtdcr(SDRAM_R0BAS + 3, val);
3058                 break;
3059         default:
3060                 printf("DCR %d not defined in case statement!!!\n", dcr);
3061         }
3062 }
3063 #endif /* defined(CONFIG_440) */
3064
3065 inline void ppc4xx_ibm_ddr2_register_dump(void)
3066 {
3067 #if defined(DEBUG)
3068         printf("\nPPC4xx IBM DDR2 Register Dump:\n");
3069
3070 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3071      defined(CONFIG_460EX) || defined(CONFIG_460GT))
3072         PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R0BAS);
3073         PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R1BAS);
3074         PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R2BAS);
3075         PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R3BAS);
3076 #endif /* (defined(CONFIG_440SP) || ... */
3077 #if defined(CONFIG_405EX)
3078         PPC4xx_IBM_DDR2_DUMP_REGISTER(BESR);
3079         PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARL);
3080         PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARH);
3081         PPC4xx_IBM_DDR2_DUMP_REGISTER(WMIRQ);
3082         PPC4xx_IBM_DDR2_DUMP_REGISTER(PLBOPT);
3083         PPC4xx_IBM_DDR2_DUMP_REGISTER(PUABA);
3084 #endif /* defined(CONFIG_405EX) */
3085         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB0CF);
3086         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB1CF);
3087         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB2CF);
3088         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB3CF);
3089         PPC4xx_IBM_DDR2_DUMP_REGISTER(MCSTAT);
3090         PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT1);
3091         PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT2);
3092         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT0);
3093         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT1);
3094         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT2);
3095         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT3);
3096         PPC4xx_IBM_DDR2_DUMP_REGISTER(CODT);
3097 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3098      defined(CONFIG_460EX) || defined(CONFIG_460GT))
3099         PPC4xx_IBM_DDR2_DUMP_REGISTER(VVPR);
3100         PPC4xx_IBM_DDR2_DUMP_REGISTER(OPARS);
3101         /*
3102          * OPART is only used as a trigger register.
3103          *
3104          * No data is contained in this register, and reading or writing
3105          * to is can cause bad things to happen (hangs). Just skip it and
3106          * report "N/A".
3107          */
3108         printf("%20s = N/A\n", "SDRAM_OPART");
3109 #endif /* defined(CONFIG_440SP) || ... */
3110         PPC4xx_IBM_DDR2_DUMP_REGISTER(RTR);
3111         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR0);
3112         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR1);
3113         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR2);
3114         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR3);
3115         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR4);
3116         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR5);
3117         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR6);
3118         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR7);
3119         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR8);
3120         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR9);
3121         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR10);
3122         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR11);
3123         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR12);
3124         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR13);
3125         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR14);
3126         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR15);
3127         PPC4xx_IBM_DDR2_DUMP_REGISTER(RQDC);
3128         PPC4xx_IBM_DDR2_DUMP_REGISTER(RFDC);
3129         PPC4xx_IBM_DDR2_DUMP_REGISTER(RDCC);
3130         PPC4xx_IBM_DDR2_DUMP_REGISTER(DLCR);
3131         PPC4xx_IBM_DDR2_DUMP_REGISTER(CLKTR);
3132         PPC4xx_IBM_DDR2_DUMP_REGISTER(WRDTR);
3133         PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR1);
3134         PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR2);
3135         PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR3);
3136         PPC4xx_IBM_DDR2_DUMP_REGISTER(MMODE);
3137         PPC4xx_IBM_DDR2_DUMP_REGISTER(MEMODE);
3138         PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCES);
3139 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3140      defined(CONFIG_460EX) || defined(CONFIG_460GT))
3141         PPC4xx_IBM_DDR2_DUMP_REGISTER(CID);
3142 #endif /* defined(CONFIG_440SP) || ... */
3143         PPC4xx_IBM_DDR2_DUMP_REGISTER(RID);
3144         PPC4xx_IBM_DDR2_DUMP_REGISTER(FCSR);
3145         PPC4xx_IBM_DDR2_DUMP_REGISTER(RTSR);
3146 #endif /* defined(DEBUG) */
3147 }