arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c

   1 /*
   2  * arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
   3  * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
   4  * DDR2 controller (non Denali Core). Those currently are:
   5  *
   6  * 405:         405EX(r)
   7  * 440/460:     440SP/440SPe/460EX/460GT
   8  *
   9  * Copyright (c) 2008 Nuovation System Designs, LLC
  10  *   Grant Erickson <gerickson@nuovations.com>
  11
  12  * (C) Copyright 2007-2009
  13  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  14  *
  15  * COPYRIGHT   AMCC   CORPORATION 2004
  16  *
  17  * SPDX-License-Identifier:     GPL-2.0+
  18  */
  19
  20 /* define DEBUG for debugging output (obviously ;-)) */
  21 #if 0
  22 #define DEBUG
  23 #endif
  24
  25 #include <common.h>
  26 #include <command.h>
  27 #include <asm/ppc4xx.h>
  28 #include <i2c.h>
  29 #include <asm/io.h>
  30 #include <asm/processor.h>
  31 #include <asm/mmu.h>
  32 #include <asm/cache.h>
  33
  34 #include "ecc.h"
  35
  36 #define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic)                         \
  37         do {                                                            \
  38                 u32 data;                                               \
  39                 mfsdram(SDRAM_##mnemonic, data);                        \
  40                 printf("%20s[%02x] = 0x%08X\n",                         \
  41                        "SDRAM_" #mnemonic, SDRAM_##mnemonic, data);     \
  42         } while (0)
  43
  44 #define PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(mnemonic)                      \
  45         do {                                                            \
  46                 u32 data;                                               \
  47                 data = mfdcr(SDRAM_##mnemonic);                         \
  48                 printf("%20s[%02x] = 0x%08X\n",                         \
  49                        "SDRAM_" #mnemonic, SDRAM_##mnemonic, data);     \
  50         } while (0)
  51
  52 static void update_rdcc(void)
  53 {
  54         u32 val;
  55
  56         /*
  57          * Complete RDSS configuration as mentioned on page 7 of the AMCC
  58          * PowerPC440SP/SPe DDR2 application note:
  59          * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
  60          *
  61          * Or item #10 "10. Complete RDSS configuration" in chapter
  62          * "22.2.9 SDRAM Initialization" of AMCC PPC460EX/EXr/GT users
  63          * manual.
  64          */
  65         mfsdram(SDRAM_RTSR, val);
  66         if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
  67                 mfsdram(SDRAM_RDCC, val);
  68                 if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
  69                         val += 0x40000000;
  70                         mtsdram(SDRAM_RDCC, val);
  71                 }
  72         }
  73 }
  74
  75 #if defined(CONFIG_440)
  76 /*
  77  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2
  78  * memory region. Right now the cache should still be disabled in U-Boot
  79  * because of the EMAC driver, that need its buffer descriptor to be located
  80  * in non cached memory.
  81  *
  82  * If at some time this restriction doesn't apply anymore, just define
  83  * CONFIG_4xx_DCACHE in the board config file and this code should setup
  84  * everything correctly.
  85  */
  86 #ifdef CONFIG_4xx_DCACHE
  87 /* enable caching on SDRAM */
  88 #define MY_TLB_WORD2_I_ENABLE           0
  89 #else
  90 /* disable caching on SDRAM */
  91 #define MY_TLB_WORD2_I_ENABLE           TLB_WORD2_I_ENABLE
  92 #endif /* CONFIG_4xx_DCACHE */
  93
  94 void dcbz_area(u32 start_address, u32 num_bytes);
  95 #endif /* CONFIG_440 */
  96
  97 #define MAXRANKS        4
  98 #define MAXBXCF         4
  99
 100 #define MULDIV64(m1, m2, d)     (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
 101
 102 /*-----------------------------------------------------------------------------+
 103  * sdram_memsize
 104  *-----------------------------------------------------------------------------*/
 105 phys_size_t sdram_memsize(void)
 106 {
 107         phys_size_t mem_size;
 108         unsigned long mcopt2;
 109         unsigned long mcstat;
 110         unsigned long mb0cf;
 111         unsigned long sdsz;
 112         unsigned long i;
 113
 114         mem_size = 0;
 115
 116         mfsdram(SDRAM_MCOPT2, mcopt2);
 117         mfsdram(SDRAM_MCSTAT, mcstat);
 118
 119         /* DDR controller must be enabled and not in self-refresh. */
 120         /* Otherwise memsize is zero. */
 121         if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
 122             && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
 123             && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
 124                 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
 125                 for (i = 0; i < MAXBXCF; i++) {
 126                         mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
 127                         /* Banks enabled */
 128                         if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
 129 #if defined(CONFIG_440)
 130                                 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
 131 #else
 132                                 sdsz = mb0cf & SDRAM_RXBAS_SDSZ_MASK;
 133 #endif
 134                                 switch(sdsz) {
 135                                 case SDRAM_RXBAS_SDSZ_8:
 136                                         mem_size+=8;
 137                                         break;
 138                                 case SDRAM_RXBAS_SDSZ_16:
 139                                         mem_size+=16;
 140                                         break;
 141                                 case SDRAM_RXBAS_SDSZ_32:
 142                                         mem_size+=32;
 143                                         break;
 144                                 case SDRAM_RXBAS_SDSZ_64:
 145                                         mem_size+=64;
 146                                         break;
 147                                 case SDRAM_RXBAS_SDSZ_128:
 148                                         mem_size+=128;
 149                                         break;
 150                                 case SDRAM_RXBAS_SDSZ_256:
 151                                         mem_size+=256;
 152                                         break;
 153                                 case SDRAM_RXBAS_SDSZ_512:
 154                                         mem_size+=512;
 155                                         break;
 156                                 case SDRAM_RXBAS_SDSZ_1024:
 157                                         mem_size+=1024;
 158                                         break;
 159                                 case SDRAM_RXBAS_SDSZ_2048:
 160                                         mem_size+=2048;
 161                                         break;
 162                                 case SDRAM_RXBAS_SDSZ_4096:
 163                                         mem_size+=4096;
 164                                         break;
 165                                 default:
 166                                         printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n"
 167                                                , sdsz);
 168                                         mem_size=0;
 169                                         break;
 170                                 }
 171                         }
 172                 }
 173         }
 174
 175         return mem_size << 20;
 176 }
 177
 178 /*-----------------------------------------------------------------------------+
 179  * is_ecc_enabled
 180  *-----------------------------------------------------------------------------*/
 181 static unsigned long is_ecc_enabled(void)
 182 {
 183         unsigned long val;
 184
 185         mfsdram(SDRAM_MCOPT1, val);
 186
 187         return SDRAM_MCOPT1_MCHK_CHK_DECODE(val);
 188 }
 189
 190 /*-----------------------------------------------------------------------------+
 191  * board_add_ram_info
 192  *-----------------------------------------------------------------------------*/
 193 void board_add_ram_info(int use_default)
 194 {
 195         PPC4xx_SYS_INFO board_cfg;
 196         u32 val;
 197
 198         if (is_ecc_enabled())
 199                 puts(" (ECC");
 200         else
 201                 puts(" (ECC not");
 202
 203         get_sys_info(&board_cfg);
 204
 205 #if defined(CONFIG_405EX)
 206         val = board_cfg.freqPLB;
 207 #else
 208         mfsdr(SDR0_DDR0, val);
 209         val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
 210 #endif
 211         printf(" enabled, %d MHz", (val * 2) / 1000000);
 212
 213         mfsdram(SDRAM_MMODE, val);
 214         val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
 215         printf(", CL%d)", val);
 216 }
 217
 218 #if defined(CONFIG_SPD_EEPROM)
 219
 220 /*-----------------------------------------------------------------------------+
 221  * Defines
 222  *-----------------------------------------------------------------------------*/
 223 #define SDRAM_DDR1      1
 224 #define SDRAM_DDR2      2
 225 #define SDRAM_NONE      0
 226
 227 #define MAXDIMMS        2
 228 #define MAX_SPD_BYTES   256   /* Max number of bytes on the DIMM's SPD EEPROM */
 229
 230 #define ONE_BILLION     1000000000
 231
 232 #define CMD_NOP         (7 << 19)
 233 #define CMD_PRECHARGE   (2 << 19)
 234 #define CMD_REFRESH     (1 << 19)
 235 #define CMD_EMR         (0 << 19)
 236 #define CMD_READ        (5 << 19)
 237 #define CMD_WRITE       (4 << 19)
 238
 239 #define SELECT_MR       (0 << 16)
 240 #define SELECT_EMR      (1 << 16)
 241 #define SELECT_EMR2     (2 << 16)
 242 #define SELECT_EMR3     (3 << 16)
 243
 244 /* MR */
 245 #define DLL_RESET       0x00000100
 246
 247 #define WRITE_RECOV_2   (1 << 9)
 248 #define WRITE_RECOV_3   (2 << 9)
 249 #define WRITE_RECOV_4   (3 << 9)
 250 #define WRITE_RECOV_5   (4 << 9)
 251 #define WRITE_RECOV_6   (5 << 9)
 252
 253 #define BURST_LEN_4     0x00000002
 254
 255 /* EMR */
 256 #define ODT_0_OHM       0x00000000
 257 #define ODT_50_OHM      0x00000044
 258 #define ODT_75_OHM      0x00000004
 259 #define ODT_150_OHM     0x00000040
 260
 261 #define ODS_FULL        0x00000000
 262 #define ODS_REDUCED     0x00000002
 263 #define OCD_CALIB_DEF   0x00000380
 264
 265 /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
 266 #define ODT_EB0R        (0x80000000 >> 8)
 267 #define ODT_EB0W        (0x80000000 >> 7)
 268 #define CALC_ODT_R(n)   (ODT_EB0R << (n << 1))
 269 #define CALC_ODT_W(n)   (ODT_EB0W << (n << 1))
 270 #define CALC_ODT_RW(n)  (CALC_ODT_R(n) | CALC_ODT_W(n))
 271
 272 /* Defines for the Read Cycle Delay test */
 273 #define NUMMEMTESTS     8
 274 #define NUMMEMWORDS     8
 275 #define NUMLOOPS        64              /* memory test loops */
 276
 277 /*
 278  * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
 279  * To support such configurations, we "only" map the first 2GB via the TLB's. We
 280  * need some free virtual address space for the remaining peripherals like, SoC
 281  * devices, FLASH etc.
 282  *
 283  * Note that ECC is currently not supported on configurations with more than 2GB
 284  * SDRAM. This is because we only map the first 2GB on such systems, and therefore
 285  * the ECC parity byte of the remaining area can't be written.
 286  */
 287
 288 /*
 289  * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
 290  */
 291 void __spd_ddr_init_hang (void)
 292 {
 293         hang ();
 294 }
 295 void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
 296
 297 /*
 298  * To provide an interface for board specific config values in this common
 299  * DDR setup code, we implement he "weak" default functions here. They return
 300  * the default value back to the caller.
 301  *
 302  * Please see include/configs/yucca.h for an example fora board specific
 303  * implementation.
 304  */
 305 u32 __ddr_wrdtr(u32 default_val)
 306 {
 307         return default_val;
 308 }
 309 u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
 310
 311 u32 __ddr_clktr(u32 default_val)
 312 {
 313         return default_val;
 314 }
 315 u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
 316
 317
 318 /* Private Structure Definitions */
 319
 320 /* enum only to ease code for cas latency setting */
 321 typedef enum ddr_cas_id {
 322         DDR_CAS_2      = 20,
 323         DDR_CAS_2_5    = 25,
 324         DDR_CAS_3      = 30,
 325         DDR_CAS_4      = 40,
 326         DDR_CAS_5      = 50
 327 } ddr_cas_id_t;
 328
 329 /*-----------------------------------------------------------------------------+
 330  * Prototypes
 331  *-----------------------------------------------------------------------------*/
 332 static void get_spd_info(unsigned long *dimm_populated,
 333                          unsigned char *iic0_dimm_addr,
 334                          unsigned long num_dimm_banks);
 335 static void check_mem_type(unsigned long *dimm_populated,
 336                            unsigned char *iic0_dimm_addr,
 337                            unsigned long num_dimm_banks);
 338 static void check_frequency(unsigned long *dimm_populated,
 339                             unsigned char *iic0_dimm_addr,
 340                             unsigned long num_dimm_banks);
 341 static void check_rank_number(unsigned long *dimm_populated,
 342                               unsigned char *iic0_dimm_addr,
 343                               unsigned long num_dimm_banks);
 344 static void check_voltage_type(unsigned long *dimm_populated,
 345                                unsigned char *iic0_dimm_addr,
 346                                unsigned long num_dimm_banks);
 347 static void program_memory_queue(unsigned long *dimm_populated,
 348                                  unsigned char *iic0_dimm_addr,
 349                                  unsigned long num_dimm_banks);
 350 static void program_codt(unsigned long *dimm_populated,
 351                          unsigned char *iic0_dimm_addr,
 352                          unsigned long num_dimm_banks);
 353 static void program_mode(unsigned long *dimm_populated,
 354                          unsigned char *iic0_dimm_addr,
 355                          unsigned long num_dimm_banks,
 356                          ddr_cas_id_t *selected_cas,
 357                          int *write_recovery);
 358 static void program_tr(unsigned long *dimm_populated,
 359                        unsigned char *iic0_dimm_addr,
 360                        unsigned long num_dimm_banks);
 361 static void program_rtr(unsigned long *dimm_populated,
 362                         unsigned char *iic0_dimm_addr,
 363                         unsigned long num_dimm_banks);
 364 static void program_bxcf(unsigned long *dimm_populated,
 365                          unsigned char *iic0_dimm_addr,
 366                          unsigned long num_dimm_banks);
 367 static void program_copt1(unsigned long *dimm_populated,
 368                           unsigned char *iic0_dimm_addr,
 369                           unsigned long num_dimm_banks);
 370 static void program_initplr(unsigned long *dimm_populated,
 371                             unsigned char *iic0_dimm_addr,
 372                             unsigned long num_dimm_banks,
 373                             ddr_cas_id_t selected_cas,
 374                             int write_recovery);
 375 #ifdef CONFIG_DDR_ECC
 376 static void program_ecc(unsigned long *dimm_populated,
 377                         unsigned char *iic0_dimm_addr,
 378                         unsigned long num_dimm_banks,
 379                         unsigned long tlb_word2_i_value);
 380 #endif
 381 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
 382 static void program_DQS_calibration(unsigned long *dimm_populated,
 383                                 unsigned char *iic0_dimm_addr,
 384                                 unsigned long num_dimm_banks);
 385 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
 386 static void     test(void);
 387 #else
 388 static void     DQS_calibration_process(void);
 389 #endif
 390 #endif
 391
 392 static unsigned char spd_read(uchar chip, uint addr)
 393 {
 394         unsigned char data[2];
 395
 396         if (i2c_probe(chip) == 0)
 397                 if (i2c_read(chip, addr, 1, data, 1) == 0)
 398                         return data[0];
 399
 400         return 0;
 401 }
 402
 403 /*-----------------------------------------------------------------------------+
 404  * initdram.  Initializes the 440SP Memory Queue and DDR SDRAM controller.
 405  * Note: This routine runs from flash with a stack set up in the chip's
 406  * sram space.  It is important that the routine does not require .sbss, .bss or
 407  * .data sections.  It also cannot call routines that require these sections.
 408  *-----------------------------------------------------------------------------*/
 409 /*-----------------------------------------------------------------------------
 410  * Function:     initdram
 411  * Description:  Configures SDRAM memory banks for DDR operation.
 412  *               Auto Memory Configuration option reads the DDR SDRAM EEPROMs
 413  *               via the IIC bus and then configures the DDR SDRAM memory
 414  *               banks appropriately. If Auto Memory Configuration is
 415  *               not used, it is assumed that no DIMM is plugged
 416  *-----------------------------------------------------------------------------*/
 417 phys_size_t initdram(int board_type)
 418 {
 419         unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 420         unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE};
 421         unsigned long num_dimm_banks;           /* on board dimm banks */
 422         unsigned long val;
 423         ddr_cas_id_t selected_cas = DDR_CAS_5;  /* preset to silence compiler */
 424         int write_recovery;
 425         phys_size_t dram_size = 0;
 426
 427         num_dimm_banks = sizeof(iic0_dimm_addr);
 428
 429         /*------------------------------------------------------------------
 430          * Reset the DDR-SDRAM controller.
 431          *-----------------------------------------------------------------*/
 432         mtsdr(SDR0_SRST, SDR0_SRST0_DMC);
 433         mtsdr(SDR0_SRST, 0x00000000);
 434
 435         /*
 436          * Make sure I2C controller is initialized
 437          * before continuing.
 438          */
 439
 440         /* switch to correct I2C bus */
 441         i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
 442
 443         /*------------------------------------------------------------------
 444          * Clear out the serial presence detect buffers.
 445          * Perform IIC reads from the dimm.  Fill in the spds.
 446          * Check to see if the dimm slots are populated
 447          *-----------------------------------------------------------------*/
 448         get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 449
 450         /*------------------------------------------------------------------
 451          * Check the memory type for the dimms plugged.
 452          *-----------------------------------------------------------------*/
 453         check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 454
 455         /*------------------------------------------------------------------
 456          * Check the frequency supported for the dimms plugged.
 457          *-----------------------------------------------------------------*/
 458         check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 459
 460         /*------------------------------------------------------------------
 461          * Check the total rank number.
 462          *-----------------------------------------------------------------*/
 463         check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 464
 465         /*------------------------------------------------------------------
 466          * Check the voltage type for the dimms plugged.
 467          *-----------------------------------------------------------------*/
 468         check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 469
 470         /*------------------------------------------------------------------
 471          * Program SDRAM controller options 2 register
 472          * Except Enabling of the memory controller.
 473          *-----------------------------------------------------------------*/
 474         mfsdram(SDRAM_MCOPT2, val);
 475         mtsdram(SDRAM_MCOPT2,
 476                 (val &
 477                  ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
 478                    SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
 479                    SDRAM_MCOPT2_ISIE_MASK))
 480                 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
 481                    SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
 482                    SDRAM_MCOPT2_ISIE_ENABLE));
 483
 484         /*------------------------------------------------------------------
 485          * Program SDRAM controller options 1 register
 486          * Note: Does not enable the memory controller.
 487          *-----------------------------------------------------------------*/
 488         program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 489
 490         /*------------------------------------------------------------------
 491          * Set the SDRAM Controller On Die Termination Register
 492          *-----------------------------------------------------------------*/
 493         program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 494
 495         /*------------------------------------------------------------------
 496          * Program SDRAM refresh register.
 497          *-----------------------------------------------------------------*/
 498         program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 499
 500         /*------------------------------------------------------------------
 501          * Program SDRAM mode register.
 502          *-----------------------------------------------------------------*/
 503         program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 504                      &selected_cas, &write_recovery);
 505
 506         /*------------------------------------------------------------------
 507          * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
 508          *-----------------------------------------------------------------*/
 509         mfsdram(SDRAM_WRDTR, val);
 510         mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
 511                 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
 512
 513         /*------------------------------------------------------------------
 514          * Set the SDRAM Clock Timing Register
 515          *-----------------------------------------------------------------*/
 516         mfsdram(SDRAM_CLKTR, val);
 517         mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
 518                 ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
 519
 520         /*------------------------------------------------------------------
 521          * Program the BxCF registers.
 522          *-----------------------------------------------------------------*/
 523         program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 524
 525         /*------------------------------------------------------------------
 526          * Program SDRAM timing registers.
 527          *-----------------------------------------------------------------*/
 528         program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 529
 530         /*------------------------------------------------------------------
 531          * Set the Extended Mode register
 532          *-----------------------------------------------------------------*/
 533         mfsdram(SDRAM_MEMODE, val);
 534         mtsdram(SDRAM_MEMODE,
 535                 (val & ~(SDRAM_MEMODE_DIC_MASK  | SDRAM_MEMODE_DLL_MASK |
 536                          SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
 537                 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
 538                  | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
 539
 540         /*------------------------------------------------------------------
 541          * Program Initialization preload registers.
 542          *-----------------------------------------------------------------*/
 543         program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 544                         selected_cas, write_recovery);
 545
 546         /*------------------------------------------------------------------
 547          * Delay to ensure 200usec have elapsed since reset.
 548          *-----------------------------------------------------------------*/
 549         udelay(400);
 550
 551         /*------------------------------------------------------------------
 552          * Set the memory queue core base addr.
 553          *-----------------------------------------------------------------*/
 554         program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 555
 556         /*------------------------------------------------------------------
 557          * Program SDRAM controller options 2 register
 558          * Enable the memory controller.
 559          *-----------------------------------------------------------------*/
 560         mfsdram(SDRAM_MCOPT2, val);
 561         mtsdram(SDRAM_MCOPT2,
 562                 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
 563                          SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
 564                          SDRAM_MCOPT2_IPTR_EXECUTE);
 565
 566         /*------------------------------------------------------------------
 567          * Wait for IPTR_EXECUTE init sequence to complete.
 568          *-----------------------------------------------------------------*/
 569         do {
 570                 mfsdram(SDRAM_MCSTAT, val);
 571         } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
 572
 573         /* enable the controller only after init sequence completes */
 574         mfsdram(SDRAM_MCOPT2, val);
 575         mtsdram(SDRAM_MCOPT2, (val | SDRAM_MCOPT2_DCEN_ENABLE));
 576
 577         /* Make sure delay-line calibration is done before proceeding */
 578         do {
 579                 mfsdram(SDRAM_DLCR, val);
 580         } while (!(val & SDRAM_DLCR_DLCS_COMPLETE));
 581
 582         /* get installed memory size */
 583         dram_size = sdram_memsize();
 584
 585         /*
 586          * Limit size to 2GB
 587          */
 588         if (dram_size > CONFIG_MAX_MEM_MAPPED)
 589                 dram_size = CONFIG_MAX_MEM_MAPPED;
 590
 591         /* and program tlb entries for this size (dynamic) */
 592
 593         /*
 594          * Program TLB entries with caches enabled, for best performace
 595          * while auto-calibrating and ECC generation
 596          */
 597         program_tlb(0, 0, dram_size, 0);
 598
 599         /*------------------------------------------------------------------
 600          * DQS calibration.
 601          *-----------------------------------------------------------------*/
 602 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
 603         DQS_autocalibration();
 604 #else
 605         program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 606 #endif
 607         /*
 608          * Now complete RDSS configuration as mentioned on page 7 of the AMCC
 609          * PowerPC440SP/SPe DDR2 application note:
 610          * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
 611          */
 612         update_rdcc();
 613
 614 #ifdef CONFIG_DDR_ECC
 615         /*------------------------------------------------------------------
 616          * If ecc is enabled, initialize the parity bits.
 617          *-----------------------------------------------------------------*/
 618         program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
 619 #endif
 620
 621         /*
 622          * Flush the dcache before removing the TLB with caches
 623          * enabled. Otherwise this might lead to problems later on,
 624          * e.g. while booting Linux (as seen on ICON-440SPe).
 625          */
 626         flush_dcache();
 627
 628         /*
 629          * Now after initialization (auto-calibration and ECC generation)
 630          * remove the TLB entries with caches enabled and program again with
 631          * desired cache functionality
 632          */
 633         remove_tlb(0, dram_size);
 634         program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
 635
 636         ppc4xx_ibm_ddr2_register_dump();
 637
 638         /*
 639          * Clear potential errors resulting from auto-calibration.
 640          * If not done, then we could get an interrupt later on when
 641          * exceptions are enabled.
 642          */
 643         set_mcsr(get_mcsr());
 644
 645         return sdram_memsize();
 646 }
 647
 648 static void get_spd_info(unsigned long *dimm_populated,
 649                          unsigned char *iic0_dimm_addr,
 650                          unsigned long num_dimm_banks)
 651 {
 652         unsigned long dimm_num;
 653         unsigned long dimm_found;
 654         unsigned char num_of_bytes;
 655         unsigned char total_size;
 656
 657         dimm_found = false;
 658         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 659                 num_of_bytes = 0;
 660                 total_size = 0;
 661
 662                 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
 663                 debug("\nspd_read(0x%x) returned %d\n",
 664                       iic0_dimm_addr[dimm_num], num_of_bytes);
 665                 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 666                 debug("spd_read(0x%x) returned %d\n",
 667                       iic0_dimm_addr[dimm_num], total_size);
 668
 669                 if ((num_of_bytes != 0) && (total_size != 0)) {
 670                         dimm_populated[dimm_num] = true;
 671                         dimm_found = true;
 672                         debug("DIMM slot %lu: populated\n", dimm_num);
 673                 } else {
 674                         dimm_populated[dimm_num] = false;
 675                         debug("DIMM slot %lu: Not populated\n", dimm_num);
 676                 }
 677         }
 678
 679         if (dimm_found == false) {
 680                 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
 681                 spd_ddr_init_hang ();
 682         }
 683 }
 684
 685
 686 /*------------------------------------------------------------------
 687  * For the memory DIMMs installed, this routine verifies that they
 688  * really are DDR specific DIMMs.
 689  *-----------------------------------------------------------------*/
 690 static void check_mem_type(unsigned long *dimm_populated,
 691                            unsigned char *iic0_dimm_addr,
 692                            unsigned long num_dimm_banks)
 693 {
 694         unsigned long dimm_num;
 695         unsigned long dimm_type;
 696
 697         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 698                 if (dimm_populated[dimm_num] == true) {
 699                         dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
 700                         switch (dimm_type) {
 701                         case 1:
 702                                 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
 703                                        "slot %d.\n", (unsigned int)dimm_num);
 704                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 705                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 706                                 spd_ddr_init_hang ();
 707                                 break;
 708                         case 2:
 709                                 printf("ERROR: EDO DIMM detected in slot %d.\n",
 710                                        (unsigned int)dimm_num);
 711                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 712                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 713                                 spd_ddr_init_hang ();
 714                                 break;
 715                         case 3:
 716                                 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
 717                                        (unsigned int)dimm_num);
 718                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 719                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 720                                 spd_ddr_init_hang ();
 721                                 break;
 722                         case 4:
 723                                 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
 724                                        (unsigned int)dimm_num);
 725                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 726                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 727                                 spd_ddr_init_hang ();
 728                                 break;
 729                         case 5:
 730                                 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
 731                                        (unsigned int)dimm_num);
 732                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 733                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 734                                 spd_ddr_init_hang ();
 735                                 break;
 736                         case 6:
 737                                 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
 738                                        (unsigned int)dimm_num);
 739                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 740                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 741                                 spd_ddr_init_hang ();
 742                                 break;
 743                         case 7:
 744                                 debug("DIMM slot %lu: DDR1 SDRAM detected\n", dimm_num);
 745                                 dimm_populated[dimm_num] = SDRAM_DDR1;
 746                                 break;
 747                         case 8:
 748                                 debug("DIMM slot %lu: DDR2 SDRAM detected\n", dimm_num);
 749                                 dimm_populated[dimm_num] = SDRAM_DDR2;
 750                                 break;
 751                         default:
 752                                 printf("ERROR: Unknown DIMM detected in slot %d.\n",
 753                                        (unsigned int)dimm_num);
 754                                 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
 755                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 756                                 spd_ddr_init_hang ();
 757                                 break;
 758                         }
 759                 }
 760         }
 761         for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
 762                 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
 763                     && (dimm_populated[dimm_num]   != SDRAM_NONE)
 764                     && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
 765                         printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
 766                         spd_ddr_init_hang ();
 767                 }
 768         }
 769 }
 770
 771 /*------------------------------------------------------------------
 772  * For the memory DIMMs installed, this routine verifies that
 773  * frequency previously calculated is supported.
 774  *-----------------------------------------------------------------*/
 775 static void check_frequency(unsigned long *dimm_populated,
 776                             unsigned char *iic0_dimm_addr,
 777                             unsigned long num_dimm_banks)
 778 {
 779         unsigned long dimm_num;
 780         unsigned long tcyc_reg;
 781         unsigned long cycle_time;
 782         unsigned long calc_cycle_time;
 783         unsigned long sdram_freq;
 784         unsigned long sdr_ddrpll;
 785         PPC4xx_SYS_INFO board_cfg;
 786
 787         /*------------------------------------------------------------------
 788          * Get the board configuration info.
 789          *-----------------------------------------------------------------*/
 790         get_sys_info(&board_cfg);
 791
 792         mfsdr(SDR0_DDR0, sdr_ddrpll);
 793         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
 794
 795         /*
 796          * calc_cycle_time is calculated from DDR frequency set by board/chip
 797          * and is expressed in multiple of 10 picoseconds
 798          * to match the way DIMM cycle time is calculated below.
 799          */
 800         calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
 801
 802         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 803                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 804                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
 805                         /*
 806                          * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
 807                          * the higher order nibble (bits 4-7) designates the cycle time
 808                          * to a granularity of 1ns;
 809                          * the value presented by the lower order nibble (bits 0-3)
 810                          * has a granularity of .1ns and is added to the value designated
 811                          * by the higher nibble. In addition, four lines of the lower order
 812                          * nibble are assigned to support +.25,+.33, +.66 and +.75.
 813                          */
 814                          /* Convert from hex to decimal */
 815                         if ((tcyc_reg & 0x0F) == 0x0D)
 816                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
 817                         else if ((tcyc_reg & 0x0F) == 0x0C)
 818                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
 819                         else if ((tcyc_reg & 0x0F) == 0x0B)
 820                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
 821                         else if ((tcyc_reg & 0x0F) == 0x0A)
 822                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
 823                         else
 824                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
 825                                         ((tcyc_reg & 0x0F)*10);
 826                         debug("cycle_time=%lu [10 picoseconds]\n", cycle_time);
 827
 828                         if  (cycle_time > (calc_cycle_time + 10)) {
 829                                 /*
 830                                  * the provided sdram cycle_time is too small
 831                                  * for the available DIMM cycle_time.
 832                                  * The additionnal 100ps is here to accept a small incertainty.
 833                                  */
 834                                 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
 835                                        "slot %d \n while calculated cycle time is %d ps.\n",
 836                                        (unsigned int)(cycle_time*10),
 837                                        (unsigned int)dimm_num,
 838                                        (unsigned int)(calc_cycle_time*10));
 839                                 printf("Replace the DIMM, or change DDR frequency via "
 840                                        "strapping bits.\n\n");
 841                                 spd_ddr_init_hang ();
 842                         }
 843                 }
 844         }
 845 }
 846
 847 /*------------------------------------------------------------------
 848  * For the memory DIMMs installed, this routine verifies two
 849  * ranks/banks maximum are availables.
 850  *-----------------------------------------------------------------*/
 851 static void check_rank_number(unsigned long *dimm_populated,
 852                               unsigned char *iic0_dimm_addr,
 853                               unsigned long num_dimm_banks)
 854 {
 855         unsigned long dimm_num;
 856         unsigned long dimm_rank;
 857         unsigned long total_rank = 0;
 858
 859         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 860                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 861                         dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
 862                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
 863                                 dimm_rank = (dimm_rank & 0x0F) +1;
 864                         else
 865                                 dimm_rank = dimm_rank & 0x0F;
 866
 867
 868                         if (dimm_rank > MAXRANKS) {
 869                                 printf("ERROR: DRAM DIMM detected with %lu ranks in "
 870                                        "slot %lu is not supported.\n", dimm_rank, dimm_num);
 871                                 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 872                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 873                                 spd_ddr_init_hang ();
 874                         } else
 875                                 total_rank += dimm_rank;
 876                 }
 877                 if (total_rank > MAXRANKS) {
 878                         printf("ERROR: DRAM DIMM detected with a total of %d ranks "
 879                                "for all slots.\n", (unsigned int)total_rank);
 880                         printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 881                         printf("Remove one of the DIMM modules.\n\n");
 882                         spd_ddr_init_hang ();
 883                 }
 884         }
 885 }
 886
 887 /*------------------------------------------------------------------
 888  * only support 2.5V modules.
 889  * This routine verifies this.
 890  *-----------------------------------------------------------------*/
 891 static void check_voltage_type(unsigned long *dimm_populated,
 892                                unsigned char *iic0_dimm_addr,
 893                                unsigned long num_dimm_banks)
 894 {
 895         unsigned long dimm_num;
 896         unsigned long voltage_type;
 897
 898         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 899                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 900                         voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
 901                         switch (voltage_type) {
 902                         case 0x00:
 903                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 904                                 printf("This DIMM is 5.0 Volt/TTL.\n");
 905                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 906                                        (unsigned int)dimm_num);
 907                                 spd_ddr_init_hang ();
 908                                 break;
 909                         case 0x01:
 910                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 911                                 printf("This DIMM is LVTTL.\n");
 912                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 913                                        (unsigned int)dimm_num);
 914                                 spd_ddr_init_hang ();
 915                                 break;
 916                         case 0x02:
 917                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 918                                 printf("This DIMM is 1.5 Volt.\n");
 919                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 920                                        (unsigned int)dimm_num);
 921                                 spd_ddr_init_hang ();
 922                                 break;
 923                         case 0x03:
 924                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 925                                 printf("This DIMM is 3.3 Volt/TTL.\n");
 926                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 927                                        (unsigned int)dimm_num);
 928                                 spd_ddr_init_hang ();
 929                                 break;
 930                         case 0x04:
 931                                 /* 2.5 Voltage only for DDR1 */
 932                                 break;
 933                         case 0x05:
 934                                 /* 1.8 Voltage only for DDR2 */
 935                                 break;
 936                         default:
 937                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 938                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 939                                        (unsigned int)dimm_num);
 940                                 spd_ddr_init_hang ();
 941                                 break;
 942                         }
 943                 }
 944         }
 945 }
 946
 947 /*-----------------------------------------------------------------------------+
 948  * program_copt1.
 949  *-----------------------------------------------------------------------------*/
 950 static void program_copt1(unsigned long *dimm_populated,
 951                           unsigned char *iic0_dimm_addr,
 952                           unsigned long num_dimm_banks)
 953 {
 954         unsigned long dimm_num;
 955         unsigned long mcopt1;
 956         unsigned long ecc_enabled;
 957         unsigned long ecc = 0;
 958         unsigned long data_width = 0;
 959         unsigned long dimm_32bit;
 960         unsigned long dimm_64bit;
 961         unsigned long registered = 0;
 962         unsigned long attribute = 0;
 963         unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
 964         unsigned long bankcount;
 965         unsigned long val;
 966
 967 #ifdef CONFIG_DDR_ECC
 968         ecc_enabled = true;
 969 #else
 970         ecc_enabled = false;
 971 #endif
 972         dimm_32bit = false;
 973         dimm_64bit = false;
 974         buf0 = false;
 975         buf1 = false;
 976
 977         /*------------------------------------------------------------------
 978          * Set memory controller options reg 1, SDRAM_MCOPT1.
 979          *-----------------------------------------------------------------*/
 980         mfsdram(SDRAM_MCOPT1, val);
 981         mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
 982                          SDRAM_MCOPT1_PMU_MASK  | SDRAM_MCOPT1_DMWD_MASK |
 983                          SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
 984                          SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
 985                          SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
 986                          SDRAM_MCOPT1_DREF_MASK);
 987
 988         mcopt1 |= SDRAM_MCOPT1_QDEP;
 989         mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
 990         mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
 991         mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
 992         mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
 993         mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
 994
 995         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 996                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 997                         /* test ecc support */
 998                         ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
 999                         if (ecc != 0x02) /* ecc not supported */
1000                                 ecc_enabled = false;
1001
1002                         /* test bank count */
1003                         bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
1004                         if (bankcount == 0x04) /* bank count = 4 */
1005                                 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
1006                         else /* bank count = 8 */
1007                                 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
1008
1009                         /* test for buffered/unbuffered, registered, differential clocks */
1010                         registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
1011                         attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
1012
1013                         /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
1014                         if (dimm_num == 0) {
1015                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1016                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1017                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1018                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1019                                 if (registered == 1) { /* DDR2 always buffered */
1020                                         /* TODO: what about above  comments ? */
1021                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
1022                                         buf0 = true;
1023                                 } else {
1024                                         /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
1025                                         if ((attribute & 0x02) == 0x00) {
1026                                                 /* buffered not supported */
1027                                                 buf0 = false;
1028                                         } else {
1029                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
1030                                                 buf0 = true;
1031                                         }
1032                                 }
1033                         }
1034                         else if (dimm_num == 1) {
1035                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1036                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1037                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1038                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1039                                 if (registered == 1) {
1040                                         /* DDR2 always buffered */
1041                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
1042                                         buf1 = true;
1043                                 } else {
1044                                         if ((attribute & 0x02) == 0x00) {
1045                                                 /* buffered not supported */
1046                                                 buf1 = false;
1047                                         } else {
1048                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
1049                                                 buf1 = true;
1050                                         }
1051                                 }
1052                         }
1053
1054                         /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
1055                         data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
1056                                 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
1057
1058                         switch (data_width) {
1059                         case 72:
1060                         case 64:
1061                                 dimm_64bit = true;
1062                                 break;
1063                         case 40:
1064                         case 32:
1065                                 dimm_32bit = true;
1066                                 break;
1067                         default:
1068                                 printf("WARNING: Detected a DIMM with a data width of %lu bits.\n",
1069                                        data_width);
1070                                 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
1071                                 break;
1072                         }
1073                 }
1074         }
1075
1076         /* verify matching properties */
1077         if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
1078                 if (buf0 != buf1) {
1079                         printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
1080                         spd_ddr_init_hang ();
1081                 }
1082         }
1083
1084         if ((dimm_64bit == true) && (dimm_32bit == true)) {
1085                 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
1086                 spd_ddr_init_hang ();
1087         } else if ((dimm_64bit == true) && (dimm_32bit == false)) {
1088                 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1089         } else if ((dimm_64bit == false) && (dimm_32bit == true)) {
1090                 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1091         } else {
1092                 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
1093                 spd_ddr_init_hang ();
1094         }
1095
1096         if (ecc_enabled == true)
1097                 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1098         else
1099                 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1100
1101         mtsdram(SDRAM_MCOPT1, mcopt1);
1102 }
1103
1104 /*-----------------------------------------------------------------------------+
1105  * program_codt.
1106  *-----------------------------------------------------------------------------*/
1107 static void program_codt(unsigned long *dimm_populated,
1108                          unsigned char *iic0_dimm_addr,
1109                          unsigned long num_dimm_banks)
1110 {
1111         unsigned long codt;
1112         unsigned long modt0 = 0;
1113         unsigned long modt1 = 0;
1114         unsigned long modt2 = 0;
1115         unsigned long modt3 = 0;
1116         unsigned char dimm_num;
1117         unsigned char dimm_rank;
1118         unsigned char total_rank = 0;
1119         unsigned char total_dimm = 0;
1120         unsigned char dimm_type = 0;
1121         unsigned char firstSlot = 0;
1122
1123         /*------------------------------------------------------------------
1124          * Set the SDRAM Controller On Die Termination Register
1125          *-----------------------------------------------------------------*/
1126         mfsdram(SDRAM_CODT, codt);
1127         codt &= ~(SDRAM_CODT_DQS_SINGLE_END | SDRAM_CODT_CKSE_SINGLE_END);
1128         codt |= SDRAM_CODT_IO_NMODE;
1129
1130         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1131                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1132                         dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1133                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1134                                 dimm_rank = (dimm_rank & 0x0F) + 1;
1135                                 dimm_type = SDRAM_DDR2;
1136                         } else {
1137                                 dimm_rank = dimm_rank & 0x0F;
1138                                 dimm_type = SDRAM_DDR1;
1139                         }
1140
1141                         total_rank += dimm_rank;
1142                         total_dimm++;
1143                         if ((dimm_num == 0) && (total_dimm == 1))
1144                                 firstSlot = true;
1145                         else
1146                                 firstSlot = false;
1147                 }
1148         }
1149         if (dimm_type == SDRAM_DDR2) {
1150                 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1151                 if ((total_dimm == 1) && (firstSlot == true)) {
1152                         if (total_rank == 1) {  /* PUUU */
1153                                 codt |= CALC_ODT_R(0);
1154                                 modt0 = CALC_ODT_W(0);
1155                                 modt1 = 0x00000000;
1156                                 modt2 = 0x00000000;
1157                                 modt3 = 0x00000000;
1158                         }
1159                         if (total_rank == 2) {  /* PPUU */
1160                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
1161                                 modt0 = CALC_ODT_W(0) | CALC_ODT_W(1);
1162                                 modt1 = 0x00000000;
1163                                 modt2 = 0x00000000;
1164                                 modt3 = 0x00000000;
1165                         }
1166                 } else if ((total_dimm == 1) && (firstSlot != true)) {
1167                         if (total_rank == 1) {  /* UUPU */
1168                                 codt |= CALC_ODT_R(2);
1169                                 modt0 = 0x00000000;
1170                                 modt1 = 0x00000000;
1171                                 modt2 = CALC_ODT_W(2);
1172                                 modt3 = 0x00000000;
1173                         }
1174                         if (total_rank == 2) {  /* UUPP */
1175                                 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1176                                 modt0 = 0x00000000;
1177                                 modt1 = 0x00000000;
1178                                 modt2 = CALC_ODT_W(2) | CALC_ODT_W(3);
1179                                 modt3 = 0x00000000;
1180                         }
1181                 }
1182                 if (total_dimm == 2) {
1183                         if (total_rank == 2) {  /* PUPU */
1184                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1185                                 modt0 = CALC_ODT_RW(2);
1186                                 modt1 = 0x00000000;
1187                                 modt2 = CALC_ODT_RW(0);
1188                                 modt3 = 0x00000000;
1189                         }
1190                         if (total_rank == 4) {  /* PPPP */
1191                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
1192                                         CALC_ODT_R(2) | CALC_ODT_R(3);
1193                                 modt0 = CALC_ODT_RW(2) | CALC_ODT_RW(3);
1194                                 modt1 = 0x00000000;
1195                                 modt2 = CALC_ODT_RW(0) | CALC_ODT_RW(1);
1196                                 modt3 = 0x00000000;
1197                         }
1198                 }
1199         } else {
1200                 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1201                 modt0 = 0x00000000;
1202                 modt1 = 0x00000000;
1203                 modt2 = 0x00000000;
1204                 modt3 = 0x00000000;
1205
1206                 if (total_dimm == 1) {
1207                         if (total_rank == 1)
1208                                 codt |= 0x00800000;
1209                         if (total_rank == 2)
1210                                 codt |= 0x02800000;
1211                 }
1212                 if (total_dimm == 2) {
1213                         if (total_rank == 2)
1214                                 codt |= 0x08800000;
1215                         if (total_rank == 4)
1216                                 codt |= 0x2a800000;
1217                 }
1218         }
1219
1220         debug("nb of dimm %d\n", total_dimm);
1221         debug("nb of rank %d\n", total_rank);
1222         if (total_dimm == 1)
1223                 debug("dimm in slot %d\n", firstSlot);
1224
1225         mtsdram(SDRAM_CODT, codt);
1226         mtsdram(SDRAM_MODT0, modt0);
1227         mtsdram(SDRAM_MODT1, modt1);
1228         mtsdram(SDRAM_MODT2, modt2);
1229         mtsdram(SDRAM_MODT3, modt3);
1230 }
1231
1232 /*-----------------------------------------------------------------------------+
1233  * program_initplr.
1234  *-----------------------------------------------------------------------------*/
1235 static void program_initplr(unsigned long *dimm_populated,
1236                             unsigned char *iic0_dimm_addr,
1237                             unsigned long num_dimm_banks,
1238                             ddr_cas_id_t selected_cas,
1239                             int write_recovery)
1240 {
1241         u32 cas = 0;
1242         u32 odt = 0;
1243         u32 ods = 0;
1244         u32 mr;
1245         u32 wr;
1246         u32 emr;
1247         u32 emr2;
1248         u32 emr3;
1249         int dimm_num;
1250         int total_dimm = 0;
1251
1252         /******************************************************
1253          ** Assumption: if more than one DIMM, all DIMMs are the same
1254          **             as already checked in check_memory_type
1255          ******************************************************/
1256
1257         if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1258                 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1259                 mtsdram(SDRAM_INITPLR1, 0x81900400);
1260                 mtsdram(SDRAM_INITPLR2, 0x81810000);
1261                 mtsdram(SDRAM_INITPLR3, 0xff800162);
1262                 mtsdram(SDRAM_INITPLR4, 0x81900400);
1263                 mtsdram(SDRAM_INITPLR5, 0x86080000);
1264                 mtsdram(SDRAM_INITPLR6, 0x86080000);
1265                 mtsdram(SDRAM_INITPLR7, 0x81000062);
1266         } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1267                 switch (selected_cas) {
1268                 case DDR_CAS_3:
1269                         cas = 3 << 4;
1270                         break;
1271                 case DDR_CAS_4:
1272                         cas = 4 << 4;
1273                         break;
1274                 case DDR_CAS_5:
1275                         cas = 5 << 4;
1276                         break;
1277                 default:
1278                         printf("ERROR: ucode error on selected_cas value %d", selected_cas);
1279                         spd_ddr_init_hang ();
1280                         break;
1281                 }
1282
1283 #if 0
1284                 /*
1285                  * ToDo - Still a problem with the write recovery:
1286                  * On the Corsair CM2X512-5400C4 module, setting write recovery
1287                  * in the INITPLR reg to the value calculated in program_mode()
1288                  * results in not correctly working DDR2 memory (crash after
1289                  * relocation).
1290                  *
1291                  * So for now, set the write recovery to 3. This seems to work
1292                  * on the Corair module too.
1293                  *
1294                  * 2007-03-01, sr
1295                  */
1296                 switch (write_recovery) {
1297                 case 3:
1298                         wr = WRITE_RECOV_3;
1299                         break;
1300                 case 4:
1301                         wr = WRITE_RECOV_4;
1302                         break;
1303                 case 5:
1304                         wr = WRITE_RECOV_5;
1305                         break;
1306                 case 6:
1307                         wr = WRITE_RECOV_6;
1308                         break;
1309                 default:
1310                         printf("ERROR: write recovery not support (%d)", write_recovery);
1311                         spd_ddr_init_hang ();
1312                         break;
1313                 }
1314 #else
1315                 wr = WRITE_RECOV_3; /* test-only, see description above */
1316 #endif
1317
1318                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1319                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1320                                 total_dimm++;
1321                 if (total_dimm == 1) {
1322                         odt = ODT_150_OHM;
1323                         ods = ODS_FULL;
1324                 } else if (total_dimm == 2) {
1325                         odt = ODT_75_OHM;
1326                         ods = ODS_REDUCED;
1327                 } else {
1328                         printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
1329                         spd_ddr_init_hang ();
1330                 }
1331
1332                 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1333                 emr = CMD_EMR | SELECT_EMR | odt | ods;
1334                 emr2 = CMD_EMR | SELECT_EMR2;
1335                 emr3 = CMD_EMR | SELECT_EMR3;
1336                 /* NOP - Wait 106 MemClk cycles */
1337                 mtsdram(SDRAM_INITPLR0, SDRAM_INITPLR_ENABLE | CMD_NOP |
1338                                         SDRAM_INITPLR_IMWT_ENCODE(106));
1339                 udelay(1000);
1340                 /* precharge 4 MemClk cycles */
1341                 mtsdram(SDRAM_INITPLR1, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1342                                         SDRAM_INITPLR_IMWT_ENCODE(4));
1343                 /* EMR2 - Wait tMRD (2 MemClk cycles) */
1344                 mtsdram(SDRAM_INITPLR2, SDRAM_INITPLR_ENABLE | emr2 |
1345                                         SDRAM_INITPLR_IMWT_ENCODE(2));
1346                 /* EMR3 - Wait tMRD (2 MemClk cycles) */
1347                 mtsdram(SDRAM_INITPLR3, SDRAM_INITPLR_ENABLE | emr3 |
1348                                         SDRAM_INITPLR_IMWT_ENCODE(2));
1349                 /* EMR DLL ENABLE - Wait tMRD (2 MemClk cycles) */
1350                 mtsdram(SDRAM_INITPLR4, SDRAM_INITPLR_ENABLE | emr |
1351                                         SDRAM_INITPLR_IMWT_ENCODE(2));
1352                 /* MR w/ DLL reset - 200 cycle wait for DLL reset */
1353                 mtsdram(SDRAM_INITPLR5, SDRAM_INITPLR_ENABLE | mr | DLL_RESET |
1354                                         SDRAM_INITPLR_IMWT_ENCODE(200));
1355                 udelay(1000);
1356                 /* precharge 4 MemClk cycles */
1357                 mtsdram(SDRAM_INITPLR6, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1358                                         SDRAM_INITPLR_IMWT_ENCODE(4));
1359                 /* Refresh 25 MemClk cycles */
1360                 mtsdram(SDRAM_INITPLR7, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1361                                         SDRAM_INITPLR_IMWT_ENCODE(25));
1362                 /* Refresh 25 MemClk cycles */
1363                 mtsdram(SDRAM_INITPLR8, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1364                                         SDRAM_INITPLR_IMWT_ENCODE(25));
1365                 /* Refresh 25 MemClk cycles */
1366                 mtsdram(SDRAM_INITPLR9, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1367                                         SDRAM_INITPLR_IMWT_ENCODE(25));
1368                 /* Refresh 25 MemClk cycles */
1369                 mtsdram(SDRAM_INITPLR10, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1370                                          SDRAM_INITPLR_IMWT_ENCODE(25));
1371                 /* MR w/o DLL reset - Wait tMRD (2 MemClk cycles) */
1372                 mtsdram(SDRAM_INITPLR11, SDRAM_INITPLR_ENABLE | mr |
1373                                          SDRAM_INITPLR_IMWT_ENCODE(2));
1374                 /* EMR OCD Default - Wait tMRD (2 MemClk cycles) */
1375                 mtsdram(SDRAM_INITPLR12, SDRAM_INITPLR_ENABLE | OCD_CALIB_DEF |
1376                                          SDRAM_INITPLR_IMWT_ENCODE(2) | emr);
1377                 /* EMR OCD Exit */
1378                 mtsdram(SDRAM_INITPLR13, SDRAM_INITPLR_ENABLE | emr |
1379                                          SDRAM_INITPLR_IMWT_ENCODE(2));
1380         } else {
1381                 printf("ERROR: ucode error as unknown DDR type in program_initplr");
1382                 spd_ddr_init_hang ();
1383         }
1384 }
1385
1386 /*------------------------------------------------------------------
1387  * This routine programs the SDRAM_MMODE register.
1388  * the selected_cas is an output parameter, that will be passed
1389  * by caller to call the above program_initplr( )
1390  *-----------------------------------------------------------------*/
1391 static void program_mode(unsigned long *dimm_populated,
1392                          unsigned char *iic0_dimm_addr,
1393                          unsigned long num_dimm_banks,
1394                          ddr_cas_id_t *selected_cas,
1395                          int *write_recovery)
1396 {
1397         unsigned long dimm_num;
1398         unsigned long sdram_ddr1;
1399         unsigned long t_wr_ns;
1400         unsigned long t_wr_clk;
1401         unsigned long cas_bit;
1402         unsigned long cas_index;
1403         unsigned long sdram_freq;
1404         unsigned long ddr_check;
1405         unsigned long mmode;
1406         unsigned long tcyc_reg;
1407         unsigned long cycle_2_0_clk;
1408         unsigned long cycle_2_5_clk;
1409         unsigned long cycle_3_0_clk;
1410         unsigned long cycle_4_0_clk;
1411         unsigned long cycle_5_0_clk;
1412         unsigned long max_2_0_tcyc_ns_x_100;
1413         unsigned long max_2_5_tcyc_ns_x_100;
1414         unsigned long max_3_0_tcyc_ns_x_100;
1415         unsigned long max_4_0_tcyc_ns_x_100;
1416         unsigned long max_5_0_tcyc_ns_x_100;
1417         unsigned long cycle_time_ns_x_100[3];
1418         PPC4xx_SYS_INFO board_cfg;
1419         unsigned char cas_2_0_available;
1420         unsigned char cas_2_5_available;
1421         unsigned char cas_3_0_available;
1422         unsigned char cas_4_0_available;
1423         unsigned char cas_5_0_available;
1424         unsigned long sdr_ddrpll;
1425
1426         /*------------------------------------------------------------------
1427          * Get the board configuration info.
1428          *-----------------------------------------------------------------*/
1429         get_sys_info(&board_cfg);
1430
1431         mfsdr(SDR0_DDR0, sdr_ddrpll);
1432         sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
1433         debug("sdram_freq=%lu\n", sdram_freq);
1434
1435         /*------------------------------------------------------------------
1436          * Handle the timing.  We need to find the worst case timing of all
1437          * the dimm modules installed.
1438          *-----------------------------------------------------------------*/
1439         t_wr_ns = 0;
1440         cas_2_0_available = true;
1441         cas_2_5_available = true;
1442         cas_3_0_available = true;
1443         cas_4_0_available = true;
1444         cas_5_0_available = true;
1445         max_2_0_tcyc_ns_x_100 = 10;
1446         max_2_5_tcyc_ns_x_100 = 10;
1447         max_3_0_tcyc_ns_x_100 = 10;
1448         max_4_0_tcyc_ns_x_100 = 10;
1449         max_5_0_tcyc_ns_x_100 = 10;
1450         sdram_ddr1 = true;
1451
1452         /* loop through all the DIMM slots on the board */
1453         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1454                 /* If a dimm is installed in a particular slot ... */
1455                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1456                         if (dimm_populated[dimm_num] == SDRAM_DDR1)
1457                                 sdram_ddr1 = true;
1458                         else
1459                                 sdram_ddr1 = false;
1460
1461                         cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1462                         debug("cas_bit[SPD byte 18]=%02lx\n", cas_bit);
1463
1464                         /* For a particular DIMM, grab the three CAS values it supports */
1465                         for (cas_index = 0; cas_index < 3; cas_index++) {
1466                                 switch (cas_index) {
1467                                 case 0:
1468                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1469                                         break;
1470                                 case 1:
1471                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1472                                         break;
1473                                 default:
1474                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1475                                         break;
1476                                 }
1477
1478                                 if ((tcyc_reg & 0x0F) >= 10) {
1479                                         if ((tcyc_reg & 0x0F) == 0x0D) {
1480                                                 /* Convert from hex to decimal */
1481                                                 cycle_time_ns_x_100[cas_index] =
1482                                                         (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
1483                                         } else {
1484                                                 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1485                                                        "in slot %d\n", (unsigned int)dimm_num);
1486                                                 spd_ddr_init_hang ();
1487                                         }
1488                                 } else {
1489                                         /* Convert from hex to decimal */
1490                                         cycle_time_ns_x_100[cas_index] =
1491                                                 (((tcyc_reg & 0xF0) >> 4) * 100) +
1492                                                 ((tcyc_reg & 0x0F)*10);
1493                                 }
1494                                 debug("cas_index=%lu: cycle_time_ns_x_100=%lu\n", cas_index,
1495                                       cycle_time_ns_x_100[cas_index]);
1496                         }
1497
1498                         /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1499                         /* supported for a particular DIMM. */
1500                         cas_index = 0;
1501
1502                         if (sdram_ddr1) {
1503                                 /*
1504                                  * DDR devices use the following bitmask for CAS latency:
1505                                  *  Bit   7    6    5    4    3    2    1    0
1506                                  *       TBD  4.0  3.5  3.0  2.5  2.0  1.5  1.0
1507                                  */
1508                                 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
1509                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1510                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1511                                                                     cycle_time_ns_x_100[cas_index]);
1512                                         cas_index++;
1513                                 } else {
1514                                         if (cas_index != 0)
1515                                                 cas_index++;
1516                                         cas_4_0_available = false;
1517                                 }
1518
1519                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1520                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1521                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1522                                                                     cycle_time_ns_x_100[cas_index]);
1523                                         cas_index++;
1524                                 } else {
1525                                         if (cas_index != 0)
1526                                                 cas_index++;
1527                                         cas_3_0_available = false;
1528                                 }
1529
1530                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1531                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1532                                         max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
1533                                                                     cycle_time_ns_x_100[cas_index]);
1534                                         cas_index++;
1535                                 } else {
1536                                         if (cas_index != 0)
1537                                                 cas_index++;
1538                                         cas_2_5_available = false;
1539                                 }
1540
1541                                 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
1542                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1543                                         max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
1544                                                                     cycle_time_ns_x_100[cas_index]);
1545                                         cas_index++;
1546                                 } else {
1547                                         if (cas_index != 0)
1548                                                 cas_index++;
1549                                         cas_2_0_available = false;
1550                                 }
1551                         } else {
1552                                 /*
1553                                  * DDR2 devices use the following bitmask for CAS latency:
1554                                  *  Bit   7    6    5    4    3    2    1    0
1555                                  *       TBD  6.0  5.0  4.0  3.0  2.0  TBD  TBD
1556                                  */
1557                                 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
1558                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1559                                         max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
1560                                                                     cycle_time_ns_x_100[cas_index]);
1561                                         cas_index++;
1562                                 } else {
1563                                         if (cas_index != 0)
1564                                                 cas_index++;
1565                                         cas_5_0_available = false;
1566                                 }
1567
1568                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1569                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1570                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1571                                                                     cycle_time_ns_x_100[cas_index]);
1572                                         cas_index++;
1573                                 } else {
1574                                         if (cas_index != 0)
1575                                                 cas_index++;
1576                                         cas_4_0_available = false;
1577                                 }
1578
1579                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1580                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1581                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1582                                                                     cycle_time_ns_x_100[cas_index]);
1583                                         cas_index++;
1584                                 } else {
1585                                         if (cas_index != 0)
1586                                                 cas_index++;
1587                                         cas_3_0_available = false;
1588                                 }
1589                         }
1590                 }
1591         }
1592
1593         /*------------------------------------------------------------------
1594          * Set the SDRAM mode, SDRAM_MMODE
1595          *-----------------------------------------------------------------*/
1596         mfsdram(SDRAM_MMODE, mmode);
1597         mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1598
1599         /* add 10 here because of rounding problems */
1600         cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1601         cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1602         cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1603         cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1604         cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
1605         debug("cycle_3_0_clk=%lu\n", cycle_3_0_clk);
1606         debug("cycle_4_0_clk=%lu\n", cycle_4_0_clk);
1607         debug("cycle_5_0_clk=%lu\n", cycle_5_0_clk);
1608
1609         if (sdram_ddr1 == true) { /* DDR1 */
1610                 if ((cas_2_0_available == true) &&
1611                         (sdram_freq <= cycle_2_0_clk)) {
1612                         mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1613                         *selected_cas = DDR_CAS_2;
1614                 } else if ((cas_2_5_available == true) &&
1615                         (sdram_freq <= cycle_2_5_clk)) {
1616                         mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1617                         *selected_cas = DDR_CAS_2_5;
1618                 } else if ((cas_3_0_available == true) &&
1619                         (sdram_freq <= cycle_3_0_clk)) {
1620                         mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1621                         *selected_cas = DDR_CAS_3;
1622                 } else {
1623                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1624                         printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1625                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1626                         spd_ddr_init_hang ();
1627                 }
1628         } else { /* DDR2 */
1629                 debug("cas_3_0_available=%d\n", cas_3_0_available);
1630                 debug("cas_4_0_available=%d\n", cas_4_0_available);
1631                 debug("cas_5_0_available=%d\n", cas_5_0_available);
1632                 if ((cas_3_0_available == true) &&
1633                         (sdram_freq <= cycle_3_0_clk)) {
1634                         mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1635                         *selected_cas = DDR_CAS_3;
1636                 } else if ((cas_4_0_available == true) &&
1637                         (sdram_freq <= cycle_4_0_clk)) {
1638                         mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1639                         *selected_cas = DDR_CAS_4;
1640                 } else if ((cas_5_0_available == true) &&
1641                         (sdram_freq <= cycle_5_0_clk)) {
1642                         mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1643                         *selected_cas = DDR_CAS_5;
1644                 } else {
1645                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1646                         printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
1647                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1648                         printf("cas3=%d cas4=%d cas5=%d\n",
1649                                cas_3_0_available, cas_4_0_available, cas_5_0_available);
1650                         printf("sdram_freq=%lu cycle3=%lu cycle4=%lu cycle5=%lu\n\n",
1651                                sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
1652                         spd_ddr_init_hang ();
1653                 }
1654         }
1655
1656         if (sdram_ddr1 == true)
1657                 mmode |= SDRAM_MMODE_WR_DDR1;
1658         else {
1659
1660                 /* loop through all the DIMM slots on the board */
1661                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1662                         /* If a dimm is installed in a particular slot ... */
1663                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1664                                 t_wr_ns = max(t_wr_ns,
1665                                               spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1666                 }
1667
1668                 /*
1669                  * convert from nanoseconds to ddr clocks
1670                  * round up if necessary
1671                  */
1672                 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1673                 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1674                 if (sdram_freq != ddr_check)
1675                         t_wr_clk++;
1676
1677                 switch (t_wr_clk) {
1678                 case 0:
1679                 case 1:
1680                 case 2:
1681                 case 3:
1682                         mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1683                         break;
1684                 case 4:
1685                         mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1686                         break;
1687                 case 5:
1688                         mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1689                         break;
1690                 default:
1691                         mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1692                         break;
1693                 }
1694                 *write_recovery = t_wr_clk;
1695         }
1696
1697         debug("CAS latency = %d\n", *selected_cas);
1698         debug("Write recovery = %d\n", *write_recovery);
1699
1700         mtsdram(SDRAM_MMODE, mmode);
1701 }
1702
1703 /*-----------------------------------------------------------------------------+
1704  * program_rtr.
1705  *-----------------------------------------------------------------------------*/
1706 static void program_rtr(unsigned long *dimm_populated,
1707                         unsigned char *iic0_dimm_addr,
1708                         unsigned long num_dimm_banks)
1709 {
1710         PPC4xx_SYS_INFO board_cfg;
1711         unsigned long max_refresh_rate;
1712         unsigned long dimm_num;
1713         unsigned long refresh_rate_type;
1714         unsigned long refresh_rate;
1715         unsigned long rint;
1716         unsigned long sdram_freq;
1717         unsigned long sdr_ddrpll;
1718         unsigned long val;
1719
1720         /*------------------------------------------------------------------
1721          * Get the board configuration info.
1722          *-----------------------------------------------------------------*/
1723         get_sys_info(&board_cfg);
1724
1725         /*------------------------------------------------------------------
1726          * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1727          *-----------------------------------------------------------------*/
1728         mfsdr(SDR0_DDR0, sdr_ddrpll);
1729         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1730
1731         max_refresh_rate = 0;
1732         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1733                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1734
1735                         refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1736                         refresh_rate_type &= 0x7F;
1737                         switch (refresh_rate_type) {
1738                         case 0:
1739                                 refresh_rate =  15625;
1740                                 break;
1741                         case 1:
1742                                 refresh_rate =   3906;
1743                                 break;
1744                         case 2:
1745                                 refresh_rate =   7812;
1746                                 break;
1747                         case 3:
1748                                 refresh_rate =  31250;
1749                                 break;
1750                         case 4:
1751                                 refresh_rate =  62500;
1752                                 break;
1753                         case 5:
1754                                 refresh_rate = 125000;
1755                                 break;
1756                         default:
1757                                 refresh_rate = 0;
1758                                 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1759                                        (unsigned int)dimm_num);
1760                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1761                                 spd_ddr_init_hang ();
1762                                 break;
1763                         }
1764
1765                         max_refresh_rate = max(max_refresh_rate, refresh_rate);
1766                 }
1767         }
1768
1769         rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1770         mfsdram(SDRAM_RTR, val);
1771         mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1772                 (SDRAM_RTR_RINT_ENCODE(rint)));
1773 }
1774
1775 /*------------------------------------------------------------------
1776  * This routine programs the SDRAM_TRx registers.
1777  *-----------------------------------------------------------------*/
1778 static void program_tr(unsigned long *dimm_populated,
1779                        unsigned char *iic0_dimm_addr,
1780                        unsigned long num_dimm_banks)
1781 {
1782         unsigned long dimm_num;
1783         unsigned long sdram_ddr1;
1784         unsigned long t_rp_ns;
1785         unsigned long t_rcd_ns;
1786         unsigned long t_rrd_ns;
1787         unsigned long t_ras_ns;
1788         unsigned long t_rc_ns;
1789         unsigned long t_rfc_ns;
1790         unsigned long t_wpc_ns;
1791         unsigned long t_wtr_ns;
1792         unsigned long t_rpc_ns;
1793         unsigned long t_rp_clk;
1794         unsigned long t_rcd_clk;
1795         unsigned long t_rrd_clk;
1796         unsigned long t_ras_clk;
1797         unsigned long t_rc_clk;
1798         unsigned long t_rfc_clk;
1799         unsigned long t_wpc_clk;
1800         unsigned long t_wtr_clk;
1801         unsigned long t_rpc_clk;
1802         unsigned long sdtr1, sdtr2, sdtr3;
1803         unsigned long ddr_check;
1804         unsigned long sdram_freq;
1805         unsigned long sdr_ddrpll;
1806
1807         PPC4xx_SYS_INFO board_cfg;
1808
1809         /*------------------------------------------------------------------
1810          * Get the board configuration info.
1811          *-----------------------------------------------------------------*/
1812         get_sys_info(&board_cfg);
1813
1814         mfsdr(SDR0_DDR0, sdr_ddrpll);
1815         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1816
1817         /*------------------------------------------------------------------
1818          * Handle the timing.  We need to find the worst case timing of all
1819          * the dimm modules installed.
1820          *-----------------------------------------------------------------*/
1821         t_rp_ns = 0;
1822         t_rrd_ns = 0;
1823         t_rcd_ns = 0;
1824         t_ras_ns = 0;
1825         t_rc_ns = 0;
1826         t_rfc_ns = 0;
1827         t_wpc_ns = 0;
1828         t_wtr_ns = 0;
1829         t_rpc_ns = 0;
1830         sdram_ddr1 = true;
1831
1832         /* loop through all the DIMM slots on the board */
1833         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1834                 /* If a dimm is installed in a particular slot ... */
1835                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1836                         if (dimm_populated[dimm_num] == SDRAM_DDR2)
1837                                 sdram_ddr1 = true;
1838                         else
1839                                 sdram_ddr1 = false;
1840
1841                         t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1842                         t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1843                         t_rp_ns  = max(t_rp_ns,  spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1844                         t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1845                         t_rc_ns  = max(t_rc_ns,  spd_read(iic0_dimm_addr[dimm_num], 41));
1846                         t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1847                 }
1848         }
1849
1850         /*------------------------------------------------------------------
1851          * Set the SDRAM Timing Reg 1, SDRAM_TR1
1852          *-----------------------------------------------------------------*/
1853         mfsdram(SDRAM_SDTR1, sdtr1);
1854         sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1855                    SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1856
1857         /* default values */
1858         sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1859         sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1860
1861         /* normal operations */
1862         sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1863         sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1864
1865         mtsdram(SDRAM_SDTR1, sdtr1);
1866
1867         /*------------------------------------------------------------------
1868          * Set the SDRAM Timing Reg 2, SDRAM_TR2
1869          *-----------------------------------------------------------------*/
1870         mfsdram(SDRAM_SDTR2, sdtr2);
1871         sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK  | SDRAM_SDTR2_WTR_MASK |
1872                    SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1873                    SDRAM_SDTR2_RPC_MASK  | SDRAM_SDTR2_RP_MASK  |
1874                    SDRAM_SDTR2_RRD_MASK);
1875
1876         /*
1877          * convert t_rcd from nanoseconds to ddr clocks
1878          * round up if necessary
1879          */
1880         t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1881         ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1882         if (sdram_freq != ddr_check)
1883                 t_rcd_clk++;
1884
1885         switch (t_rcd_clk) {
1886         case 0:
1887         case 1:
1888                 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1889                 break;
1890         case 2:
1891                 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1892                 break;
1893         case 3:
1894                 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1895                 break;
1896         case 4:
1897                 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1898                 break;
1899         default:
1900                 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1901                 break;
1902         }
1903
1904         if (sdram_ddr1 == true) { /* DDR1 */
1905                 if (sdram_freq < 200000000) {
1906                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1907                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1908                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1909                 } else {
1910                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1911                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1912                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1913                 }
1914         } else { /* DDR2 */
1915                 /* loop through all the DIMM slots on the board */
1916                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1917                         /* If a dimm is installed in a particular slot ... */
1918                         if (dimm_populated[dimm_num] != SDRAM_NONE) {
1919                                 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1920                                 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1921                                 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1922                         }
1923                 }
1924
1925                 /*
1926                  * convert from nanoseconds to ddr clocks
1927                  * round up if necessary
1928                  */
1929                 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1930                 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1931                 if (sdram_freq != ddr_check)
1932                         t_wpc_clk++;
1933
1934                 switch (t_wpc_clk) {
1935                 case 0:
1936                 case 1:
1937                 case 2:
1938                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1939                         break;
1940                 case 3:
1941                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1942                         break;
1943                 case 4:
1944                         sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1945                         break;
1946                 case 5:
1947                         sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1948                         break;
1949                 default:
1950                         sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1951                         break;
1952                 }
1953
1954                 /*
1955                  * convert from nanoseconds to ddr clocks
1956                  * round up if necessary
1957                  */
1958                 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1959                 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1960                 if (sdram_freq != ddr_check)
1961                         t_wtr_clk++;
1962
1963                 switch (t_wtr_clk) {
1964                 case 0:
1965                 case 1:
1966                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1967                         break;
1968                 case 2:
1969                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1970                         break;
1971                 case 3:
1972                         sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
1973                         break;
1974                 default:
1975                         sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
1976                         break;
1977                 }
1978
1979                 /*
1980                  * convert from nanoseconds to ddr clocks
1981                  * round up if necessary
1982                  */
1983                 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
1984                 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
1985                 if (sdram_freq != ddr_check)
1986                         t_rpc_clk++;
1987
1988                 switch (t_rpc_clk) {
1989                 case 0:
1990                 case 1:
1991                 case 2:
1992                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1993                         break;
1994                 case 3:
1995                         sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
1996                         break;
1997                 default:
1998                         sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
1999                         break;
2000                 }
2001         }
2002
2003         /* default value */
2004         sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
2005
2006         /*
2007          * convert t_rrd from nanoseconds to ddr clocks
2008          * round up if necessary
2009          */
2010         t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
2011         ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
2012         if (sdram_freq != ddr_check)
2013                 t_rrd_clk++;
2014
2015         if (t_rrd_clk == 3)
2016                 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
2017         else
2018                 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
2019
2020         /*
2021          * convert t_rp from nanoseconds to ddr clocks
2022          * round up if necessary
2023          */
2024         t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
2025         ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
2026         if (sdram_freq != ddr_check)
2027                 t_rp_clk++;
2028
2029         switch (t_rp_clk) {
2030         case 0:
2031         case 1:
2032         case 2:
2033         case 3:
2034                 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
2035                 break;
2036         case 4:
2037                 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
2038                 break;
2039         case 5:
2040                 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
2041                 break;
2042         case 6:
2043                 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
2044                 break;
2045         default:
2046                 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
2047                 break;
2048         }
2049
2050         mtsdram(SDRAM_SDTR2, sdtr2);
2051
2052         /*------------------------------------------------------------------
2053          * Set the SDRAM Timing Reg 3, SDRAM_TR3
2054          *-----------------------------------------------------------------*/
2055         mfsdram(SDRAM_SDTR3, sdtr3);
2056         sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK  | SDRAM_SDTR3_RC_MASK |
2057                    SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
2058
2059         /*
2060          * convert t_ras from nanoseconds to ddr clocks
2061          * round up if necessary
2062          */
2063         t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
2064         ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
2065         if (sdram_freq != ddr_check)
2066                 t_ras_clk++;
2067
2068         sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
2069
2070         /*
2071          * convert t_rc from nanoseconds to ddr clocks
2072          * round up if necessary
2073          */
2074         t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
2075         ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
2076         if (sdram_freq != ddr_check)
2077                 t_rc_clk++;
2078
2079         sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
2080
2081         /* default xcs value */
2082         sdtr3 |= SDRAM_SDTR3_XCS;
2083
2084         /*
2085          * convert t_rfc from nanoseconds to ddr clocks
2086          * round up if necessary
2087          */
2088         t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
2089         ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
2090         if (sdram_freq != ddr_check)
2091                 t_rfc_clk++;
2092
2093         sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
2094
2095         mtsdram(SDRAM_SDTR3, sdtr3);
2096 }
2097
2098 /*-----------------------------------------------------------------------------+
2099  * program_bxcf.
2100  *-----------------------------------------------------------------------------*/
2101 static void program_bxcf(unsigned long *dimm_populated,
2102                          unsigned char *iic0_dimm_addr,
2103                          unsigned long num_dimm_banks)
2104 {
2105         unsigned long dimm_num;
2106         unsigned long num_col_addr;
2107         unsigned long num_ranks;
2108         unsigned long num_banks;
2109         unsigned long mode;
2110         unsigned long ind_rank;
2111         unsigned long ind;
2112         unsigned long ind_bank;
2113         unsigned long bank_0_populated;
2114
2115         /*------------------------------------------------------------------
2116          * Set the BxCF regs.  First, wipe out the bank config registers.
2117          *-----------------------------------------------------------------*/
2118         mtsdram(SDRAM_MB0CF, 0x00000000);
2119         mtsdram(SDRAM_MB1CF, 0x00000000);
2120         mtsdram(SDRAM_MB2CF, 0x00000000);
2121         mtsdram(SDRAM_MB3CF, 0x00000000);
2122
2123         mode = SDRAM_BXCF_M_BE_ENABLE;
2124
2125         bank_0_populated = 0;
2126
2127         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2128                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2129                         num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
2130                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2131                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2132                                 num_ranks = (num_ranks & 0x0F) +1;
2133                         else
2134                                 num_ranks = num_ranks & 0x0F;
2135
2136                         num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
2137
2138                         for (ind_bank = 0; ind_bank < 2; ind_bank++) {
2139                                 if (num_banks == 4)
2140                                         ind = 0;
2141                                 else
2142                                         ind = 5 << 8;
2143                                 switch (num_col_addr) {
2144                                 case 0x08:
2145                                         mode |= (SDRAM_BXCF_M_AM_0 + ind);
2146                                         break;
2147                                 case 0x09:
2148                                         mode |= (SDRAM_BXCF_M_AM_1 + ind);
2149                                         break;
2150                                 case 0x0A:
2151                                         mode |= (SDRAM_BXCF_M_AM_2 + ind);
2152                                         break;
2153                                 case 0x0B:
2154                                         mode |= (SDRAM_BXCF_M_AM_3 + ind);
2155                                         break;
2156                                 case 0x0C:
2157                                         mode |= (SDRAM_BXCF_M_AM_4 + ind);
2158                                         break;
2159                                 default:
2160                                         printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2161                                                (unsigned int)dimm_num);
2162                                         printf("ERROR: Unsupported value for number of "
2163                                                "column addresses: %d.\n", (unsigned int)num_col_addr);
2164                                         printf("Replace the DIMM module with a supported DIMM.\n\n");
2165                                         spd_ddr_init_hang ();
2166                                 }
2167                         }
2168
2169                         if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2170                                 bank_0_populated = 1;
2171
2172                         for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
2173                                 mtsdram(SDRAM_MB0CF +
2174                                         ((dimm_num + bank_0_populated + ind_rank) << 2),
2175                                         mode);
2176                         }
2177                 }
2178         }
2179 }
2180
2181 /*------------------------------------------------------------------
2182  * program memory queue.
2183  *-----------------------------------------------------------------*/
2184 static void program_memory_queue(unsigned long *dimm_populated,
2185                                  unsigned char *iic0_dimm_addr,
2186                                  unsigned long num_dimm_banks)
2187 {
2188         unsigned long dimm_num;
2189         phys_size_t rank_base_addr;
2190         unsigned long rank_reg;
2191         phys_size_t rank_size_bytes;
2192         unsigned long rank_size_id;
2193         unsigned long num_ranks;
2194         unsigned long baseadd_size;
2195         unsigned long i;
2196         unsigned long bank_0_populated = 0;
2197         phys_size_t total_size = 0;
2198
2199         /*------------------------------------------------------------------
2200          * Reset the rank_base_address.
2201          *-----------------------------------------------------------------*/
2202         rank_reg   = SDRAM_R0BAS;
2203
2204         rank_base_addr = 0x00000000;
2205
2206         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2207                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2208                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2209                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2210                                 num_ranks = (num_ranks & 0x0F) + 1;
2211                         else
2212                                 num_ranks = num_ranks & 0x0F;
2213
2214                         rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2215
2216                         /*------------------------------------------------------------------
2217                          * Set the sizes
2218                          *-----------------------------------------------------------------*/
2219                         baseadd_size = 0;
2220                         switch (rank_size_id) {
2221                         case 0x01:
2222                                 baseadd_size |= SDRAM_RXBAS_SDSZ_1024;
2223                                 total_size = 1024;
2224                                 break;
2225                         case 0x02:
2226                                 baseadd_size |= SDRAM_RXBAS_SDSZ_2048;
2227                                 total_size = 2048;
2228                                 break;
2229                         case 0x04:
2230                                 baseadd_size |= SDRAM_RXBAS_SDSZ_4096;
2231                                 total_size = 4096;
2232                                 break;
2233                         case 0x08:
2234                                 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
2235                                 total_size = 32;
2236                                 break;
2237                         case 0x10:
2238                                 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
2239                                 total_size = 64;
2240                                 break;
2241                         case 0x20:
2242                                 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
2243                                 total_size = 128;
2244                                 break;
2245                         case 0x40:
2246                                 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
2247                                 total_size = 256;
2248                                 break;
2249                         case 0x80:
2250                                 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
2251                                 total_size = 512;
2252                                 break;
2253                         default:
2254                                 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2255                                        (unsigned int)dimm_num);
2256                                 printf("ERROR: Unsupported value for the banksize: %d.\n",
2257                                        (unsigned int)rank_size_id);
2258                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
2259                                 spd_ddr_init_hang ();
2260                         }
2261                         rank_size_bytes = total_size << 20;
2262
2263                         if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2264                                 bank_0_populated = 1;
2265
2266                         for (i = 0; i < num_ranks; i++) {
2267                                 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
2268                                           (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2269                                            baseadd_size));
2270                                 rank_base_addr += rank_size_bytes;
2271                         }
2272                 }
2273         }
2274
2275 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
2276     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
2277     defined(CONFIG_460SX)
2278         /*
2279          * Enable high bandwidth access
2280          * This is currently not used, but with this setup
2281          * it is possible to use it later on in e.g. the Linux
2282          * EMAC driver for performance gain.
2283          */
2284         mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
2285         mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
2286
2287         /*
2288          * Set optimal value for Memory Queue HB/LL Configuration registers
2289          */
2290         mtdcr(SDRAM_CONF1HB, (mfdcr(SDRAM_CONF1HB) & ~SDRAM_CONF1HB_MASK) |
2291               SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE |
2292               SDRAM_CONF1HB_RPLM | SDRAM_CONF1HB_WRCL);
2293         mtdcr(SDRAM_CONF1LL, (mfdcr(SDRAM_CONF1LL) & ~SDRAM_CONF1LL_MASK) |
2294               SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE |
2295               SDRAM_CONF1LL_RPLM);
2296         mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
2297 #endif
2298 }
2299
2300 #ifdef CONFIG_DDR_ECC
2301 /*-----------------------------------------------------------------------------+
2302  * program_ecc.
2303  *-----------------------------------------------------------------------------*/
2304 static void program_ecc(unsigned long *dimm_populated,
2305                         unsigned char *iic0_dimm_addr,
2306                         unsigned long num_dimm_banks,
2307                         unsigned long tlb_word2_i_value)
2308 {
2309         unsigned long dimm_num;
2310         unsigned long ecc;
2311
2312         ecc = 0;
2313         /* loop through all the DIMM slots on the board */
2314         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2315                 /* If a dimm is installed in a particular slot ... */
2316                 if (dimm_populated[dimm_num] != SDRAM_NONE)
2317                         ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2318         }
2319         if (ecc == 0)
2320                 return;
2321
2322         do_program_ecc(tlb_word2_i_value);
2323 }
2324 #endif
2325
2326 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
2327 /*-----------------------------------------------------------------------------+
2328  * program_DQS_calibration.
2329  *-----------------------------------------------------------------------------*/
2330 static void program_DQS_calibration(unsigned long *dimm_populated,
2331                                     unsigned char *iic0_dimm_addr,
2332                                     unsigned long num_dimm_banks)
2333 {
2334         unsigned long val;
2335
2336 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2337         mtsdram(SDRAM_RQDC, 0x80000037);
2338         mtsdram(SDRAM_RDCC, 0x40000000);
2339         mtsdram(SDRAM_RFDC, 0x000001DF);
2340
2341         test();
2342 #else
2343         /*------------------------------------------------------------------
2344          * Program RDCC register
2345          * Read sample cycle auto-update enable
2346          *-----------------------------------------------------------------*/
2347
2348         mfsdram(SDRAM_RDCC, val);
2349         mtsdram(SDRAM_RDCC,
2350                 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
2351                 | SDRAM_RDCC_RSAE_ENABLE);
2352
2353         /*------------------------------------------------------------------
2354          * Program RQDC register
2355          * Internal DQS delay mechanism enable
2356          *-----------------------------------------------------------------*/
2357         mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2358
2359         /*------------------------------------------------------------------
2360          * Program RFDC register
2361          * Set Feedback Fractional Oversample
2362          * Auto-detect read sample cycle enable
2363          * Set RFOS to 1/4 of memclk cycle (0x3f)
2364          *-----------------------------------------------------------------*/
2365         mfsdram(SDRAM_RFDC, val);
2366         mtsdram(SDRAM_RFDC,
2367                 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2368                          SDRAM_RFDC_RFFD_MASK))
2369                 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0x3f) |
2370                    SDRAM_RFDC_RFFD_ENCODE(0)));
2371
2372         DQS_calibration_process();
2373 #endif
2374 }
2375
2376 static int short_mem_test(void)
2377 {
2378         u32 *membase;
2379         u32 bxcr_num;
2380         u32 bxcf;
2381         int i;
2382         int j;
2383         phys_size_t base_addr;
2384         u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2385                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2386                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2387                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2388                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2389                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2390                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2391                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2392                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2393                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2394                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2395                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2396                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2397                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2398                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2399                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2400                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2401         int l;
2402
2403         for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2404                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2405
2406                 /* Banks enabled */
2407                 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2408                         /* Bank is enabled */
2409
2410                         /*
2411                          * Only run test on accessable memory (below 2GB)
2412                          */
2413                         base_addr = SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num));
2414                         if (base_addr >= CONFIG_MAX_MEM_MAPPED)
2415                                 continue;
2416
2417                         /*------------------------------------------------------------------
2418                          * Run the short memory test.
2419                          *-----------------------------------------------------------------*/
2420                         membase = (u32 *)(u32)base_addr;
2421
2422                         for (i = 0; i < NUMMEMTESTS; i++) {
2423                                 for (j = 0; j < NUMMEMWORDS; j++) {
2424                                         membase[j] = test[i][j];
2425                                         ppcDcbf((u32)&(membase[j]));
2426                                 }
2427                                 sync();
2428                                 for (l=0; l<NUMLOOPS; l++) {
2429                                         for (j = 0; j < NUMMEMWORDS; j++) {
2430                                                 if (membase[j] != test[i][j]) {
2431                                                         ppcDcbf((u32)&(membase[j]));
2432                                                         return 0;
2433                                                 }
2434                                                 ppcDcbf((u32)&(membase[j]));
2435                                         }
2436                                         sync();
2437                                 }
2438                         }
2439                 }       /* if bank enabled */
2440         }               /* for bxcf_num */
2441
2442         return 1;
2443 }
2444
2445 #ifndef HARD_CODED_DQS
2446 /*-----------------------------------------------------------------------------+
2447  * DQS_calibration_process.
2448  *-----------------------------------------------------------------------------*/
2449 static void DQS_calibration_process(void)
2450 {
2451         unsigned long rfdc_reg;
2452         unsigned long rffd;
2453         unsigned long val;
2454         long rffd_average;
2455         long max_start;
2456         unsigned long dlycal;
2457         unsigned long dly_val;
2458         unsigned long max_pass_length;
2459         unsigned long current_pass_length;
2460         unsigned long current_fail_length;
2461         unsigned long current_start;
2462         long max_end;
2463         unsigned char fail_found;
2464         unsigned char pass_found;
2465 #if !defined(CONFIG_DDR_RQDC_FIXED)
2466         int window_found;
2467         u32 rqdc_reg;
2468         u32 rqfd;
2469         u32 rqfd_start;
2470         u32 rqfd_average;
2471         int loopi = 0;
2472         char str[] = "Auto calibration -";
2473         char slash[] = "\\|/-\\|/-";
2474
2475         /*------------------------------------------------------------------
2476          * Test to determine the best read clock delay tuning bits.
2477          *
2478          * Before the DDR controller can be used, the read clock delay needs to be
2479          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2480          * This value cannot be hardcoded into the program because it changes
2481          * depending on the board's setup and environment.
2482          * To do this, all delay values are tested to see if they
2483          * work or not.  By doing this, you get groups of fails with groups of
2484          * passing values.  The idea is to find the start and end of a passing
2485          * window and take the center of it to use as the read clock delay.
2486          *
2487          * A failure has to be seen first so that when we hit a pass, we know
2488          * that it is truely the start of the window.  If we get passing values
2489          * to start off with, we don't know if we are at the start of the window.
2490          *
2491          * The code assumes that a failure will always be found.
2492          * If a failure is not found, there is no easy way to get the middle
2493          * of the passing window.  I guess we can pretty much pick any value
2494          * but some values will be better than others.  Since the lowest speed
2495          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2496          * from experimentation it is safe to say you will always have a failure.
2497          *-----------------------------------------------------------------*/
2498
2499         /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2500         rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
2501
2502         puts(str);
2503
2504 calibration_loop:
2505         mfsdram(SDRAM_RQDC, rqdc_reg);
2506         mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2507                 SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
2508 #else /* CONFIG_DDR_RQDC_FIXED */
2509         /*
2510          * On Katmai the complete auto-calibration somehow doesn't seem to
2511          * produce the best results, meaning optimal values for RQFD/RFFD.
2512          * This was discovered by GDA using a high bandwidth scope,
2513          * analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
2514          * so now on Katmai "only" RFFD is auto-calibrated.
2515          */
2516         mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
2517 #endif /* CONFIG_DDR_RQDC_FIXED */
2518
2519         max_start = 0;
2520
2521         max_pass_length = 0;
2522         max_start = 0;
2523         max_end = 0;
2524         current_pass_length = 0;
2525         current_fail_length = 0;
2526         current_start = 0;
2527         fail_found = false;
2528         pass_found = false;
2529
2530         /*
2531          * get the delay line calibration register value
2532          */
2533         mfsdram(SDRAM_DLCR, dlycal);
2534         dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2535
2536         for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2537                 mfsdram(SDRAM_RFDC, rfdc_reg);
2538                 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2539
2540                 /*------------------------------------------------------------------
2541                  * Set the timing reg for the test.
2542                  *-----------------------------------------------------------------*/
2543                 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2544
2545                 /*------------------------------------------------------------------
2546                  * See if the rffd value passed.
2547                  *-----------------------------------------------------------------*/
2548                 if (short_mem_test()) {
2549                         if (fail_found == true) {
2550                                 pass_found = true;
2551                                 if (current_pass_length == 0)
2552                                         current_start = rffd;
2553
2554                                 current_fail_length = 0;
2555                                 current_pass_length++;
2556
2557                                 if (current_pass_length > max_pass_length) {
2558                                         max_pass_length = current_pass_length;
2559                                         max_start = current_start;
2560                                         max_end = rffd;
2561                                 }
2562                         }
2563                 } else {
2564                         current_pass_length = 0;
2565                         current_fail_length++;
2566
2567                         if (current_fail_length >= (dly_val >> 2)) {
2568                                 if (fail_found == false)
2569                                         fail_found = true;
2570                                 else if (pass_found == true)
2571                                         break;
2572                         }
2573                 }
2574         }               /* for rffd */
2575
2576         /*------------------------------------------------------------------
2577          * Set the average RFFD value
2578          *-----------------------------------------------------------------*/
2579         rffd_average = ((max_start + max_end) >> 1);
2580
2581         if (rffd_average < 0)
2582                 rffd_average = 0;
2583
2584         if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2585                 rffd_average = SDRAM_RFDC_RFFD_MAX;
2586         /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2587         mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2588
2589 #if !defined(CONFIG_DDR_RQDC_FIXED)
2590         max_pass_length = 0;
2591         max_start = 0;
2592         max_end = 0;
2593         current_pass_length = 0;
2594         current_fail_length = 0;
2595         current_start = 0;
2596         window_found = false;
2597         fail_found = false;
2598         pass_found = false;
2599
2600         for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2601                 mfsdram(SDRAM_RQDC, rqdc_reg);
2602                 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2603
2604                 /*------------------------------------------------------------------
2605                  * Set the timing reg for the test.
2606                  *-----------------------------------------------------------------*/
2607                 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2608
2609                 /*------------------------------------------------------------------
2610                  * See if the rffd value passed.
2611                  *-----------------------------------------------------------------*/
2612                 if (short_mem_test()) {
2613                         if (fail_found == true) {
2614                                 pass_found = true;
2615                                 if (current_pass_length == 0)
2616                                         current_start = rqfd;
2617
2618                                 current_fail_length = 0;
2619                                 current_pass_length++;
2620
2621                                 if (current_pass_length > max_pass_length) {
2622                                         max_pass_length = current_pass_length;
2623                                         max_start = current_start;
2624                                         max_end = rqfd;
2625                                 }
2626                         }
2627                 } else {
2628                         current_pass_length = 0;
2629                         current_fail_length++;
2630
2631                         if (fail_found == false) {
2632                                 fail_found = true;
2633                         } else if (pass_found == true) {
2634                                 window_found = true;
2635                                 break;
2636                         }
2637                 }
2638         }
2639
2640         rqfd_average = ((max_start + max_end) >> 1);
2641
2642         /*------------------------------------------------------------------
2643          * Make sure we found the valid read passing window.  Halt if not
2644          *-----------------------------------------------------------------*/
2645         if (window_found == false) {
2646                 if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
2647                         putc('\b');
2648                         putc(slash[loopi++ % 8]);
2649
2650                         /* try again from with a different RQFD start value */
2651                         rqfd_start++;
2652                         goto calibration_loop;
2653                 }
2654
2655                 printf("\nERROR: Cannot determine a common read delay for the "
2656                        "DIMM(s) installed.\n");
2657                 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2658                 ppc4xx_ibm_ddr2_register_dump();
2659                 spd_ddr_init_hang ();
2660         }
2661
2662         if (rqfd_average < 0)
2663                 rqfd_average = 0;
2664
2665         if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2666                 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2667
2668         mtsdram(SDRAM_RQDC,
2669                 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2670                 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2671
2672         blank_string(strlen(str));
2673 #endif /* CONFIG_DDR_RQDC_FIXED */
2674
2675         mfsdram(SDRAM_DLCR, val);
2676         debug("%s[%d] DLCR: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2677         mfsdram(SDRAM_RQDC, val);
2678         debug("%s[%d] RQDC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2679         mfsdram(SDRAM_RFDC, val);
2680         debug("%s[%d] RFDC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2681         mfsdram(SDRAM_RDCC, val);
2682         debug("%s[%d] RDCC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2683 }
2684 #else /* calibration test with hardvalues */
2685 /*-----------------------------------------------------------------------------+
2686  * DQS_calibration_process.
2687  *-----------------------------------------------------------------------------*/
2688 static void test(void)
2689 {
2690         unsigned long dimm_num;
2691         unsigned long ecc_temp;
2692         unsigned long i, j;
2693         unsigned long *membase;
2694         unsigned long bxcf[MAXRANKS];
2695         unsigned long val;
2696         char window_found;
2697         char begin_found[MAXDIMMS];
2698         char end_found[MAXDIMMS];
2699         char search_end[MAXDIMMS];
2700         unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2701                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2702                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2703                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2704                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2705                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2706                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2707                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2708                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2709                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2710                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2711                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2712                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2713                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2714                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2715                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2716                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2717
2718         /*------------------------------------------------------------------
2719          * Test to determine the best read clock delay tuning bits.
2720          *
2721          * Before the DDR controller can be used, the read clock delay needs to be
2722          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2723          * This value cannot be hardcoded into the program because it changes
2724          * depending on the board's setup and environment.
2725          * To do this, all delay values are tested to see if they
2726          * work or not.  By doing this, you get groups of fails with groups of
2727          * passing values.  The idea is to find the start and end of a passing
2728          * window and take the center of it to use as the read clock delay.
2729          *
2730          * A failure has to be seen first so that when we hit a pass, we know
2731          * that it is truely the start of the window.  If we get passing values
2732          * to start off with, we don't know if we are at the start of the window.
2733          *
2734          * The code assumes that a failure will always be found.
2735          * If a failure is not found, there is no easy way to get the middle
2736          * of the passing window.  I guess we can pretty much pick any value
2737          * but some values will be better than others.  Since the lowest speed
2738          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2739          * from experimentation it is safe to say you will always have a failure.
2740          *-----------------------------------------------------------------*/
2741         mfsdram(SDRAM_MCOPT1, ecc_temp);
2742         ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2743         mfsdram(SDRAM_MCOPT1, val);
2744         mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2745                 SDRAM_MCOPT1_MCHK_NON);
2746
2747         window_found = false;
2748         begin_found[0] = false;
2749         end_found[0] = false;
2750         search_end[0] = false;
2751         begin_found[1] = false;
2752         end_found[1] = false;
2753         search_end[1] = false;
2754
2755         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2756                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2757
2758                 /* Banks enabled */
2759                 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2760
2761                         /* Bank is enabled */
2762                         membase =
2763                                 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2764
2765                         /*------------------------------------------------------------------
2766                          * Run the short memory test.
2767                          *-----------------------------------------------------------------*/
2768                         for (i = 0; i < NUMMEMTESTS; i++) {
2769                                 for (j = 0; j < NUMMEMWORDS; j++) {
2770                                         membase[j] = test[i][j];
2771                                         ppcDcbf((u32)&(membase[j]));
2772                                 }
2773                                 sync();
2774                                 for (j = 0; j < NUMMEMWORDS; j++) {
2775                                         if (membase[j] != test[i][j]) {
2776                                                 ppcDcbf((u32)&(membase[j]));
2777                                                 break;
2778                                         }
2779                                         ppcDcbf((u32)&(membase[j]));
2780                                 }
2781                                 sync();
2782                                 if (j < NUMMEMWORDS)
2783                                         break;
2784                         }
2785
2786                         /*------------------------------------------------------------------
2787                          * See if the rffd value passed.
2788                          *-----------------------------------------------------------------*/
2789                         if (i < NUMMEMTESTS) {
2790                                 if ((end_found[dimm_num] == false) &&
2791                                     (search_end[dimm_num] == true)) {
2792                                         end_found[dimm_num] = true;
2793                                 }
2794                                 if ((end_found[0] == true) &&
2795                                     (end_found[1] == true))
2796                                         break;
2797                         } else {
2798                                 if (begin_found[dimm_num] == false) {
2799                                         begin_found[dimm_num] = true;
2800                                         search_end[dimm_num] = true;
2801                                 }
2802                         }
2803                 } else {
2804                         begin_found[dimm_num] = true;
2805                         end_found[dimm_num] = true;
2806                 }
2807         }
2808
2809         if ((begin_found[0] == true) && (begin_found[1] == true))
2810                 window_found = true;
2811
2812         /*------------------------------------------------------------------
2813          * Make sure we found the valid read passing window.  Halt if not
2814          *-----------------------------------------------------------------*/
2815         if (window_found == false) {
2816                 printf("ERROR: Cannot determine a common read delay for the "
2817                        "DIMM(s) installed.\n");
2818                 spd_ddr_init_hang ();
2819         }
2820
2821         /*------------------------------------------------------------------
2822          * Restore the ECC variable to what it originally was
2823          *-----------------------------------------------------------------*/
2824         mtsdram(SDRAM_MCOPT1,
2825                 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2826                 | ecc_temp);
2827 }
2828 #endif /* !HARD_CODED_DQS */
2829 #endif /* !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) */
2830
2831 #else /* CONFIG_SPD_EEPROM */
2832
2833 /*-----------------------------------------------------------------------------
2834  * Function:    initdram
2835  * Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller.
2836  *              The configuration is performed using static, compile-
2837  *              time parameters.
2838  *              Configures the PPC405EX(r) and PPC460EX/GT
2839  *---------------------------------------------------------------------------*/
2840 phys_size_t initdram(int board_type)
2841 {
2842         unsigned long val;
2843
2844 #if defined(CONFIG_440)
2845         mtdcr(SDRAM_R0BAS,      CONFIG_SYS_SDRAM_R0BAS);
2846         mtdcr(SDRAM_R1BAS,      CONFIG_SYS_SDRAM_R1BAS);
2847         mtdcr(SDRAM_R2BAS,      CONFIG_SYS_SDRAM_R2BAS);
2848         mtdcr(SDRAM_R3BAS,      CONFIG_SYS_SDRAM_R3BAS);
2849         mtdcr(SDRAM_PLBADDULL,  CONFIG_SYS_SDRAM_PLBADDULL);    /* MQ0_BAUL */
2850         mtdcr(SDRAM_PLBADDUHB,  CONFIG_SYS_SDRAM_PLBADDUHB);    /* MQ0_BAUH */
2851         mtdcr(SDRAM_CONF1LL,    CONFIG_SYS_SDRAM_CONF1LL);
2852         mtdcr(SDRAM_CONF1HB,    CONFIG_SYS_SDRAM_CONF1HB);
2853         mtdcr(SDRAM_CONFPATHB,  CONFIG_SYS_SDRAM_CONFPATHB);
2854 #endif
2855
2856         /* Set Memory Bank Configuration Registers */
2857
2858         mtsdram(SDRAM_MB0CF, CONFIG_SYS_SDRAM0_MB0CF);
2859         mtsdram(SDRAM_MB1CF, CONFIG_SYS_SDRAM0_MB1CF);
2860         mtsdram(SDRAM_MB2CF, CONFIG_SYS_SDRAM0_MB2CF);
2861         mtsdram(SDRAM_MB3CF, CONFIG_SYS_SDRAM0_MB3CF);
2862
2863         /* Set Memory Clock Timing Register */
2864
2865         mtsdram(SDRAM_CLKTR, CONFIG_SYS_SDRAM0_CLKTR);
2866
2867         /* Set Refresh Time Register */
2868
2869         mtsdram(SDRAM_RTR, CONFIG_SYS_SDRAM0_RTR);
2870
2871         /* Set SDRAM Timing Registers */
2872
2873         mtsdram(SDRAM_SDTR1, CONFIG_SYS_SDRAM0_SDTR1);
2874         mtsdram(SDRAM_SDTR2, CONFIG_SYS_SDRAM0_SDTR2);
2875         mtsdram(SDRAM_SDTR3, CONFIG_SYS_SDRAM0_SDTR3);
2876
2877         /* Set Mode and Extended Mode Registers */
2878
2879         mtsdram(SDRAM_MMODE, CONFIG_SYS_SDRAM0_MMODE);
2880         mtsdram(SDRAM_MEMODE, CONFIG_SYS_SDRAM0_MEMODE);
2881
2882         /* Set Memory Controller Options 1 Register */
2883
2884         mtsdram(SDRAM_MCOPT1, CONFIG_SYS_SDRAM0_MCOPT1);
2885
2886         /* Set Manual Initialization Control Registers */
2887
2888         mtsdram(SDRAM_INITPLR0, CONFIG_SYS_SDRAM0_INITPLR0);
2889         mtsdram(SDRAM_INITPLR1, CONFIG_SYS_SDRAM0_INITPLR1);
2890         mtsdram(SDRAM_INITPLR2, CONFIG_SYS_SDRAM0_INITPLR2);
2891         mtsdram(SDRAM_INITPLR3, CONFIG_SYS_SDRAM0_INITPLR3);
2892         mtsdram(SDRAM_INITPLR4, CONFIG_SYS_SDRAM0_INITPLR4);
2893         mtsdram(SDRAM_INITPLR5, CONFIG_SYS_SDRAM0_INITPLR5);
2894         mtsdram(SDRAM_INITPLR6, CONFIG_SYS_SDRAM0_INITPLR6);
2895         mtsdram(SDRAM_INITPLR7, CONFIG_SYS_SDRAM0_INITPLR7);
2896         mtsdram(SDRAM_INITPLR8, CONFIG_SYS_SDRAM0_INITPLR8);
2897         mtsdram(SDRAM_INITPLR9, CONFIG_SYS_SDRAM0_INITPLR9);
2898         mtsdram(SDRAM_INITPLR10, CONFIG_SYS_SDRAM0_INITPLR10);
2899         mtsdram(SDRAM_INITPLR11, CONFIG_SYS_SDRAM0_INITPLR11);
2900         mtsdram(SDRAM_INITPLR12, CONFIG_SYS_SDRAM0_INITPLR12);
2901         mtsdram(SDRAM_INITPLR13, CONFIG_SYS_SDRAM0_INITPLR13);
2902         mtsdram(SDRAM_INITPLR14, CONFIG_SYS_SDRAM0_INITPLR14);
2903         mtsdram(SDRAM_INITPLR15, CONFIG_SYS_SDRAM0_INITPLR15);
2904
2905         /* Set On-Die Termination Registers */
2906
2907         mtsdram(SDRAM_CODT, CONFIG_SYS_SDRAM0_CODT);
2908         mtsdram(SDRAM_MODT0, CONFIG_SYS_SDRAM0_MODT0);
2909         mtsdram(SDRAM_MODT1, CONFIG_SYS_SDRAM0_MODT1);
2910
2911         /* Set Write Timing Register */
2912
2913         mtsdram(SDRAM_WRDTR, CONFIG_SYS_SDRAM0_WRDTR);
2914
2915         /*
2916          * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
2917          * SDRAM0_MCOPT2[IPTR] = 1
2918          */
2919
2920         mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT |
2921                                SDRAM_MCOPT2_IPTR_EXECUTE));
2922
2923         /*
2924          * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
2925          * completion of initialization.
2926          */
2927
2928         do {
2929                 mfsdram(SDRAM_MCSTAT, val);
2930         } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
2931
2932         /* Set Delay Control Registers */
2933
2934         mtsdram(SDRAM_DLCR, CONFIG_SYS_SDRAM0_DLCR);
2935
2936 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
2937         mtsdram(SDRAM_RDCC, CONFIG_SYS_SDRAM0_RDCC);
2938         mtsdram(SDRAM_RQDC, CONFIG_SYS_SDRAM0_RQDC);
2939         mtsdram(SDRAM_RFDC, CONFIG_SYS_SDRAM0_RFDC);
2940 #endif /* !CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
2941
2942         /*
2943          * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
2944          */
2945
2946         mfsdram(SDRAM_MCOPT2, val);
2947         mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
2948
2949 #if defined(CONFIG_440)
2950         /*
2951          * Program TLB entries with caches enabled, for best performace
2952          * while auto-calibrating and ECC generation
2953          */
2954         program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), 0);
2955 #endif
2956
2957 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
2958         /*------------------------------------------------------------------
2959          | DQS calibration.
2960          +-----------------------------------------------------------------*/
2961         DQS_autocalibration();
2962 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
2963
2964         /*
2965          * Now complete RDSS configuration as mentioned on page 7 of the AMCC
2966          * PowerPC440SP/SPe DDR2 application note:
2967          * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
2968          */
2969         update_rdcc();
2970
2971 #if defined(CONFIG_DDR_ECC)
2972         do_program_ecc(0);
2973 #endif /* defined(CONFIG_DDR_ECC) */
2974
2975 #if defined(CONFIG_440)
2976         /*
2977          * Now after initialization (auto-calibration and ECC generation)
2978          * remove the TLB entries with caches enabled and program again with
2979          * desired cache functionality
2980          */
2981         remove_tlb(0, (CONFIG_SYS_MBYTES_SDRAM << 20));
2982         program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), MY_TLB_WORD2_I_ENABLE);
2983 #endif
2984
2985         ppc4xx_ibm_ddr2_register_dump();
2986
2987 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
2988         /*
2989          * Clear potential errors resulting from auto-calibration.
2990          * If not done, then we could get an interrupt later on when
2991          * exceptions are enabled.
2992          */
2993         set_mcsr(get_mcsr());
2994 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
2995
2996         return (CONFIG_SYS_MBYTES_SDRAM << 20);
2997 }
2998 #endif /* CONFIG_SPD_EEPROM */
2999
3000 #if defined(CONFIG_440)
3001 u32 mfdcr_any(u32 dcr)
3002 {
3003         u32 val;
3004
3005         switch (dcr) {
3006         case SDRAM_R0BAS + 0:
3007                 val = mfdcr(SDRAM_R0BAS + 0);
3008                 break;
3009         case SDRAM_R0BAS + 1:
3010                 val = mfdcr(SDRAM_R0BAS + 1);
3011                 break;
3012         case SDRAM_R0BAS + 2:
3013                 val = mfdcr(SDRAM_R0BAS + 2);
3014                 break;
3015         case SDRAM_R0BAS + 3:
3016                 val = mfdcr(SDRAM_R0BAS + 3);
3017                 break;
3018         default:
3019                 printf("DCR %d not defined in case statement!!!\n", dcr);
3020                 val = 0; /* just to satisfy the compiler */
3021         }
3022
3023         return val;
3024 }
3025
3026 void mtdcr_any(u32 dcr, u32 val)
3027 {
3028         switch (dcr) {
3029         case SDRAM_R0BAS + 0:
3030                 mtdcr(SDRAM_R0BAS + 0, val);
3031                 break;
3032         case SDRAM_R0BAS + 1:
3033                 mtdcr(SDRAM_R0BAS + 1, val);
3034                 break;
3035         case SDRAM_R0BAS + 2:
3036                 mtdcr(SDRAM_R0BAS + 2, val);
3037                 break;
3038         case SDRAM_R0BAS + 3:
3039                 mtdcr(SDRAM_R0BAS + 3, val);
3040                 break;
3041         default:
3042                 printf("DCR %d not defined in case statement!!!\n", dcr);
3043         }
3044 }
3045 #endif /* defined(CONFIG_440) */
3046
3047 inline void ppc4xx_ibm_ddr2_register_dump(void)
3048 {
3049 #if defined(DEBUG)
3050         printf("\nPPC4xx IBM DDR2 Register Dump:\n");
3051
3052 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3053      defined(CONFIG_460EX) || defined(CONFIG_460GT))
3054         PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R0BAS);
3055         PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R1BAS);
3056         PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R2BAS);
3057         PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R3BAS);
3058 #endif /* (defined(CONFIG_440SP) || ... */
3059 #if defined(CONFIG_405EX)
3060         PPC4xx_IBM_DDR2_DUMP_REGISTER(BESR);
3061         PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARL);
3062         PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARH);
3063         PPC4xx_IBM_DDR2_DUMP_REGISTER(WMIRQ);
3064         PPC4xx_IBM_DDR2_DUMP_REGISTER(PLBOPT);
3065         PPC4xx_IBM_DDR2_DUMP_REGISTER(PUABA);
3066 #endif /* defined(CONFIG_405EX) */
3067         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB0CF);
3068         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB1CF);
3069         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB2CF);
3070         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB3CF);
3071         PPC4xx_IBM_DDR2_DUMP_REGISTER(MCSTAT);
3072         PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT1);
3073         PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT2);
3074         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT0);
3075         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT1);
3076         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT2);
3077         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT3);
3078         PPC4xx_IBM_DDR2_DUMP_REGISTER(CODT);
3079 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3080      defined(CONFIG_460EX) || defined(CONFIG_460GT))
3081         PPC4xx_IBM_DDR2_DUMP_REGISTER(VVPR);
3082         PPC4xx_IBM_DDR2_DUMP_REGISTER(OPARS);
3083         /*
3084          * OPART is only used as a trigger register.
3085          *
3086          * No data is contained in this register, and reading or writing
3087          * to is can cause bad things to happen (hangs). Just skip it and
3088          * report "N/A".
3089          */
3090         printf("%20s = N/A\n", "SDRAM_OPART");
3091 #endif /* defined(CONFIG_440SP) || ... */
3092         PPC4xx_IBM_DDR2_DUMP_REGISTER(RTR);
3093         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR0);
3094         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR1);
3095         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR2);
3096         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR3);
3097         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR4);
3098         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR5);
3099         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR6);
3100         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR7);
3101         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR8);
3102         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR9);
3103         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR10);
3104         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR11);
3105         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR12);
3106         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR13);
3107         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR14);
3108         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR15);
3109         PPC4xx_IBM_DDR2_DUMP_REGISTER(RQDC);
3110         PPC4xx_IBM_DDR2_DUMP_REGISTER(RFDC);
3111         PPC4xx_IBM_DDR2_DUMP_REGISTER(RDCC);
3112         PPC4xx_IBM_DDR2_DUMP_REGISTER(DLCR);
3113         PPC4xx_IBM_DDR2_DUMP_REGISTER(CLKTR);
3114         PPC4xx_IBM_DDR2_DUMP_REGISTER(WRDTR);
3115         PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR1);
3116         PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR2);
3117         PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR3);
3118         PPC4xx_IBM_DDR2_DUMP_REGISTER(MMODE);
3119         PPC4xx_IBM_DDR2_DUMP_REGISTER(MEMODE);
3120         PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCES);
3121 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3122      defined(CONFIG_460EX) || defined(CONFIG_460GT))
3123         PPC4xx_IBM_DDR2_DUMP_REGISTER(CID);
3124 #endif /* defined(CONFIG_440SP) || ... */
3125         PPC4xx_IBM_DDR2_DUMP_REGISTER(RID);
3126         PPC4xx_IBM_DDR2_DUMP_REGISTER(FCSR);
3127         PPC4xx_IBM_DDR2_DUMP_REGISTER(RTSR);
3128 #endif /* defined(DEBUG) */
3129 }