arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c

   1 /*
   2  * arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
   3  * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
   4  * DDR2 controller (non Denali Core). Those currently are:
   5  *
   6  * 405:         405EX(r)
   7  * 440/460:     440SP/440SPe/460EX/460GT
   8  *
   9  * Copyright (c) 2008 Nuovation System Designs, LLC
  10  *   Grant Erickson <gerickson@nuovations.com>
  11
  12  * (C) Copyright 2007-2009
  13  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  14  *
  15  * COPYRIGHT   AMCC   CORPORATION 2004
  16  *
  17  * See file CREDITS for list of people who contributed to this
  18  * project.
  19  *
  20  * This program is free software; you can redistribute it and/or
  21  * modify it under the terms of the GNU General Public License as
  22  * published by the Free Software Foundation; either version 2 of
  23  * the License, or (at your option) any later version.
  24  *
  25  * This program is distributed in the hope that it will be useful,
  26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  28  * GNU General Public License for more details.
  29  *
  30  * You should have received a copy of the GNU General Public License
  31  * along with this program; if not, write to the Free Software
  32  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  33  * MA 02111-1307 USA
  34  *
  35  */
  36
  37 /* define DEBUG for debugging output (obviously ;-)) */
  38 #if 0
  39 #define DEBUG
  40 #endif
  41
  42 #include <common.h>
  43 #include <command.h>
  44 #include <asm/ppc4xx.h>
  45 #include <i2c.h>
  46 #include <asm/io.h>
  47 #include <asm/processor.h>
  48 #include <asm/mmu.h>
  49 #include <asm/cache.h>
  50
  51 #include "ecc.h"
  52
  53 #define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic)                         \
  54         do {                                                            \
  55                 u32 data;                                               \
  56                 mfsdram(SDRAM_##mnemonic, data);                        \
  57                 printf("%20s[%02x] = 0x%08X\n",                         \
  58                        "SDRAM_" #mnemonic, SDRAM_##mnemonic, data);     \
  59         } while (0)
  60
  61 #define PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(mnemonic)                      \
  62         do {                                                            \
  63                 u32 data;                                               \
  64                 data = mfdcr(SDRAM_##mnemonic);                         \
  65                 printf("%20s[%02x] = 0x%08X\n",                         \
  66                        "SDRAM_" #mnemonic, SDRAM_##mnemonic, data);     \
  67         } while (0)
  68
  69 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
  70 static void update_rdcc(void)
  71 {
  72         u32 val;
  73
  74         /*
  75          * Complete RDSS configuration as mentioned on page 7 of the AMCC
  76          * PowerPC440SP/SPe DDR2 application note:
  77          * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
  78          *
  79          * Or item #10 "10. Complete RDSS configuration" in chapter
  80          * "22.2.9 SDRAM Initialization" of AMCC PPC460EX/EXr/GT users
  81          * manual.
  82          */
  83         mfsdram(SDRAM_RTSR, val);
  84         if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
  85                 mfsdram(SDRAM_RDCC, val);
  86                 if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
  87                         val += 0x40000000;
  88                         mtsdram(SDRAM_RDCC, val);
  89                 }
  90         }
  91 }
  92 #endif
  93
  94 #if defined(CONFIG_440)
  95 /*
  96  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2
  97  * memory region. Right now the cache should still be disabled in U-Boot
  98  * because of the EMAC driver, that need its buffer descriptor to be located
  99  * in non cached memory.
 100  *
 101  * If at some time this restriction doesn't apply anymore, just define
 102  * CONFIG_4xx_DCACHE in the board config file and this code should setup
 103  * everything correctly.
 104  */
 105 #ifdef CONFIG_4xx_DCACHE
 106 /* enable caching on SDRAM */
 107 #define MY_TLB_WORD2_I_ENABLE           0
 108 #else
 109 /* disable caching on SDRAM */
 110 #define MY_TLB_WORD2_I_ENABLE           TLB_WORD2_I_ENABLE
 111 #endif /* CONFIG_4xx_DCACHE */
 112
 113 void dcbz_area(u32 start_address, u32 num_bytes);
 114 #endif /* CONFIG_440 */
 115
 116 #define MAXRANKS        4
 117 #define MAXBXCF         4
 118
 119 #define MULDIV64(m1, m2, d)     (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
 120
 121 #if !defined(CONFIG_NAND_SPL)
 122 /*-----------------------------------------------------------------------------+
 123  * sdram_memsize
 124  *-----------------------------------------------------------------------------*/
 125 phys_size_t sdram_memsize(void)
 126 {
 127         phys_size_t mem_size;
 128         unsigned long mcopt2;
 129         unsigned long mcstat;
 130         unsigned long mb0cf;
 131         unsigned long sdsz;
 132         unsigned long i;
 133
 134         mem_size = 0;
 135
 136         mfsdram(SDRAM_MCOPT2, mcopt2);
 137         mfsdram(SDRAM_MCSTAT, mcstat);
 138
 139         /* DDR controller must be enabled and not in self-refresh. */
 140         /* Otherwise memsize is zero. */
 141         if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
 142             && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
 143             && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
 144                 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
 145                 for (i = 0; i < MAXBXCF; i++) {
 146                         mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
 147                         /* Banks enabled */
 148                         if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
 149 #if defined(CONFIG_440)
 150                                 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
 151 #else
 152                                 sdsz = mb0cf & SDRAM_RXBAS_SDSZ_MASK;
 153 #endif
 154                                 switch(sdsz) {
 155                                 case SDRAM_RXBAS_SDSZ_8:
 156                                         mem_size+=8;
 157                                         break;
 158                                 case SDRAM_RXBAS_SDSZ_16:
 159                                         mem_size+=16;
 160                                         break;
 161                                 case SDRAM_RXBAS_SDSZ_32:
 162                                         mem_size+=32;
 163                                         break;
 164                                 case SDRAM_RXBAS_SDSZ_64:
 165                                         mem_size+=64;
 166                                         break;
 167                                 case SDRAM_RXBAS_SDSZ_128:
 168                                         mem_size+=128;
 169                                         break;
 170                                 case SDRAM_RXBAS_SDSZ_256:
 171                                         mem_size+=256;
 172                                         break;
 173                                 case SDRAM_RXBAS_SDSZ_512:
 174                                         mem_size+=512;
 175                                         break;
 176                                 case SDRAM_RXBAS_SDSZ_1024:
 177                                         mem_size+=1024;
 178                                         break;
 179                                 case SDRAM_RXBAS_SDSZ_2048:
 180                                         mem_size+=2048;
 181                                         break;
 182                                 case SDRAM_RXBAS_SDSZ_4096:
 183                                         mem_size+=4096;
 184                                         break;
 185                                 default:
 186                                         printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n"
 187                                                , sdsz);
 188                                         mem_size=0;
 189                                         break;
 190                                 }
 191                         }
 192                 }
 193         }
 194
 195         return mem_size << 20;
 196 }
 197
 198 /*-----------------------------------------------------------------------------+
 199  * is_ecc_enabled
 200  *-----------------------------------------------------------------------------*/
 201 static unsigned long is_ecc_enabled(void)
 202 {
 203         unsigned long val;
 204
 205         mfsdram(SDRAM_MCOPT1, val);
 206
 207         return SDRAM_MCOPT1_MCHK_CHK_DECODE(val);
 208 }
 209
 210 /*-----------------------------------------------------------------------------+
 211  * board_add_ram_info
 212  *-----------------------------------------------------------------------------*/
 213 void board_add_ram_info(int use_default)
 214 {
 215         PPC4xx_SYS_INFO board_cfg;
 216         u32 val;
 217
 218         if (is_ecc_enabled())
 219                 puts(" (ECC");
 220         else
 221                 puts(" (ECC not");
 222
 223         get_sys_info(&board_cfg);
 224
 225 #if defined(CONFIG_405EX)
 226         val = board_cfg.freqPLB;
 227 #else
 228         mfsdr(SDR0_DDR0, val);
 229         val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
 230 #endif
 231         printf(" enabled, %d MHz", (val * 2) / 1000000);
 232
 233         mfsdram(SDRAM_MMODE, val);
 234         val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
 235         printf(", CL%d)", val);
 236 }
 237 #endif /* !CONFIG_NAND_SPL */
 238
 239 #if defined(CONFIG_SPD_EEPROM)
 240
 241 /*-----------------------------------------------------------------------------+
 242  * Defines
 243  *-----------------------------------------------------------------------------*/
 244 #ifndef TRUE
 245 #define TRUE            1
 246 #endif
 247 #ifndef FALSE
 248 #define FALSE           0
 249 #endif
 250
 251 #define SDRAM_DDR1      1
 252 #define SDRAM_DDR2      2
 253 #define SDRAM_NONE      0
 254
 255 #define MAXDIMMS        2
 256 #define MAX_SPD_BYTES   256   /* Max number of bytes on the DIMM's SPD EEPROM */
 257
 258 #define ONE_BILLION     1000000000
 259
 260 #define CMD_NOP         (7 << 19)
 261 #define CMD_PRECHARGE   (2 << 19)
 262 #define CMD_REFRESH     (1 << 19)
 263 #define CMD_EMR         (0 << 19)
 264 #define CMD_READ        (5 << 19)
 265 #define CMD_WRITE       (4 << 19)
 266
 267 #define SELECT_MR       (0 << 16)
 268 #define SELECT_EMR      (1 << 16)
 269 #define SELECT_EMR2     (2 << 16)
 270 #define SELECT_EMR3     (3 << 16)
 271
 272 /* MR */
 273 #define DLL_RESET       0x00000100
 274
 275 #define WRITE_RECOV_2   (1 << 9)
 276 #define WRITE_RECOV_3   (2 << 9)
 277 #define WRITE_RECOV_4   (3 << 9)
 278 #define WRITE_RECOV_5   (4 << 9)
 279 #define WRITE_RECOV_6   (5 << 9)
 280
 281 #define BURST_LEN_4     0x00000002
 282
 283 /* EMR */
 284 #define ODT_0_OHM       0x00000000
 285 #define ODT_50_OHM      0x00000044
 286 #define ODT_75_OHM      0x00000004
 287 #define ODT_150_OHM     0x00000040
 288
 289 #define ODS_FULL        0x00000000
 290 #define ODS_REDUCED     0x00000002
 291 #define OCD_CALIB_DEF   0x00000380
 292
 293 /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
 294 #define ODT_EB0R        (0x80000000 >> 8)
 295 #define ODT_EB0W        (0x80000000 >> 7)
 296 #define CALC_ODT_R(n)   (ODT_EB0R << (n << 1))
 297 #define CALC_ODT_W(n)   (ODT_EB0W << (n << 1))
 298 #define CALC_ODT_RW(n)  (CALC_ODT_R(n) | CALC_ODT_W(n))
 299
 300 /* Defines for the Read Cycle Delay test */
 301 #define NUMMEMTESTS     8
 302 #define NUMMEMWORDS     8
 303 #define NUMLOOPS        64              /* memory test loops */
 304
 305 /*
 306  * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
 307  * To support such configurations, we "only" map the first 2GB via the TLB's. We
 308  * need some free virtual address space for the remaining peripherals like, SoC
 309  * devices, FLASH etc.
 310  *
 311  * Note that ECC is currently not supported on configurations with more than 2GB
 312  * SDRAM. This is because we only map the first 2GB on such systems, and therefore
 313  * the ECC parity byte of the remaining area can't be written.
 314  */
 315
 316 /*
 317  * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
 318  */
 319 void __spd_ddr_init_hang (void)
 320 {
 321         hang ();
 322 }
 323 void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
 324
 325 /*
 326  * To provide an interface for board specific config values in this common
 327  * DDR setup code, we implement he "weak" default functions here. They return
 328  * the default value back to the caller.
 329  *
 330  * Please see include/configs/yucca.h for an example fora board specific
 331  * implementation.
 332  */
 333 u32 __ddr_wrdtr(u32 default_val)
 334 {
 335         return default_val;
 336 }
 337 u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
 338
 339 u32 __ddr_clktr(u32 default_val)
 340 {
 341         return default_val;
 342 }
 343 u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
 344
 345
 346 /* Private Structure Definitions */
 347
 348 /* enum only to ease code for cas latency setting */
 349 typedef enum ddr_cas_id {
 350         DDR_CAS_2      = 20,
 351         DDR_CAS_2_5    = 25,
 352         DDR_CAS_3      = 30,
 353         DDR_CAS_4      = 40,
 354         DDR_CAS_5      = 50
 355 } ddr_cas_id_t;
 356
 357 /*-----------------------------------------------------------------------------+
 358  * Prototypes
 359  *-----------------------------------------------------------------------------*/
 360 static void get_spd_info(unsigned long *dimm_populated,
 361                          unsigned char *iic0_dimm_addr,
 362                          unsigned long num_dimm_banks);
 363 static void check_mem_type(unsigned long *dimm_populated,
 364                            unsigned char *iic0_dimm_addr,
 365                            unsigned long num_dimm_banks);
 366 static void check_frequency(unsigned long *dimm_populated,
 367                             unsigned char *iic0_dimm_addr,
 368                             unsigned long num_dimm_banks);
 369 static void check_rank_number(unsigned long *dimm_populated,
 370                               unsigned char *iic0_dimm_addr,
 371                               unsigned long num_dimm_banks);
 372 static void check_voltage_type(unsigned long *dimm_populated,
 373                                unsigned char *iic0_dimm_addr,
 374                                unsigned long num_dimm_banks);
 375 static void program_memory_queue(unsigned long *dimm_populated,
 376                                  unsigned char *iic0_dimm_addr,
 377                                  unsigned long num_dimm_banks);
 378 static void program_codt(unsigned long *dimm_populated,
 379                          unsigned char *iic0_dimm_addr,
 380                          unsigned long num_dimm_banks);
 381 static void program_mode(unsigned long *dimm_populated,
 382                          unsigned char *iic0_dimm_addr,
 383                          unsigned long num_dimm_banks,
 384                          ddr_cas_id_t *selected_cas,
 385                          int *write_recovery);
 386 static void program_tr(unsigned long *dimm_populated,
 387                        unsigned char *iic0_dimm_addr,
 388                        unsigned long num_dimm_banks);
 389 static void program_rtr(unsigned long *dimm_populated,
 390                         unsigned char *iic0_dimm_addr,
 391                         unsigned long num_dimm_banks);
 392 static void program_bxcf(unsigned long *dimm_populated,
 393                          unsigned char *iic0_dimm_addr,
 394                          unsigned long num_dimm_banks);
 395 static void program_copt1(unsigned long *dimm_populated,
 396                           unsigned char *iic0_dimm_addr,
 397                           unsigned long num_dimm_banks);
 398 static void program_initplr(unsigned long *dimm_populated,
 399                             unsigned char *iic0_dimm_addr,
 400                             unsigned long num_dimm_banks,
 401                             ddr_cas_id_t selected_cas,
 402                             int write_recovery);
 403 #ifdef CONFIG_DDR_ECC
 404 static void program_ecc(unsigned long *dimm_populated,
 405                         unsigned char *iic0_dimm_addr,
 406                         unsigned long num_dimm_banks,
 407                         unsigned long tlb_word2_i_value);
 408 #endif
 409 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
 410 static void program_DQS_calibration(unsigned long *dimm_populated,
 411                                 unsigned char *iic0_dimm_addr,
 412                                 unsigned long num_dimm_banks);
 413 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
 414 static void     test(void);
 415 #else
 416 static void     DQS_calibration_process(void);
 417 #endif
 418 #endif
 419
 420 static unsigned char spd_read(uchar chip, uint addr)
 421 {
 422         unsigned char data[2];
 423
 424         if (i2c_probe(chip) == 0)
 425                 if (i2c_read(chip, addr, 1, data, 1) == 0)
 426                         return data[0];
 427
 428         return 0;
 429 }
 430
 431 /*-----------------------------------------------------------------------------+
 432  * initdram.  Initializes the 440SP Memory Queue and DDR SDRAM controller.
 433  * Note: This routine runs from flash with a stack set up in the chip's
 434  * sram space.  It is important that the routine does not require .sbss, .bss or
 435  * .data sections.  It also cannot call routines that require these sections.
 436  *-----------------------------------------------------------------------------*/
 437 /*-----------------------------------------------------------------------------
 438  * Function:     initdram
 439  * Description:  Configures SDRAM memory banks for DDR operation.
 440  *               Auto Memory Configuration option reads the DDR SDRAM EEPROMs
 441  *               via the IIC bus and then configures the DDR SDRAM memory
 442  *               banks appropriately. If Auto Memory Configuration is
 443  *               not used, it is assumed that no DIMM is plugged
 444  *-----------------------------------------------------------------------------*/
 445 phys_size_t initdram(int board_type)
 446 {
 447         unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 448         unsigned char spd0[MAX_SPD_BYTES];
 449         unsigned char spd1[MAX_SPD_BYTES];
 450         unsigned char *dimm_spd[MAXDIMMS];
 451         unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE};
 452         unsigned long num_dimm_banks;           /* on board dimm banks */
 453         unsigned long val;
 454         ddr_cas_id_t selected_cas = DDR_CAS_5;  /* preset to silence compiler */
 455         int write_recovery;
 456         phys_size_t dram_size = 0;
 457
 458         num_dimm_banks = sizeof(iic0_dimm_addr);
 459
 460         /*------------------------------------------------------------------
 461          * Set up an array of SPD matrixes.
 462          *-----------------------------------------------------------------*/
 463         dimm_spd[0] = spd0;
 464         dimm_spd[1] = spd1;
 465
 466         /*------------------------------------------------------------------
 467          * Reset the DDR-SDRAM controller.
 468          *-----------------------------------------------------------------*/
 469         mtsdr(SDR0_SRST, SDR0_SRST0_DMC);
 470         mtsdr(SDR0_SRST, 0x00000000);
 471
 472         /*
 473          * Make sure I2C controller is initialized
 474          * before continuing.
 475          */
 476
 477         /* switch to correct I2C bus */
 478         I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
 479         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 480
 481         /*------------------------------------------------------------------
 482          * Clear out the serial presence detect buffers.
 483          * Perform IIC reads from the dimm.  Fill in the spds.
 484          * Check to see if the dimm slots are populated
 485          *-----------------------------------------------------------------*/
 486         get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 487
 488         /*------------------------------------------------------------------
 489          * Check the memory type for the dimms plugged.
 490          *-----------------------------------------------------------------*/
 491         check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 492
 493         /*------------------------------------------------------------------
 494          * Check the frequency supported for the dimms plugged.
 495          *-----------------------------------------------------------------*/
 496         check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 497
 498         /*------------------------------------------------------------------
 499          * Check the total rank number.
 500          *-----------------------------------------------------------------*/
 501         check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 502
 503         /*------------------------------------------------------------------
 504          * Check the voltage type for the dimms plugged.
 505          *-----------------------------------------------------------------*/
 506         check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 507
 508         /*------------------------------------------------------------------
 509          * Program SDRAM controller options 2 register
 510          * Except Enabling of the memory controller.
 511          *-----------------------------------------------------------------*/
 512         mfsdram(SDRAM_MCOPT2, val);
 513         mtsdram(SDRAM_MCOPT2,
 514                 (val &
 515                  ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
 516                    SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
 517                    SDRAM_MCOPT2_ISIE_MASK))
 518                 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
 519                    SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
 520                    SDRAM_MCOPT2_ISIE_ENABLE));
 521
 522         /*------------------------------------------------------------------
 523          * Program SDRAM controller options 1 register
 524          * Note: Does not enable the memory controller.
 525          *-----------------------------------------------------------------*/
 526         program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 527
 528         /*------------------------------------------------------------------
 529          * Set the SDRAM Controller On Die Termination Register
 530          *-----------------------------------------------------------------*/
 531         program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 532
 533         /*------------------------------------------------------------------
 534          * Program SDRAM refresh register.
 535          *-----------------------------------------------------------------*/
 536         program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 537
 538         /*------------------------------------------------------------------
 539          * Program SDRAM mode register.
 540          *-----------------------------------------------------------------*/
 541         program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 542                      &selected_cas, &write_recovery);
 543
 544         /*------------------------------------------------------------------
 545          * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
 546          *-----------------------------------------------------------------*/
 547         mfsdram(SDRAM_WRDTR, val);
 548         mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
 549                 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
 550
 551         /*------------------------------------------------------------------
 552          * Set the SDRAM Clock Timing Register
 553          *-----------------------------------------------------------------*/
 554         mfsdram(SDRAM_CLKTR, val);
 555         mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
 556                 ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
 557
 558         /*------------------------------------------------------------------
 559          * Program the BxCF registers.
 560          *-----------------------------------------------------------------*/
 561         program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 562
 563         /*------------------------------------------------------------------
 564          * Program SDRAM timing registers.
 565          *-----------------------------------------------------------------*/
 566         program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 567
 568         /*------------------------------------------------------------------
 569          * Set the Extended Mode register
 570          *-----------------------------------------------------------------*/
 571         mfsdram(SDRAM_MEMODE, val);
 572         mtsdram(SDRAM_MEMODE,
 573                 (val & ~(SDRAM_MEMODE_DIC_MASK  | SDRAM_MEMODE_DLL_MASK |
 574                          SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
 575                 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
 576                  | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
 577
 578         /*------------------------------------------------------------------
 579          * Program Initialization preload registers.
 580          *-----------------------------------------------------------------*/
 581         program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 582                         selected_cas, write_recovery);
 583
 584         /*------------------------------------------------------------------
 585          * Delay to ensure 200usec have elapsed since reset.
 586          *-----------------------------------------------------------------*/
 587         udelay(400);
 588
 589         /*------------------------------------------------------------------
 590          * Set the memory queue core base addr.
 591          *-----------------------------------------------------------------*/
 592         program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 593
 594         /*------------------------------------------------------------------
 595          * Program SDRAM controller options 2 register
 596          * Enable the memory controller.
 597          *-----------------------------------------------------------------*/
 598         mfsdram(SDRAM_MCOPT2, val);
 599         mtsdram(SDRAM_MCOPT2,
 600                 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
 601                          SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
 602                          SDRAM_MCOPT2_IPTR_EXECUTE);
 603
 604         /*------------------------------------------------------------------
 605          * Wait for IPTR_EXECUTE init sequence to complete.
 606          *-----------------------------------------------------------------*/
 607         do {
 608                 mfsdram(SDRAM_MCSTAT, val);
 609         } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
 610
 611         /* enable the controller only after init sequence completes */
 612         mfsdram(SDRAM_MCOPT2, val);
 613         mtsdram(SDRAM_MCOPT2, (val | SDRAM_MCOPT2_DCEN_ENABLE));
 614
 615         /* Make sure delay-line calibration is done before proceeding */
 616         do {
 617                 mfsdram(SDRAM_DLCR, val);
 618         } while (!(val & SDRAM_DLCR_DLCS_COMPLETE));
 619
 620         /* get installed memory size */
 621         dram_size = sdram_memsize();
 622
 623         /*
 624          * Limit size to 2GB
 625          */
 626         if (dram_size > CONFIG_MAX_MEM_MAPPED)
 627                 dram_size = CONFIG_MAX_MEM_MAPPED;
 628
 629         /* and program tlb entries for this size (dynamic) */
 630
 631         /*
 632          * Program TLB entries with caches enabled, for best performace
 633          * while auto-calibrating and ECC generation
 634          */
 635         program_tlb(0, 0, dram_size, 0);
 636
 637         /*------------------------------------------------------------------
 638          * DQS calibration.
 639          *-----------------------------------------------------------------*/
 640 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
 641         DQS_autocalibration();
 642 #else
 643         program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 644 #endif
 645         /*
 646          * Now complete RDSS configuration as mentioned on page 7 of the AMCC
 647          * PowerPC440SP/SPe DDR2 application note:
 648          * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
 649          */
 650         update_rdcc();
 651
 652 #ifdef CONFIG_DDR_ECC
 653         /*------------------------------------------------------------------
 654          * If ecc is enabled, initialize the parity bits.
 655          *-----------------------------------------------------------------*/
 656         program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
 657 #endif
 658
 659         /*
 660          * Flush the dcache before removing the TLB with caches
 661          * enabled. Otherwise this might lead to problems later on,
 662          * e.g. while booting Linux (as seen on ICON-440SPe).
 663          */
 664         flush_dcache();
 665
 666         /*
 667          * Now after initialization (auto-calibration and ECC generation)
 668          * remove the TLB entries with caches enabled and program again with
 669          * desired cache functionality
 670          */
 671         remove_tlb(0, dram_size);
 672         program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
 673
 674         ppc4xx_ibm_ddr2_register_dump();
 675
 676         /*
 677          * Clear potential errors resulting from auto-calibration.
 678          * If not done, then we could get an interrupt later on when
 679          * exceptions are enabled.
 680          */
 681         set_mcsr(get_mcsr());
 682
 683         return sdram_memsize();
 684 }
 685
 686 static void get_spd_info(unsigned long *dimm_populated,
 687                          unsigned char *iic0_dimm_addr,
 688                          unsigned long num_dimm_banks)
 689 {
 690         unsigned long dimm_num;
 691         unsigned long dimm_found;
 692         unsigned char num_of_bytes;
 693         unsigned char total_size;
 694
 695         dimm_found = FALSE;
 696         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 697                 num_of_bytes = 0;
 698                 total_size = 0;
 699
 700                 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
 701                 debug("\nspd_read(0x%x) returned %d\n",
 702                       iic0_dimm_addr[dimm_num], num_of_bytes);
 703                 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 704                 debug("spd_read(0x%x) returned %d\n",
 705                       iic0_dimm_addr[dimm_num], total_size);
 706
 707                 if ((num_of_bytes != 0) && (total_size != 0)) {
 708                         dimm_populated[dimm_num] = TRUE;
 709                         dimm_found = TRUE;
 710                         debug("DIMM slot %lu: populated\n", dimm_num);
 711                 } else {
 712                         dimm_populated[dimm_num] = FALSE;
 713                         debug("DIMM slot %lu: Not populated\n", dimm_num);
 714                 }
 715         }
 716
 717         if (dimm_found == FALSE) {
 718                 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
 719                 spd_ddr_init_hang ();
 720         }
 721 }
 722
 723
 724 /*------------------------------------------------------------------
 725  * For the memory DIMMs installed, this routine verifies that they
 726  * really are DDR specific DIMMs.
 727  *-----------------------------------------------------------------*/
 728 static void check_mem_type(unsigned long *dimm_populated,
 729                            unsigned char *iic0_dimm_addr,
 730                            unsigned long num_dimm_banks)
 731 {
 732         unsigned long dimm_num;
 733         unsigned long dimm_type;
 734
 735         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 736                 if (dimm_populated[dimm_num] == TRUE) {
 737                         dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
 738                         switch (dimm_type) {
 739                         case 1:
 740                                 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
 741                                        "slot %d.\n", (unsigned int)dimm_num);
 742                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 743                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 744                                 spd_ddr_init_hang ();
 745                                 break;
 746                         case 2:
 747                                 printf("ERROR: EDO DIMM detected in slot %d.\n",
 748                                        (unsigned int)dimm_num);
 749                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 750                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 751                                 spd_ddr_init_hang ();
 752                                 break;
 753                         case 3:
 754                                 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
 755                                        (unsigned int)dimm_num);
 756                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 757                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 758                                 spd_ddr_init_hang ();
 759                                 break;
 760                         case 4:
 761                                 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
 762                                        (unsigned int)dimm_num);
 763                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 764                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 765                                 spd_ddr_init_hang ();
 766                                 break;
 767                         case 5:
 768                                 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
 769                                        (unsigned int)dimm_num);
 770                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 771                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 772                                 spd_ddr_init_hang ();
 773                                 break;
 774                         case 6:
 775                                 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
 776                                        (unsigned int)dimm_num);
 777                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 778                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 779                                 spd_ddr_init_hang ();
 780                                 break;
 781                         case 7:
 782                                 debug("DIMM slot %lu: DDR1 SDRAM detected\n", dimm_num);
 783                                 dimm_populated[dimm_num] = SDRAM_DDR1;
 784                                 break;
 785                         case 8:
 786                                 debug("DIMM slot %lu: DDR2 SDRAM detected\n", dimm_num);
 787                                 dimm_populated[dimm_num] = SDRAM_DDR2;
 788                                 break;
 789                         default:
 790                                 printf("ERROR: Unknown DIMM detected in slot %d.\n",
 791                                        (unsigned int)dimm_num);
 792                                 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
 793                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 794                                 spd_ddr_init_hang ();
 795                                 break;
 796                         }
 797                 }
 798         }
 799         for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
 800                 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
 801                     && (dimm_populated[dimm_num]   != SDRAM_NONE)
 802                     && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
 803                         printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
 804                         spd_ddr_init_hang ();
 805                 }
 806         }
 807 }
 808
 809 /*------------------------------------------------------------------
 810  * For the memory DIMMs installed, this routine verifies that
 811  * frequency previously calculated is supported.
 812  *-----------------------------------------------------------------*/
 813 static void check_frequency(unsigned long *dimm_populated,
 814                             unsigned char *iic0_dimm_addr,
 815                             unsigned long num_dimm_banks)
 816 {
 817         unsigned long dimm_num;
 818         unsigned long tcyc_reg;
 819         unsigned long cycle_time;
 820         unsigned long calc_cycle_time;
 821         unsigned long sdram_freq;
 822         unsigned long sdr_ddrpll;
 823         PPC4xx_SYS_INFO board_cfg;
 824
 825         /*------------------------------------------------------------------
 826          * Get the board configuration info.
 827          *-----------------------------------------------------------------*/
 828         get_sys_info(&board_cfg);
 829
 830         mfsdr(SDR0_DDR0, sdr_ddrpll);
 831         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
 832
 833         /*
 834          * calc_cycle_time is calculated from DDR frequency set by board/chip
 835          * and is expressed in multiple of 10 picoseconds
 836          * to match the way DIMM cycle time is calculated below.
 837          */
 838         calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
 839
 840         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 841                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 842                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
 843                         /*
 844                          * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
 845                          * the higher order nibble (bits 4-7) designates the cycle time
 846                          * to a granularity of 1ns;
 847                          * the value presented by the lower order nibble (bits 0-3)
 848                          * has a granularity of .1ns and is added to the value designated
 849                          * by the higher nibble. In addition, four lines of the lower order
 850                          * nibble are assigned to support +.25,+.33, +.66 and +.75.
 851                          */
 852                          /* Convert from hex to decimal */
 853                         if ((tcyc_reg & 0x0F) == 0x0D)
 854                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
 855                         else if ((tcyc_reg & 0x0F) == 0x0C)
 856                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
 857                         else if ((tcyc_reg & 0x0F) == 0x0B)
 858                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
 859                         else if ((tcyc_reg & 0x0F) == 0x0A)
 860                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
 861                         else
 862                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
 863                                         ((tcyc_reg & 0x0F)*10);
 864                         debug("cycle_time=%lu [10 picoseconds]\n", cycle_time);
 865
 866                         if  (cycle_time > (calc_cycle_time + 10)) {
 867                                 /*
 868                                  * the provided sdram cycle_time is too small
 869                                  * for the available DIMM cycle_time.
 870                                  * The additionnal 100ps is here to accept a small incertainty.
 871                                  */
 872                                 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
 873                                        "slot %d \n while calculated cycle time is %d ps.\n",
 874                                        (unsigned int)(cycle_time*10),
 875                                        (unsigned int)dimm_num,
 876                                        (unsigned int)(calc_cycle_time*10));
 877                                 printf("Replace the DIMM, or change DDR frequency via "
 878                                        "strapping bits.\n\n");
 879                                 spd_ddr_init_hang ();
 880                         }
 881                 }
 882         }
 883 }
 884
 885 /*------------------------------------------------------------------
 886  * For the memory DIMMs installed, this routine verifies two
 887  * ranks/banks maximum are availables.
 888  *-----------------------------------------------------------------*/
 889 static void check_rank_number(unsigned long *dimm_populated,
 890                               unsigned char *iic0_dimm_addr,
 891                               unsigned long num_dimm_banks)
 892 {
 893         unsigned long dimm_num;
 894         unsigned long dimm_rank;
 895         unsigned long total_rank = 0;
 896
 897         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 898                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 899                         dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
 900                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
 901                                 dimm_rank = (dimm_rank & 0x0F) +1;
 902                         else
 903                                 dimm_rank = dimm_rank & 0x0F;
 904
 905
 906                         if (dimm_rank > MAXRANKS) {
 907                                 printf("ERROR: DRAM DIMM detected with %lu ranks in "
 908                                        "slot %lu is not supported.\n", dimm_rank, dimm_num);
 909                                 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 910                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 911                                 spd_ddr_init_hang ();
 912                         } else
 913                                 total_rank += dimm_rank;
 914                 }
 915                 if (total_rank > MAXRANKS) {
 916                         printf("ERROR: DRAM DIMM detected with a total of %d ranks "
 917                                "for all slots.\n", (unsigned int)total_rank);
 918                         printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 919                         printf("Remove one of the DIMM modules.\n\n");
 920                         spd_ddr_init_hang ();
 921                 }
 922         }
 923 }
 924
 925 /*------------------------------------------------------------------
 926  * only support 2.5V modules.
 927  * This routine verifies this.
 928  *-----------------------------------------------------------------*/
 929 static void check_voltage_type(unsigned long *dimm_populated,
 930                                unsigned char *iic0_dimm_addr,
 931                                unsigned long num_dimm_banks)
 932 {
 933         unsigned long dimm_num;
 934         unsigned long voltage_type;
 935
 936         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 937                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 938                         voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
 939                         switch (voltage_type) {
 940                         case 0x00:
 941                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 942                                 printf("This DIMM is 5.0 Volt/TTL.\n");
 943                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 944                                        (unsigned int)dimm_num);
 945                                 spd_ddr_init_hang ();
 946                                 break;
 947                         case 0x01:
 948                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 949                                 printf("This DIMM is LVTTL.\n");
 950                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 951                                        (unsigned int)dimm_num);
 952                                 spd_ddr_init_hang ();
 953                                 break;
 954                         case 0x02:
 955                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 956                                 printf("This DIMM is 1.5 Volt.\n");
 957                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 958                                        (unsigned int)dimm_num);
 959                                 spd_ddr_init_hang ();
 960                                 break;
 961                         case 0x03:
 962                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 963                                 printf("This DIMM is 3.3 Volt/TTL.\n");
 964                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 965                                        (unsigned int)dimm_num);
 966                                 spd_ddr_init_hang ();
 967                                 break;
 968                         case 0x04:
 969                                 /* 2.5 Voltage only for DDR1 */
 970                                 break;
 971                         case 0x05:
 972                                 /* 1.8 Voltage only for DDR2 */
 973                                 break;
 974                         default:
 975                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 976                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 977                                        (unsigned int)dimm_num);
 978                                 spd_ddr_init_hang ();
 979                                 break;
 980                         }
 981                 }
 982         }
 983 }
 984
 985 /*-----------------------------------------------------------------------------+
 986  * program_copt1.
 987  *-----------------------------------------------------------------------------*/
 988 static void program_copt1(unsigned long *dimm_populated,
 989                           unsigned char *iic0_dimm_addr,
 990                           unsigned long num_dimm_banks)
 991 {
 992         unsigned long dimm_num;
 993         unsigned long mcopt1;
 994         unsigned long ecc_enabled;
 995         unsigned long ecc = 0;
 996         unsigned long data_width = 0;
 997         unsigned long dimm_32bit;
 998         unsigned long dimm_64bit;
 999         unsigned long registered = 0;
1000         unsigned long attribute = 0;
1001         unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
1002         unsigned long bankcount;
1003         unsigned long ddrtype;
1004         unsigned long val;
1005
1006 #ifdef CONFIG_DDR_ECC
1007         ecc_enabled = TRUE;
1008 #else
1009         ecc_enabled = FALSE;
1010 #endif
1011         dimm_32bit = FALSE;
1012         dimm_64bit = FALSE;
1013         buf0 = FALSE;
1014         buf1 = FALSE;
1015
1016         /*------------------------------------------------------------------
1017          * Set memory controller options reg 1, SDRAM_MCOPT1.
1018          *-----------------------------------------------------------------*/
1019         mfsdram(SDRAM_MCOPT1, val);
1020         mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
1021                          SDRAM_MCOPT1_PMU_MASK  | SDRAM_MCOPT1_DMWD_MASK |
1022                          SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
1023                          SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
1024                          SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
1025                          SDRAM_MCOPT1_DREF_MASK);
1026
1027         mcopt1 |= SDRAM_MCOPT1_QDEP;
1028         mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
1029         mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
1030         mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
1031         mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
1032         mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
1033
1034         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1035                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1036                         /* test ecc support */
1037                         ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
1038                         if (ecc != 0x02) /* ecc not supported */
1039                                 ecc_enabled = FALSE;
1040
1041                         /* test bank count */
1042                         bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
1043                         if (bankcount == 0x04) /* bank count = 4 */
1044                                 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
1045                         else /* bank count = 8 */
1046                                 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
1047
1048                         /* test DDR type */
1049                         ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
1050                         /* test for buffered/unbuffered, registered, differential clocks */
1051                         registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
1052                         attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
1053
1054                         /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
1055                         if (dimm_num == 0) {
1056                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1057                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1058                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1059                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1060                                 if (registered == 1) { /* DDR2 always buffered */
1061                                         /* TODO: what about above  comments ? */
1062                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
1063                                         buf0 = TRUE;
1064                                 } else {
1065                                         /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
1066                                         if ((attribute & 0x02) == 0x00) {
1067                                                 /* buffered not supported */
1068                                                 buf0 = FALSE;
1069                                         } else {
1070                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
1071                                                 buf0 = TRUE;
1072                                         }
1073                                 }
1074                         }
1075                         else if (dimm_num == 1) {
1076                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1077                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1078                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1079                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1080                                 if (registered == 1) {
1081                                         /* DDR2 always buffered */
1082                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
1083                                         buf1 = TRUE;
1084                                 } else {
1085                                         if ((attribute & 0x02) == 0x00) {
1086                                                 /* buffered not supported */
1087                                                 buf1 = FALSE;
1088                                         } else {
1089                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
1090                                                 buf1 = TRUE;
1091                                         }
1092                                 }
1093                         }
1094
1095                         /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
1096                         data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
1097                                 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
1098
1099                         switch (data_width) {
1100                         case 72:
1101                         case 64:
1102                                 dimm_64bit = TRUE;
1103                                 break;
1104                         case 40:
1105                         case 32:
1106                                 dimm_32bit = TRUE;
1107                                 break;
1108                         default:
1109                                 printf("WARNING: Detected a DIMM with a data width of %lu bits.\n",
1110                                        data_width);
1111                                 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
1112                                 break;
1113                         }
1114                 }
1115         }
1116
1117         /* verify matching properties */
1118         if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
1119                 if (buf0 != buf1) {
1120                         printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
1121                         spd_ddr_init_hang ();
1122                 }
1123         }
1124
1125         if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
1126                 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
1127                 spd_ddr_init_hang ();
1128         }
1129         else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
1130                 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1131         } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
1132                 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1133         } else {
1134                 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
1135                 spd_ddr_init_hang ();
1136         }
1137
1138         if (ecc_enabled == TRUE)
1139                 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1140         else
1141                 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1142
1143         mtsdram(SDRAM_MCOPT1, mcopt1);
1144 }
1145
1146 /*-----------------------------------------------------------------------------+
1147  * program_codt.
1148  *-----------------------------------------------------------------------------*/
1149 static void program_codt(unsigned long *dimm_populated,
1150                          unsigned char *iic0_dimm_addr,
1151                          unsigned long num_dimm_banks)
1152 {
1153         unsigned long codt;
1154         unsigned long modt0 = 0;
1155         unsigned long modt1 = 0;
1156         unsigned long modt2 = 0;
1157         unsigned long modt3 = 0;
1158         unsigned char dimm_num;
1159         unsigned char dimm_rank;
1160         unsigned char total_rank = 0;
1161         unsigned char total_dimm = 0;
1162         unsigned char dimm_type = 0;
1163         unsigned char firstSlot = 0;
1164
1165         /*------------------------------------------------------------------
1166          * Set the SDRAM Controller On Die Termination Register
1167          *-----------------------------------------------------------------*/
1168         mfsdram(SDRAM_CODT, codt);
1169         codt &= ~(SDRAM_CODT_DQS_SINGLE_END | SDRAM_CODT_CKSE_SINGLE_END);
1170         codt |= SDRAM_CODT_IO_NMODE;
1171
1172         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1173                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1174                         dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1175                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1176                                 dimm_rank = (dimm_rank & 0x0F) + 1;
1177                                 dimm_type = SDRAM_DDR2;
1178                         } else {
1179                                 dimm_rank = dimm_rank & 0x0F;
1180                                 dimm_type = SDRAM_DDR1;
1181                         }
1182
1183                         total_rank += dimm_rank;
1184                         total_dimm++;
1185                         if ((dimm_num == 0) && (total_dimm == 1))
1186                                 firstSlot = TRUE;
1187                         else
1188                                 firstSlot = FALSE;
1189                 }
1190         }
1191         if (dimm_type == SDRAM_DDR2) {
1192                 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1193                 if ((total_dimm == 1) && (firstSlot == TRUE)) {
1194                         if (total_rank == 1) {  /* PUUU */
1195                                 codt |= CALC_ODT_R(0);
1196                                 modt0 = CALC_ODT_W(0);
1197                                 modt1 = 0x00000000;
1198                                 modt2 = 0x00000000;
1199                                 modt3 = 0x00000000;
1200                         }
1201                         if (total_rank == 2) {  /* PPUU */
1202                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
1203                                 modt0 = CALC_ODT_W(0) | CALC_ODT_W(1);
1204                                 modt1 = 0x00000000;
1205                                 modt2 = 0x00000000;
1206                                 modt3 = 0x00000000;
1207                         }
1208                 } else if ((total_dimm == 1) && (firstSlot != TRUE)) {
1209                         if (total_rank == 1) {  /* UUPU */
1210                                 codt |= CALC_ODT_R(2);
1211                                 modt0 = 0x00000000;
1212                                 modt1 = 0x00000000;
1213                                 modt2 = CALC_ODT_W(2);
1214                                 modt3 = 0x00000000;
1215                         }
1216                         if (total_rank == 2) {  /* UUPP */
1217                                 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1218                                 modt0 = 0x00000000;
1219                                 modt1 = 0x00000000;
1220                                 modt2 = CALC_ODT_W(2) | CALC_ODT_W(3);
1221                                 modt3 = 0x00000000;
1222                         }
1223                 }
1224                 if (total_dimm == 2) {
1225                         if (total_rank == 2) {  /* PUPU */
1226                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1227                                 modt0 = CALC_ODT_RW(2);
1228                                 modt1 = 0x00000000;
1229                                 modt2 = CALC_ODT_RW(0);
1230                                 modt3 = 0x00000000;
1231                         }
1232                         if (total_rank == 4) {  /* PPPP */
1233                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
1234                                         CALC_ODT_R(2) | CALC_ODT_R(3);
1235                                 modt0 = CALC_ODT_RW(2) | CALC_ODT_RW(3);
1236                                 modt1 = 0x00000000;
1237                                 modt2 = CALC_ODT_RW(0) | CALC_ODT_RW(1);
1238                                 modt3 = 0x00000000;
1239                         }
1240                 }
1241         } else {
1242                 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1243                 modt0 = 0x00000000;
1244                 modt1 = 0x00000000;
1245                 modt2 = 0x00000000;
1246                 modt3 = 0x00000000;
1247
1248                 if (total_dimm == 1) {
1249                         if (total_rank == 1)
1250                                 codt |= 0x00800000;
1251                         if (total_rank == 2)
1252                                 codt |= 0x02800000;
1253                 }
1254                 if (total_dimm == 2) {
1255                         if (total_rank == 2)
1256                                 codt |= 0x08800000;
1257                         if (total_rank == 4)
1258                                 codt |= 0x2a800000;
1259                 }
1260         }
1261
1262         debug("nb of dimm %d\n", total_dimm);
1263         debug("nb of rank %d\n", total_rank);
1264         if (total_dimm == 1)
1265                 debug("dimm in slot %d\n", firstSlot);
1266
1267         mtsdram(SDRAM_CODT, codt);
1268         mtsdram(SDRAM_MODT0, modt0);
1269         mtsdram(SDRAM_MODT1, modt1);
1270         mtsdram(SDRAM_MODT2, modt2);
1271         mtsdram(SDRAM_MODT3, modt3);
1272 }
1273
1274 /*-----------------------------------------------------------------------------+
1275  * program_initplr.
1276  *-----------------------------------------------------------------------------*/
1277 static void program_initplr(unsigned long *dimm_populated,
1278                             unsigned char *iic0_dimm_addr,
1279                             unsigned long num_dimm_banks,
1280                             ddr_cas_id_t selected_cas,
1281                             int write_recovery)
1282 {
1283         u32 cas = 0;
1284         u32 odt = 0;
1285         u32 ods = 0;
1286         u32 mr;
1287         u32 wr;
1288         u32 emr;
1289         u32 emr2;
1290         u32 emr3;
1291         int dimm_num;
1292         int total_dimm = 0;
1293
1294         /******************************************************
1295          ** Assumption: if more than one DIMM, all DIMMs are the same
1296          **             as already checked in check_memory_type
1297          ******************************************************/
1298
1299         if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1300                 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1301                 mtsdram(SDRAM_INITPLR1, 0x81900400);
1302                 mtsdram(SDRAM_INITPLR2, 0x81810000);
1303                 mtsdram(SDRAM_INITPLR3, 0xff800162);
1304                 mtsdram(SDRAM_INITPLR4, 0x81900400);
1305                 mtsdram(SDRAM_INITPLR5, 0x86080000);
1306                 mtsdram(SDRAM_INITPLR6, 0x86080000);
1307                 mtsdram(SDRAM_INITPLR7, 0x81000062);
1308         } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1309                 switch (selected_cas) {
1310                 case DDR_CAS_3:
1311                         cas = 3 << 4;
1312                         break;
1313                 case DDR_CAS_4:
1314                         cas = 4 << 4;
1315                         break;
1316                 case DDR_CAS_5:
1317                         cas = 5 << 4;
1318                         break;
1319                 default:
1320                         printf("ERROR: ucode error on selected_cas value %d", selected_cas);
1321                         spd_ddr_init_hang ();
1322                         break;
1323                 }
1324
1325 #if 0
1326                 /*
1327                  * ToDo - Still a problem with the write recovery:
1328                  * On the Corsair CM2X512-5400C4 module, setting write recovery
1329                  * in the INITPLR reg to the value calculated in program_mode()
1330                  * results in not correctly working DDR2 memory (crash after
1331                  * relocation).
1332                  *
1333                  * So for now, set the write recovery to 3. This seems to work
1334                  * on the Corair module too.
1335                  *
1336                  * 2007-03-01, sr
1337                  */
1338                 switch (write_recovery) {
1339                 case 3:
1340                         wr = WRITE_RECOV_3;
1341                         break;
1342                 case 4:
1343                         wr = WRITE_RECOV_4;
1344                         break;
1345                 case 5:
1346                         wr = WRITE_RECOV_5;
1347                         break;
1348                 case 6:
1349                         wr = WRITE_RECOV_6;
1350                         break;
1351                 default:
1352                         printf("ERROR: write recovery not support (%d)", write_recovery);
1353                         spd_ddr_init_hang ();
1354                         break;
1355                 }
1356 #else
1357                 wr = WRITE_RECOV_3; /* test-only, see description above */
1358 #endif
1359
1360                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1361                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1362                                 total_dimm++;
1363                 if (total_dimm == 1) {
1364                         odt = ODT_150_OHM;
1365                         ods = ODS_FULL;
1366                 } else if (total_dimm == 2) {
1367                         odt = ODT_75_OHM;
1368                         ods = ODS_REDUCED;
1369                 } else {
1370                         printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
1371                         spd_ddr_init_hang ();
1372                 }
1373
1374                 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1375                 emr = CMD_EMR | SELECT_EMR | odt | ods;
1376                 emr2 = CMD_EMR | SELECT_EMR2;
1377                 emr3 = CMD_EMR | SELECT_EMR3;
1378                 /* NOP - Wait 106 MemClk cycles */
1379                 mtsdram(SDRAM_INITPLR0, SDRAM_INITPLR_ENABLE | CMD_NOP |
1380                                         SDRAM_INITPLR_IMWT_ENCODE(106));
1381                 udelay(1000);
1382                 /* precharge 4 MemClk cycles */
1383                 mtsdram(SDRAM_INITPLR1, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1384                                         SDRAM_INITPLR_IMWT_ENCODE(4));
1385                 /* EMR2 - Wait tMRD (2 MemClk cycles) */
1386                 mtsdram(SDRAM_INITPLR2, SDRAM_INITPLR_ENABLE | emr2 |
1387                                         SDRAM_INITPLR_IMWT_ENCODE(2));
1388                 /* EMR3 - Wait tMRD (2 MemClk cycles) */
1389                 mtsdram(SDRAM_INITPLR3, SDRAM_INITPLR_ENABLE | emr3 |
1390                                         SDRAM_INITPLR_IMWT_ENCODE(2));
1391                 /* EMR DLL ENABLE - Wait tMRD (2 MemClk cycles) */
1392                 mtsdram(SDRAM_INITPLR4, SDRAM_INITPLR_ENABLE | emr |
1393                                         SDRAM_INITPLR_IMWT_ENCODE(2));
1394                 /* MR w/ DLL reset - 200 cycle wait for DLL reset */
1395                 mtsdram(SDRAM_INITPLR5, SDRAM_INITPLR_ENABLE | mr | DLL_RESET |
1396                                         SDRAM_INITPLR_IMWT_ENCODE(200));
1397                 udelay(1000);
1398                 /* precharge 4 MemClk cycles */
1399                 mtsdram(SDRAM_INITPLR6, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1400                                         SDRAM_INITPLR_IMWT_ENCODE(4));
1401                 /* Refresh 25 MemClk cycles */
1402                 mtsdram(SDRAM_INITPLR7, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1403                                         SDRAM_INITPLR_IMWT_ENCODE(25));
1404                 /* Refresh 25 MemClk cycles */
1405                 mtsdram(SDRAM_INITPLR8, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1406                                         SDRAM_INITPLR_IMWT_ENCODE(25));
1407                 /* Refresh 25 MemClk cycles */
1408                 mtsdram(SDRAM_INITPLR9, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1409                                         SDRAM_INITPLR_IMWT_ENCODE(25));
1410                 /* Refresh 25 MemClk cycles */
1411                 mtsdram(SDRAM_INITPLR10, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1412                                          SDRAM_INITPLR_IMWT_ENCODE(25));
1413                 /* MR w/o DLL reset - Wait tMRD (2 MemClk cycles) */
1414                 mtsdram(SDRAM_INITPLR11, SDRAM_INITPLR_ENABLE | mr |
1415                                          SDRAM_INITPLR_IMWT_ENCODE(2));
1416                 /* EMR OCD Default - Wait tMRD (2 MemClk cycles) */
1417                 mtsdram(SDRAM_INITPLR12, SDRAM_INITPLR_ENABLE | OCD_CALIB_DEF |
1418                                          SDRAM_INITPLR_IMWT_ENCODE(2) | emr);
1419                 /* EMR OCD Exit */
1420                 mtsdram(SDRAM_INITPLR13, SDRAM_INITPLR_ENABLE | emr |
1421                                          SDRAM_INITPLR_IMWT_ENCODE(2));
1422         } else {
1423                 printf("ERROR: ucode error as unknown DDR type in program_initplr");
1424                 spd_ddr_init_hang ();
1425         }
1426 }
1427
1428 /*------------------------------------------------------------------
1429  * This routine programs the SDRAM_MMODE register.
1430  * the selected_cas is an output parameter, that will be passed
1431  * by caller to call the above program_initplr( )
1432  *-----------------------------------------------------------------*/
1433 static void program_mode(unsigned long *dimm_populated,
1434                          unsigned char *iic0_dimm_addr,
1435                          unsigned long num_dimm_banks,
1436                          ddr_cas_id_t *selected_cas,
1437                          int *write_recovery)
1438 {
1439         unsigned long dimm_num;
1440         unsigned long sdram_ddr1;
1441         unsigned long t_wr_ns;
1442         unsigned long t_wr_clk;
1443         unsigned long cas_bit;
1444         unsigned long cas_index;
1445         unsigned long sdram_freq;
1446         unsigned long ddr_check;
1447         unsigned long mmode;
1448         unsigned long tcyc_reg;
1449         unsigned long cycle_2_0_clk;
1450         unsigned long cycle_2_5_clk;
1451         unsigned long cycle_3_0_clk;
1452         unsigned long cycle_4_0_clk;
1453         unsigned long cycle_5_0_clk;
1454         unsigned long max_2_0_tcyc_ns_x_100;
1455         unsigned long max_2_5_tcyc_ns_x_100;
1456         unsigned long max_3_0_tcyc_ns_x_100;
1457         unsigned long max_4_0_tcyc_ns_x_100;
1458         unsigned long max_5_0_tcyc_ns_x_100;
1459         unsigned long cycle_time_ns_x_100[3];
1460         PPC4xx_SYS_INFO board_cfg;
1461         unsigned char cas_2_0_available;
1462         unsigned char cas_2_5_available;
1463         unsigned char cas_3_0_available;
1464         unsigned char cas_4_0_available;
1465         unsigned char cas_5_0_available;
1466         unsigned long sdr_ddrpll;
1467
1468         /*------------------------------------------------------------------
1469          * Get the board configuration info.
1470          *-----------------------------------------------------------------*/
1471         get_sys_info(&board_cfg);
1472
1473         mfsdr(SDR0_DDR0, sdr_ddrpll);
1474         sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
1475         debug("sdram_freq=%lu\n", sdram_freq);
1476
1477         /*------------------------------------------------------------------
1478          * Handle the timing.  We need to find the worst case timing of all
1479          * the dimm modules installed.
1480          *-----------------------------------------------------------------*/
1481         t_wr_ns = 0;
1482         cas_2_0_available = TRUE;
1483         cas_2_5_available = TRUE;
1484         cas_3_0_available = TRUE;
1485         cas_4_0_available = TRUE;
1486         cas_5_0_available = TRUE;
1487         max_2_0_tcyc_ns_x_100 = 10;
1488         max_2_5_tcyc_ns_x_100 = 10;
1489         max_3_0_tcyc_ns_x_100 = 10;
1490         max_4_0_tcyc_ns_x_100 = 10;
1491         max_5_0_tcyc_ns_x_100 = 10;
1492         sdram_ddr1 = TRUE;
1493
1494         /* loop through all the DIMM slots on the board */
1495         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1496                 /* If a dimm is installed in a particular slot ... */
1497                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1498                         if (dimm_populated[dimm_num] == SDRAM_DDR1)
1499                                 sdram_ddr1 = TRUE;
1500                         else
1501                                 sdram_ddr1 = FALSE;
1502
1503                         /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /*  not used in this loop. */
1504                         cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1505                         debug("cas_bit[SPD byte 18]=%02lx\n", cas_bit);
1506
1507                         /* For a particular DIMM, grab the three CAS values it supports */
1508                         for (cas_index = 0; cas_index < 3; cas_index++) {
1509                                 switch (cas_index) {
1510                                 case 0:
1511                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1512                                         break;
1513                                 case 1:
1514                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1515                                         break;
1516                                 default:
1517                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1518                                         break;
1519                                 }
1520
1521                                 if ((tcyc_reg & 0x0F) >= 10) {
1522                                         if ((tcyc_reg & 0x0F) == 0x0D) {
1523                                                 /* Convert from hex to decimal */
1524                                                 cycle_time_ns_x_100[cas_index] =
1525                                                         (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
1526                                         } else {
1527                                                 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1528                                                        "in slot %d\n", (unsigned int)dimm_num);
1529                                                 spd_ddr_init_hang ();
1530                                         }
1531                                 } else {
1532                                         /* Convert from hex to decimal */
1533                                         cycle_time_ns_x_100[cas_index] =
1534                                                 (((tcyc_reg & 0xF0) >> 4) * 100) +
1535                                                 ((tcyc_reg & 0x0F)*10);
1536                                 }
1537                                 debug("cas_index=%lu: cycle_time_ns_x_100=%lu\n", cas_index,
1538                                       cycle_time_ns_x_100[cas_index]);
1539                         }
1540
1541                         /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1542                         /* supported for a particular DIMM. */
1543                         cas_index = 0;
1544
1545                         if (sdram_ddr1) {
1546                                 /*
1547                                  * DDR devices use the following bitmask for CAS latency:
1548                                  *  Bit   7    6    5    4    3    2    1    0
1549                                  *       TBD  4.0  3.5  3.0  2.5  2.0  1.5  1.0
1550                                  */
1551                                 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
1552                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1553                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1554                                                                     cycle_time_ns_x_100[cas_index]);
1555                                         cas_index++;
1556                                 } else {
1557                                         if (cas_index != 0)
1558                                                 cas_index++;
1559                                         cas_4_0_available = FALSE;
1560                                 }
1561
1562                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1563                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1564                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1565                                                                     cycle_time_ns_x_100[cas_index]);
1566                                         cas_index++;
1567                                 } else {
1568                                         if (cas_index != 0)
1569                                                 cas_index++;
1570                                         cas_3_0_available = FALSE;
1571                                 }
1572
1573                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1574                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1575                                         max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
1576                                                                     cycle_time_ns_x_100[cas_index]);
1577                                         cas_index++;
1578                                 } else {
1579                                         if (cas_index != 0)
1580                                                 cas_index++;
1581                                         cas_2_5_available = FALSE;
1582                                 }
1583
1584                                 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
1585                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1586                                         max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
1587                                                                     cycle_time_ns_x_100[cas_index]);
1588                                         cas_index++;
1589                                 } else {
1590                                         if (cas_index != 0)
1591                                                 cas_index++;
1592                                         cas_2_0_available = FALSE;
1593                                 }
1594                         } else {
1595                                 /*
1596                                  * DDR2 devices use the following bitmask for CAS latency:
1597                                  *  Bit   7    6    5    4    3    2    1    0
1598                                  *       TBD  6.0  5.0  4.0  3.0  2.0  TBD  TBD
1599                                  */
1600                                 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
1601                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1602                                         max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
1603                                                                     cycle_time_ns_x_100[cas_index]);
1604                                         cas_index++;
1605                                 } else {
1606                                         if (cas_index != 0)
1607                                                 cas_index++;
1608                                         cas_5_0_available = FALSE;
1609                                 }
1610
1611                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1612                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1613                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1614                                                                     cycle_time_ns_x_100[cas_index]);
1615                                         cas_index++;
1616                                 } else {
1617                                         if (cas_index != 0)
1618                                                 cas_index++;
1619                                         cas_4_0_available = FALSE;
1620                                 }
1621
1622                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1623                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1624                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1625                                                                     cycle_time_ns_x_100[cas_index]);
1626                                         cas_index++;
1627                                 } else {
1628                                         if (cas_index != 0)
1629                                                 cas_index++;
1630                                         cas_3_0_available = FALSE;
1631                                 }
1632                         }
1633                 }
1634         }
1635
1636         /*------------------------------------------------------------------
1637          * Set the SDRAM mode, SDRAM_MMODE
1638          *-----------------------------------------------------------------*/
1639         mfsdram(SDRAM_MMODE, mmode);
1640         mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1641
1642         /* add 10 here because of rounding problems */
1643         cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1644         cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1645         cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1646         cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1647         cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
1648         debug("cycle_3_0_clk=%lu\n", cycle_3_0_clk);
1649         debug("cycle_4_0_clk=%lu\n", cycle_4_0_clk);
1650         debug("cycle_5_0_clk=%lu\n", cycle_5_0_clk);
1651
1652         if (sdram_ddr1 == TRUE) { /* DDR1 */
1653                 if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
1654                         mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1655                         *selected_cas = DDR_CAS_2;
1656                 } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
1657                         mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1658                         *selected_cas = DDR_CAS_2_5;
1659                 } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1660                         mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1661                         *selected_cas = DDR_CAS_3;
1662                 } else {
1663                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1664                         printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1665                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1666                         spd_ddr_init_hang ();
1667                 }
1668         } else { /* DDR2 */
1669                 debug("cas_3_0_available=%d\n", cas_3_0_available);
1670                 debug("cas_4_0_available=%d\n", cas_4_0_available);
1671                 debug("cas_5_0_available=%d\n", cas_5_0_available);
1672                 if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1673                         mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1674                         *selected_cas = DDR_CAS_3;
1675                 } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
1676                         mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1677                         *selected_cas = DDR_CAS_4;
1678                 } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
1679                         mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1680                         *selected_cas = DDR_CAS_5;
1681                 } else {
1682                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1683                         printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
1684                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1685                         printf("cas3=%d cas4=%d cas5=%d\n",
1686                                cas_3_0_available, cas_4_0_available, cas_5_0_available);
1687                         printf("sdram_freq=%lu cycle3=%lu cycle4=%lu cycle5=%lu\n\n",
1688                                sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
1689                         spd_ddr_init_hang ();
1690                 }
1691         }
1692
1693         if (sdram_ddr1 == TRUE)
1694                 mmode |= SDRAM_MMODE_WR_DDR1;
1695         else {
1696
1697                 /* loop through all the DIMM slots on the board */
1698                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1699                         /* If a dimm is installed in a particular slot ... */
1700                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1701                                 t_wr_ns = max(t_wr_ns,
1702                                               spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1703                 }
1704
1705                 /*
1706                  * convert from nanoseconds to ddr clocks
1707                  * round up if necessary
1708                  */
1709                 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1710                 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1711                 if (sdram_freq != ddr_check)
1712                         t_wr_clk++;
1713
1714                 switch (t_wr_clk) {
1715                 case 0:
1716                 case 1:
1717                 case 2:
1718                 case 3:
1719                         mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1720                         break;
1721                 case 4:
1722                         mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1723                         break;
1724                 case 5:
1725                         mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1726                         break;
1727                 default:
1728                         mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1729                         break;
1730                 }
1731                 *write_recovery = t_wr_clk;
1732         }
1733
1734         debug("CAS latency = %d\n", *selected_cas);
1735         debug("Write recovery = %d\n", *write_recovery);
1736
1737         mtsdram(SDRAM_MMODE, mmode);
1738 }
1739
1740 /*-----------------------------------------------------------------------------+
1741  * program_rtr.
1742  *-----------------------------------------------------------------------------*/
1743 static void program_rtr(unsigned long *dimm_populated,
1744                         unsigned char *iic0_dimm_addr,
1745                         unsigned long num_dimm_banks)
1746 {
1747         PPC4xx_SYS_INFO board_cfg;
1748         unsigned long max_refresh_rate;
1749         unsigned long dimm_num;
1750         unsigned long refresh_rate_type;
1751         unsigned long refresh_rate;
1752         unsigned long rint;
1753         unsigned long sdram_freq;
1754         unsigned long sdr_ddrpll;
1755         unsigned long val;
1756
1757         /*------------------------------------------------------------------
1758          * Get the board configuration info.
1759          *-----------------------------------------------------------------*/
1760         get_sys_info(&board_cfg);
1761
1762         /*------------------------------------------------------------------
1763          * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1764          *-----------------------------------------------------------------*/
1765         mfsdr(SDR0_DDR0, sdr_ddrpll);
1766         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1767
1768         max_refresh_rate = 0;
1769         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1770                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1771
1772                         refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1773                         refresh_rate_type &= 0x7F;
1774                         switch (refresh_rate_type) {
1775                         case 0:
1776                                 refresh_rate =  15625;
1777                                 break;
1778                         case 1:
1779                                 refresh_rate =   3906;
1780                                 break;
1781                         case 2:
1782                                 refresh_rate =   7812;
1783                                 break;
1784                         case 3:
1785                                 refresh_rate =  31250;
1786                                 break;
1787                         case 4:
1788                                 refresh_rate =  62500;
1789                                 break;
1790                         case 5:
1791                                 refresh_rate = 125000;
1792                                 break;
1793                         default:
1794                                 refresh_rate = 0;
1795                                 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1796                                        (unsigned int)dimm_num);
1797                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1798                                 spd_ddr_init_hang ();
1799                                 break;
1800                         }
1801
1802                         max_refresh_rate = max(max_refresh_rate, refresh_rate);
1803                 }
1804         }
1805
1806         rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1807         mfsdram(SDRAM_RTR, val);
1808         mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1809                 (SDRAM_RTR_RINT_ENCODE(rint)));
1810 }
1811
1812 /*------------------------------------------------------------------
1813  * This routine programs the SDRAM_TRx registers.
1814  *-----------------------------------------------------------------*/
1815 static void program_tr(unsigned long *dimm_populated,
1816                        unsigned char *iic0_dimm_addr,
1817                        unsigned long num_dimm_banks)
1818 {
1819         unsigned long dimm_num;
1820         unsigned long sdram_ddr1;
1821         unsigned long t_rp_ns;
1822         unsigned long t_rcd_ns;
1823         unsigned long t_rrd_ns;
1824         unsigned long t_ras_ns;
1825         unsigned long t_rc_ns;
1826         unsigned long t_rfc_ns;
1827         unsigned long t_wpc_ns;
1828         unsigned long t_wtr_ns;
1829         unsigned long t_rpc_ns;
1830         unsigned long t_rp_clk;
1831         unsigned long t_rcd_clk;
1832         unsigned long t_rrd_clk;
1833         unsigned long t_ras_clk;
1834         unsigned long t_rc_clk;
1835         unsigned long t_rfc_clk;
1836         unsigned long t_wpc_clk;
1837         unsigned long t_wtr_clk;
1838         unsigned long t_rpc_clk;
1839         unsigned long sdtr1, sdtr2, sdtr3;
1840         unsigned long ddr_check;
1841         unsigned long sdram_freq;
1842         unsigned long sdr_ddrpll;
1843
1844         PPC4xx_SYS_INFO board_cfg;
1845
1846         /*------------------------------------------------------------------
1847          * Get the board configuration info.
1848          *-----------------------------------------------------------------*/
1849         get_sys_info(&board_cfg);
1850
1851         mfsdr(SDR0_DDR0, sdr_ddrpll);
1852         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1853
1854         /*------------------------------------------------------------------
1855          * Handle the timing.  We need to find the worst case timing of all
1856          * the dimm modules installed.
1857          *-----------------------------------------------------------------*/
1858         t_rp_ns = 0;
1859         t_rrd_ns = 0;
1860         t_rcd_ns = 0;
1861         t_ras_ns = 0;
1862         t_rc_ns = 0;
1863         t_rfc_ns = 0;
1864         t_wpc_ns = 0;
1865         t_wtr_ns = 0;
1866         t_rpc_ns = 0;
1867         sdram_ddr1 = TRUE;
1868
1869         /* loop through all the DIMM slots on the board */
1870         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1871                 /* If a dimm is installed in a particular slot ... */
1872                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1873                         if (dimm_populated[dimm_num] == SDRAM_DDR2)
1874                                 sdram_ddr1 = TRUE;
1875                         else
1876                                 sdram_ddr1 = FALSE;
1877
1878                         t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1879                         t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1880                         t_rp_ns  = max(t_rp_ns,  spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1881                         t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1882                         t_rc_ns  = max(t_rc_ns,  spd_read(iic0_dimm_addr[dimm_num], 41));
1883                         t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1884                 }
1885         }
1886
1887         /*------------------------------------------------------------------
1888          * Set the SDRAM Timing Reg 1, SDRAM_TR1
1889          *-----------------------------------------------------------------*/
1890         mfsdram(SDRAM_SDTR1, sdtr1);
1891         sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1892                    SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1893
1894         /* default values */
1895         sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1896         sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1897
1898         /* normal operations */
1899         sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1900         sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1901
1902         mtsdram(SDRAM_SDTR1, sdtr1);
1903
1904         /*------------------------------------------------------------------
1905          * Set the SDRAM Timing Reg 2, SDRAM_TR2
1906          *-----------------------------------------------------------------*/
1907         mfsdram(SDRAM_SDTR2, sdtr2);
1908         sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK  | SDRAM_SDTR2_WTR_MASK |
1909                    SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1910                    SDRAM_SDTR2_RPC_MASK  | SDRAM_SDTR2_RP_MASK  |
1911                    SDRAM_SDTR2_RRD_MASK);
1912
1913         /*
1914          * convert t_rcd from nanoseconds to ddr clocks
1915          * round up if necessary
1916          */
1917         t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1918         ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1919         if (sdram_freq != ddr_check)
1920                 t_rcd_clk++;
1921
1922         switch (t_rcd_clk) {
1923         case 0:
1924         case 1:
1925                 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1926                 break;
1927         case 2:
1928                 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1929                 break;
1930         case 3:
1931                 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1932                 break;
1933         case 4:
1934                 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1935                 break;
1936         default:
1937                 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1938                 break;
1939         }
1940
1941         if (sdram_ddr1 == TRUE) { /* DDR1 */
1942                 if (sdram_freq < 200000000) {
1943                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1944                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1945                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1946                 } else {
1947                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1948                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1949                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1950                 }
1951         } else { /* DDR2 */
1952                 /* loop through all the DIMM slots on the board */
1953                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1954                         /* If a dimm is installed in a particular slot ... */
1955                         if (dimm_populated[dimm_num] != SDRAM_NONE) {
1956                                 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1957                                 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1958                                 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1959                         }
1960                 }
1961
1962                 /*
1963                  * convert from nanoseconds to ddr clocks
1964                  * round up if necessary
1965                  */
1966                 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1967                 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1968                 if (sdram_freq != ddr_check)
1969                         t_wpc_clk++;
1970
1971                 switch (t_wpc_clk) {
1972                 case 0:
1973                 case 1:
1974                 case 2:
1975                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1976                         break;
1977                 case 3:
1978                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1979                         break;
1980                 case 4:
1981                         sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1982                         break;
1983                 case 5:
1984                         sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1985                         break;
1986                 default:
1987                         sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1988                         break;
1989                 }
1990
1991                 /*
1992                  * convert from nanoseconds to ddr clocks
1993                  * round up if necessary
1994                  */
1995                 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1996                 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1997                 if (sdram_freq != ddr_check)
1998                         t_wtr_clk++;
1999
2000                 switch (t_wtr_clk) {
2001                 case 0:
2002                 case 1:
2003                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
2004                         break;
2005                 case 2:
2006                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
2007                         break;
2008                 case 3:
2009                         sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
2010                         break;
2011                 default:
2012                         sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
2013                         break;
2014                 }
2015
2016                 /*
2017                  * convert from nanoseconds to ddr clocks
2018                  * round up if necessary
2019                  */
2020                 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
2021                 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
2022                 if (sdram_freq != ddr_check)
2023                         t_rpc_clk++;
2024
2025                 switch (t_rpc_clk) {
2026                 case 0:
2027                 case 1:
2028                 case 2:
2029                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
2030                         break;
2031                 case 3:
2032                         sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
2033                         break;
2034                 default:
2035                         sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
2036                         break;
2037                 }
2038         }
2039
2040         /* default value */
2041         sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
2042
2043         /*
2044          * convert t_rrd from nanoseconds to ddr clocks
2045          * round up if necessary
2046          */
2047         t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
2048         ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
2049         if (sdram_freq != ddr_check)
2050                 t_rrd_clk++;
2051
2052         if (t_rrd_clk == 3)
2053                 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
2054         else
2055                 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
2056
2057         /*
2058          * convert t_rp from nanoseconds to ddr clocks
2059          * round up if necessary
2060          */
2061         t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
2062         ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
2063         if (sdram_freq != ddr_check)
2064                 t_rp_clk++;
2065
2066         switch (t_rp_clk) {
2067         case 0:
2068         case 1:
2069         case 2:
2070         case 3:
2071                 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
2072                 break;
2073         case 4:
2074                 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
2075                 break;
2076         case 5:
2077                 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
2078                 break;
2079         case 6:
2080                 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
2081                 break;
2082         default:
2083                 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
2084                 break;
2085         }
2086
2087         mtsdram(SDRAM_SDTR2, sdtr2);
2088
2089         /*------------------------------------------------------------------
2090          * Set the SDRAM Timing Reg 3, SDRAM_TR3
2091          *-----------------------------------------------------------------*/
2092         mfsdram(SDRAM_SDTR3, sdtr3);
2093         sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK  | SDRAM_SDTR3_RC_MASK |
2094                    SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
2095
2096         /*
2097          * convert t_ras from nanoseconds to ddr clocks
2098          * round up if necessary
2099          */
2100         t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
2101         ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
2102         if (sdram_freq != ddr_check)
2103                 t_ras_clk++;
2104
2105         sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
2106
2107         /*
2108          * convert t_rc from nanoseconds to ddr clocks
2109          * round up if necessary
2110          */
2111         t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
2112         ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
2113         if (sdram_freq != ddr_check)
2114                 t_rc_clk++;
2115
2116         sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
2117
2118         /* default xcs value */
2119         sdtr3 |= SDRAM_SDTR3_XCS;
2120
2121         /*
2122          * convert t_rfc from nanoseconds to ddr clocks
2123          * round up if necessary
2124          */
2125         t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
2126         ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
2127         if (sdram_freq != ddr_check)
2128                 t_rfc_clk++;
2129
2130         sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
2131
2132         mtsdram(SDRAM_SDTR3, sdtr3);
2133 }
2134
2135 /*-----------------------------------------------------------------------------+
2136  * program_bxcf.
2137  *-----------------------------------------------------------------------------*/
2138 static void program_bxcf(unsigned long *dimm_populated,
2139                          unsigned char *iic0_dimm_addr,
2140                          unsigned long num_dimm_banks)
2141 {
2142         unsigned long dimm_num;
2143         unsigned long num_col_addr;
2144         unsigned long num_ranks;
2145         unsigned long num_banks;
2146         unsigned long mode;
2147         unsigned long ind_rank;
2148         unsigned long ind;
2149         unsigned long ind_bank;
2150         unsigned long bank_0_populated;
2151
2152         /*------------------------------------------------------------------
2153          * Set the BxCF regs.  First, wipe out the bank config registers.
2154          *-----------------------------------------------------------------*/
2155         mtsdram(SDRAM_MB0CF, 0x00000000);
2156         mtsdram(SDRAM_MB1CF, 0x00000000);
2157         mtsdram(SDRAM_MB2CF, 0x00000000);
2158         mtsdram(SDRAM_MB3CF, 0x00000000);
2159
2160         mode = SDRAM_BXCF_M_BE_ENABLE;
2161
2162         bank_0_populated = 0;
2163
2164         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2165                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2166                         num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
2167                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2168                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2169                                 num_ranks = (num_ranks & 0x0F) +1;
2170                         else
2171                                 num_ranks = num_ranks & 0x0F;
2172
2173                         num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
2174
2175                         for (ind_bank = 0; ind_bank < 2; ind_bank++) {
2176                                 if (num_banks == 4)
2177                                         ind = 0;
2178                                 else
2179                                         ind = 5 << 8;
2180                                 switch (num_col_addr) {
2181                                 case 0x08:
2182                                         mode |= (SDRAM_BXCF_M_AM_0 + ind);
2183                                         break;
2184                                 case 0x09:
2185                                         mode |= (SDRAM_BXCF_M_AM_1 + ind);
2186                                         break;
2187                                 case 0x0A:
2188                                         mode |= (SDRAM_BXCF_M_AM_2 + ind);
2189                                         break;
2190                                 case 0x0B:
2191                                         mode |= (SDRAM_BXCF_M_AM_3 + ind);
2192                                         break;
2193                                 case 0x0C:
2194                                         mode |= (SDRAM_BXCF_M_AM_4 + ind);
2195                                         break;
2196                                 default:
2197                                         printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2198                                                (unsigned int)dimm_num);
2199                                         printf("ERROR: Unsupported value for number of "
2200                                                "column addresses: %d.\n", (unsigned int)num_col_addr);
2201                                         printf("Replace the DIMM module with a supported DIMM.\n\n");
2202                                         spd_ddr_init_hang ();
2203                                 }
2204                         }
2205
2206                         if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2207                                 bank_0_populated = 1;
2208
2209                         for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
2210                                 mtsdram(SDRAM_MB0CF +
2211                                         ((dimm_num + bank_0_populated + ind_rank) << 2),
2212                                         mode);
2213                         }
2214                 }
2215         }
2216 }
2217
2218 /*------------------------------------------------------------------
2219  * program memory queue.
2220  *-----------------------------------------------------------------*/
2221 static void program_memory_queue(unsigned long *dimm_populated,
2222                                  unsigned char *iic0_dimm_addr,
2223                                  unsigned long num_dimm_banks)
2224 {
2225         unsigned long dimm_num;
2226         phys_size_t rank_base_addr;
2227         unsigned long rank_reg;
2228         phys_size_t rank_size_bytes;
2229         unsigned long rank_size_id;
2230         unsigned long num_ranks;
2231         unsigned long baseadd_size;
2232         unsigned long i;
2233         unsigned long bank_0_populated = 0;
2234         phys_size_t total_size = 0;
2235
2236         /*------------------------------------------------------------------
2237          * Reset the rank_base_address.
2238          *-----------------------------------------------------------------*/
2239         rank_reg   = SDRAM_R0BAS;
2240
2241         rank_base_addr = 0x00000000;
2242
2243         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2244                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2245                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2246                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2247                                 num_ranks = (num_ranks & 0x0F) + 1;
2248                         else
2249                                 num_ranks = num_ranks & 0x0F;
2250
2251                         rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2252
2253                         /*------------------------------------------------------------------
2254                          * Set the sizes
2255                          *-----------------------------------------------------------------*/
2256                         baseadd_size = 0;
2257                         switch (rank_size_id) {
2258                         case 0x01:
2259                                 baseadd_size |= SDRAM_RXBAS_SDSZ_1024;
2260                                 total_size = 1024;
2261                                 break;
2262                         case 0x02:
2263                                 baseadd_size |= SDRAM_RXBAS_SDSZ_2048;
2264                                 total_size = 2048;
2265                                 break;
2266                         case 0x04:
2267                                 baseadd_size |= SDRAM_RXBAS_SDSZ_4096;
2268                                 total_size = 4096;
2269                                 break;
2270                         case 0x08:
2271                                 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
2272                                 total_size = 32;
2273                                 break;
2274                         case 0x10:
2275                                 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
2276                                 total_size = 64;
2277                                 break;
2278                         case 0x20:
2279                                 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
2280                                 total_size = 128;
2281                                 break;
2282                         case 0x40:
2283                                 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
2284                                 total_size = 256;
2285                                 break;
2286                         case 0x80:
2287                                 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
2288                                 total_size = 512;
2289                                 break;
2290                         default:
2291                                 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2292                                        (unsigned int)dimm_num);
2293                                 printf("ERROR: Unsupported value for the banksize: %d.\n",
2294                                        (unsigned int)rank_size_id);
2295                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
2296                                 spd_ddr_init_hang ();
2297                         }
2298                         rank_size_bytes = total_size << 20;
2299
2300                         if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2301                                 bank_0_populated = 1;
2302
2303                         for (i = 0; i < num_ranks; i++) {
2304                                 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
2305                                           (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2306                                            baseadd_size));
2307                                 rank_base_addr += rank_size_bytes;
2308                         }
2309                 }
2310         }
2311
2312 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
2313     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
2314     defined(CONFIG_460SX)
2315         /*
2316          * Enable high bandwidth access
2317          * This is currently not used, but with this setup
2318          * it is possible to use it later on in e.g. the Linux
2319          * EMAC driver for performance gain.
2320          */
2321         mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
2322         mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
2323
2324         /*
2325          * Set optimal value for Memory Queue HB/LL Configuration registers
2326          */
2327         mtdcr(SDRAM_CONF1HB, (mfdcr(SDRAM_CONF1HB) & ~SDRAM_CONF1HB_MASK) |
2328               SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE |
2329               SDRAM_CONF1HB_RPLM | SDRAM_CONF1HB_WRCL);
2330         mtdcr(SDRAM_CONF1LL, (mfdcr(SDRAM_CONF1LL) & ~SDRAM_CONF1LL_MASK) |
2331               SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE |
2332               SDRAM_CONF1LL_RPLM);
2333         mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
2334 #endif
2335 }
2336
2337 #ifdef CONFIG_DDR_ECC
2338 /*-----------------------------------------------------------------------------+
2339  * program_ecc.
2340  *-----------------------------------------------------------------------------*/
2341 static void program_ecc(unsigned long *dimm_populated,
2342                         unsigned char *iic0_dimm_addr,
2343                         unsigned long num_dimm_banks,
2344                         unsigned long tlb_word2_i_value)
2345 {
2346         unsigned long dimm_num;
2347         unsigned long ecc;
2348
2349         ecc = 0;
2350         /* loop through all the DIMM slots on the board */
2351         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2352                 /* If a dimm is installed in a particular slot ... */
2353                 if (dimm_populated[dimm_num] != SDRAM_NONE)
2354                         ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2355         }
2356         if (ecc == 0)
2357                 return;
2358
2359         do_program_ecc(tlb_word2_i_value);
2360 }
2361 #endif
2362
2363 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
2364 /*-----------------------------------------------------------------------------+
2365  * program_DQS_calibration.
2366  *-----------------------------------------------------------------------------*/
2367 static void program_DQS_calibration(unsigned long *dimm_populated,
2368                                     unsigned char *iic0_dimm_addr,
2369                                     unsigned long num_dimm_banks)
2370 {
2371         unsigned long val;
2372
2373 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2374         mtsdram(SDRAM_RQDC, 0x80000037);
2375         mtsdram(SDRAM_RDCC, 0x40000000);
2376         mtsdram(SDRAM_RFDC, 0x000001DF);
2377
2378         test();
2379 #else
2380         /*------------------------------------------------------------------
2381          * Program RDCC register
2382          * Read sample cycle auto-update enable
2383          *-----------------------------------------------------------------*/
2384
2385         mfsdram(SDRAM_RDCC, val);
2386         mtsdram(SDRAM_RDCC,
2387                 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
2388                 | SDRAM_RDCC_RSAE_ENABLE);
2389
2390         /*------------------------------------------------------------------
2391          * Program RQDC register
2392          * Internal DQS delay mechanism enable
2393          *-----------------------------------------------------------------*/
2394         mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2395
2396         /*------------------------------------------------------------------
2397          * Program RFDC register
2398          * Set Feedback Fractional Oversample
2399          * Auto-detect read sample cycle enable
2400          * Set RFOS to 1/4 of memclk cycle (0x3f)
2401          *-----------------------------------------------------------------*/
2402         mfsdram(SDRAM_RFDC, val);
2403         mtsdram(SDRAM_RFDC,
2404                 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2405                          SDRAM_RFDC_RFFD_MASK))
2406                 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0x3f) |
2407                    SDRAM_RFDC_RFFD_ENCODE(0)));
2408
2409         DQS_calibration_process();
2410 #endif
2411 }
2412
2413 static int short_mem_test(void)
2414 {
2415         u32 *membase;
2416         u32 bxcr_num;
2417         u32 bxcf;
2418         int i;
2419         int j;
2420         phys_size_t base_addr;
2421         u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2422                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2423                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2424                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2425                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2426                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2427                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2428                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2429                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2430                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2431                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2432                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2433                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2434                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2435                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2436                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2437                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2438         int l;
2439
2440         for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2441                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2442
2443                 /* Banks enabled */
2444                 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2445                         /* Bank is enabled */
2446
2447                         /*
2448                          * Only run test on accessable memory (below 2GB)
2449                          */
2450                         base_addr = SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num));
2451                         if (base_addr >= CONFIG_MAX_MEM_MAPPED)
2452                                 continue;
2453
2454                         /*------------------------------------------------------------------
2455                          * Run the short memory test.
2456                          *-----------------------------------------------------------------*/
2457                         membase = (u32 *)(u32)base_addr;
2458
2459                         for (i = 0; i < NUMMEMTESTS; i++) {
2460                                 for (j = 0; j < NUMMEMWORDS; j++) {
2461                                         membase[j] = test[i][j];
2462                                         ppcDcbf((u32)&(membase[j]));
2463                                 }
2464                                 sync();
2465                                 for (l=0; l<NUMLOOPS; l++) {
2466                                         for (j = 0; j < NUMMEMWORDS; j++) {
2467                                                 if (membase[j] != test[i][j]) {
2468                                                         ppcDcbf((u32)&(membase[j]));
2469                                                         return 0;
2470                                                 }
2471                                                 ppcDcbf((u32)&(membase[j]));
2472                                         }
2473                                         sync();
2474                                 }
2475                         }
2476                 }       /* if bank enabled */
2477         }               /* for bxcf_num */
2478
2479         return 1;
2480 }
2481
2482 #ifndef HARD_CODED_DQS
2483 /*-----------------------------------------------------------------------------+
2484  * DQS_calibration_process.
2485  *-----------------------------------------------------------------------------*/
2486 static void DQS_calibration_process(void)
2487 {
2488         unsigned long rfdc_reg;
2489         unsigned long rffd;
2490         unsigned long val;
2491         long rffd_average;
2492         long max_start;
2493         long min_end;
2494         unsigned long begin_rqfd[MAXRANKS];
2495         unsigned long begin_rffd[MAXRANKS];
2496         unsigned long end_rqfd[MAXRANKS];
2497         unsigned long end_rffd[MAXRANKS];
2498         char window_found;
2499         unsigned long dlycal;
2500         unsigned long dly_val;
2501         unsigned long max_pass_length;
2502         unsigned long current_pass_length;
2503         unsigned long current_fail_length;
2504         unsigned long current_start;
2505         long max_end;
2506         unsigned char fail_found;
2507         unsigned char pass_found;
2508 #if !defined(CONFIG_DDR_RQDC_FIXED)
2509         u32 rqdc_reg;
2510         u32 rqfd;
2511         u32 rqfd_start;
2512         u32 rqfd_average;
2513         int loopi = 0;
2514         char str[] = "Auto calibration -";
2515         char slash[] = "\\|/-\\|/-";
2516
2517         /*------------------------------------------------------------------
2518          * Test to determine the best read clock delay tuning bits.
2519          *
2520          * Before the DDR controller can be used, the read clock delay needs to be
2521          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2522          * This value cannot be hardcoded into the program because it changes
2523          * depending on the board's setup and environment.
2524          * To do this, all delay values are tested to see if they
2525          * work or not.  By doing this, you get groups of fails with groups of
2526          * passing values.  The idea is to find the start and end of a passing
2527          * window and take the center of it to use as the read clock delay.
2528          *
2529          * A failure has to be seen first so that when we hit a pass, we know
2530          * that it is truely the start of the window.  If we get passing values
2531          * to start off with, we don't know if we are at the start of the window.
2532          *
2533          * The code assumes that a failure will always be found.
2534          * If a failure is not found, there is no easy way to get the middle
2535          * of the passing window.  I guess we can pretty much pick any value
2536          * but some values will be better than others.  Since the lowest speed
2537          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2538          * from experimentation it is safe to say you will always have a failure.
2539          *-----------------------------------------------------------------*/
2540
2541         /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2542         rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
2543
2544         puts(str);
2545
2546 calibration_loop:
2547         mfsdram(SDRAM_RQDC, rqdc_reg);
2548         mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2549                 SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
2550 #else /* CONFIG_DDR_RQDC_FIXED */
2551         /*
2552          * On Katmai the complete auto-calibration somehow doesn't seem to
2553          * produce the best results, meaning optimal values for RQFD/RFFD.
2554          * This was discovered by GDA using a high bandwidth scope,
2555          * analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
2556          * so now on Katmai "only" RFFD is auto-calibrated.
2557          */
2558         mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
2559 #endif /* CONFIG_DDR_RQDC_FIXED */
2560
2561         max_start = 0;
2562         min_end = 0;
2563         begin_rqfd[0] = 0;
2564         begin_rffd[0] = 0;
2565         begin_rqfd[1] = 0;
2566         begin_rffd[1] = 0;
2567         end_rqfd[0] = 0;
2568         end_rffd[0] = 0;
2569         end_rqfd[1] = 0;
2570         end_rffd[1] = 0;
2571         window_found = FALSE;
2572
2573         max_pass_length = 0;
2574         max_start = 0;
2575         max_end = 0;
2576         current_pass_length = 0;
2577         current_fail_length = 0;
2578         current_start = 0;
2579         window_found = FALSE;
2580         fail_found = FALSE;
2581         pass_found = FALSE;
2582
2583         /*
2584          * get the delay line calibration register value
2585          */
2586         mfsdram(SDRAM_DLCR, dlycal);
2587         dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2588
2589         for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2590                 mfsdram(SDRAM_RFDC, rfdc_reg);
2591                 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2592
2593                 /*------------------------------------------------------------------
2594                  * Set the timing reg for the test.
2595                  *-----------------------------------------------------------------*/
2596                 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2597
2598                 /*------------------------------------------------------------------
2599                  * See if the rffd value passed.
2600                  *-----------------------------------------------------------------*/
2601                 if (short_mem_test()) {
2602                         if (fail_found == TRUE) {
2603                                 pass_found = TRUE;
2604                                 if (current_pass_length == 0)
2605                                         current_start = rffd;
2606
2607                                 current_fail_length = 0;
2608                                 current_pass_length++;
2609
2610                                 if (current_pass_length > max_pass_length) {
2611                                         max_pass_length = current_pass_length;
2612                                         max_start = current_start;
2613                                         max_end = rffd;
2614                                 }
2615                         }
2616                 } else {
2617                         current_pass_length = 0;
2618                         current_fail_length++;
2619
2620                         if (current_fail_length >= (dly_val >> 2)) {
2621                                 if (fail_found == FALSE) {
2622                                         fail_found = TRUE;
2623                                 } else if (pass_found == TRUE) {
2624                                         window_found = TRUE;
2625                                         break;
2626                                 }
2627                         }
2628                 }
2629         }               /* for rffd */
2630
2631         /*------------------------------------------------------------------
2632          * Set the average RFFD value
2633          *-----------------------------------------------------------------*/
2634         rffd_average = ((max_start + max_end) >> 1);
2635
2636         if (rffd_average < 0)
2637                 rffd_average = 0;
2638
2639         if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2640                 rffd_average = SDRAM_RFDC_RFFD_MAX;
2641         /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2642         mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2643
2644 #if !defined(CONFIG_DDR_RQDC_FIXED)
2645         max_pass_length = 0;
2646         max_start = 0;
2647         max_end = 0;
2648         current_pass_length = 0;
2649         current_fail_length = 0;
2650         current_start = 0;
2651         window_found = FALSE;
2652         fail_found = FALSE;
2653         pass_found = FALSE;
2654
2655         for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2656                 mfsdram(SDRAM_RQDC, rqdc_reg);
2657                 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2658
2659                 /*------------------------------------------------------------------
2660                  * Set the timing reg for the test.
2661                  *-----------------------------------------------------------------*/
2662                 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2663
2664                 /*------------------------------------------------------------------
2665                  * See if the rffd value passed.
2666                  *-----------------------------------------------------------------*/
2667                 if (short_mem_test()) {
2668                         if (fail_found == TRUE) {
2669                                 pass_found = TRUE;
2670                                 if (current_pass_length == 0)
2671                                         current_start = rqfd;
2672
2673                                 current_fail_length = 0;
2674                                 current_pass_length++;
2675
2676                                 if (current_pass_length > max_pass_length) {
2677                                         max_pass_length = current_pass_length;
2678                                         max_start = current_start;
2679                                         max_end = rqfd;
2680                                 }
2681                         }
2682                 } else {
2683                         current_pass_length = 0;
2684                         current_fail_length++;
2685
2686                         if (fail_found == FALSE) {
2687                                 fail_found = TRUE;
2688                         } else if (pass_found == TRUE) {
2689                                 window_found = TRUE;
2690                                 break;
2691                         }
2692                 }
2693         }
2694
2695         rqfd_average = ((max_start + max_end) >> 1);
2696
2697         /*------------------------------------------------------------------
2698          * Make sure we found the valid read passing window.  Halt if not
2699          *-----------------------------------------------------------------*/
2700         if (window_found == FALSE) {
2701                 if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
2702                         putc('\b');
2703                         putc(slash[loopi++ % 8]);
2704
2705                         /* try again from with a different RQFD start value */
2706                         rqfd_start++;
2707                         goto calibration_loop;
2708                 }
2709
2710                 printf("\nERROR: Cannot determine a common read delay for the "
2711                        "DIMM(s) installed.\n");
2712                 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2713                 ppc4xx_ibm_ddr2_register_dump();
2714                 spd_ddr_init_hang ();
2715         }
2716
2717         if (rqfd_average < 0)
2718                 rqfd_average = 0;
2719
2720         if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2721                 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2722
2723         mtsdram(SDRAM_RQDC,
2724                 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2725                 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2726
2727         blank_string(strlen(str));
2728 #endif /* CONFIG_DDR_RQDC_FIXED */
2729
2730         mfsdram(SDRAM_DLCR, val);
2731         debug("%s[%d] DLCR: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2732         mfsdram(SDRAM_RQDC, val);
2733         debug("%s[%d] RQDC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2734         mfsdram(SDRAM_RFDC, val);
2735         debug("%s[%d] RFDC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2736         mfsdram(SDRAM_RDCC, val);
2737         debug("%s[%d] RDCC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2738 }
2739 #else /* calibration test with hardvalues */
2740 /*-----------------------------------------------------------------------------+
2741  * DQS_calibration_process.
2742  *-----------------------------------------------------------------------------*/
2743 static void test(void)
2744 {
2745         unsigned long dimm_num;
2746         unsigned long ecc_temp;
2747         unsigned long i, j;
2748         unsigned long *membase;
2749         unsigned long bxcf[MAXRANKS];
2750         unsigned long val;
2751         char window_found;
2752         char begin_found[MAXDIMMS];
2753         char end_found[MAXDIMMS];
2754         char search_end[MAXDIMMS];
2755         unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2756                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2757                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2758                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2759                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2760                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2761                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2762                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2763                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2764                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2765                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2766                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2767                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2768                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2769                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2770                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2771                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2772
2773         /*------------------------------------------------------------------
2774          * Test to determine the best read clock delay tuning bits.
2775          *
2776          * Before the DDR controller can be used, the read clock delay needs to be
2777          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2778          * This value cannot be hardcoded into the program because it changes
2779          * depending on the board's setup and environment.
2780          * To do this, all delay values are tested to see if they
2781          * work or not.  By doing this, you get groups of fails with groups of
2782          * passing values.  The idea is to find the start and end of a passing
2783          * window and take the center of it to use as the read clock delay.
2784          *
2785          * A failure has to be seen first so that when we hit a pass, we know
2786          * that it is truely the start of the window.  If we get passing values
2787          * to start off with, we don't know if we are at the start of the window.
2788          *
2789          * The code assumes that a failure will always be found.
2790          * If a failure is not found, there is no easy way to get the middle
2791          * of the passing window.  I guess we can pretty much pick any value
2792          * but some values will be better than others.  Since the lowest speed
2793          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2794          * from experimentation it is safe to say you will always have a failure.
2795          *-----------------------------------------------------------------*/
2796         mfsdram(SDRAM_MCOPT1, ecc_temp);
2797         ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2798         mfsdram(SDRAM_MCOPT1, val);
2799         mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2800                 SDRAM_MCOPT1_MCHK_NON);
2801
2802         window_found = FALSE;
2803         begin_found[0] = FALSE;
2804         end_found[0] = FALSE;
2805         search_end[0] = FALSE;
2806         begin_found[1] = FALSE;
2807         end_found[1] = FALSE;
2808         search_end[1] = FALSE;
2809
2810         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2811                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2812
2813                 /* Banks enabled */
2814                 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2815
2816                         /* Bank is enabled */
2817                         membase =
2818                                 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2819
2820                         /*------------------------------------------------------------------
2821                          * Run the short memory test.
2822                          *-----------------------------------------------------------------*/
2823                         for (i = 0; i < NUMMEMTESTS; i++) {
2824                                 for (j = 0; j < NUMMEMWORDS; j++) {
2825                                         membase[j] = test[i][j];
2826                                         ppcDcbf((u32)&(membase[j]));
2827                                 }
2828                                 sync();
2829                                 for (j = 0; j < NUMMEMWORDS; j++) {
2830                                         if (membase[j] != test[i][j]) {
2831                                                 ppcDcbf((u32)&(membase[j]));
2832                                                 break;
2833                                         }
2834                                         ppcDcbf((u32)&(membase[j]));
2835                                 }
2836                                 sync();
2837                                 if (j < NUMMEMWORDS)
2838                                         break;
2839                         }
2840
2841                         /*------------------------------------------------------------------
2842                          * See if the rffd value passed.
2843                          *-----------------------------------------------------------------*/
2844                         if (i < NUMMEMTESTS) {
2845                                 if ((end_found[dimm_num] == FALSE) &&
2846                                     (search_end[dimm_num] == TRUE)) {
2847                                         end_found[dimm_num] = TRUE;
2848                                 }
2849                                 if ((end_found[0] == TRUE) &&
2850                                     (end_found[1] == TRUE))
2851                                         break;
2852                         } else {
2853                                 if (begin_found[dimm_num] == FALSE) {
2854                                         begin_found[dimm_num] = TRUE;
2855                                         search_end[dimm_num] = TRUE;
2856                                 }
2857                         }
2858                 } else {
2859                         begin_found[dimm_num] = TRUE;
2860                         end_found[dimm_num] = TRUE;
2861                 }
2862         }
2863
2864         if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
2865                 window_found = TRUE;
2866
2867         /*------------------------------------------------------------------
2868          * Make sure we found the valid read passing window.  Halt if not
2869          *-----------------------------------------------------------------*/
2870         if (window_found == FALSE) {
2871                 printf("ERROR: Cannot determine a common read delay for the "
2872                        "DIMM(s) installed.\n");
2873                 spd_ddr_init_hang ();
2874         }
2875
2876         /*------------------------------------------------------------------
2877          * Restore the ECC variable to what it originally was
2878          *-----------------------------------------------------------------*/
2879         mtsdram(SDRAM_MCOPT1,
2880                 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2881                 | ecc_temp);
2882 }
2883 #endif /* !HARD_CODED_DQS */
2884 #endif /* !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) */
2885
2886 #else /* CONFIG_SPD_EEPROM */
2887
2888 /*-----------------------------------------------------------------------------
2889  * Function:    initdram
2890  * Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller.
2891  *              The configuration is performed using static, compile-
2892  *              time parameters.
2893  *              Configures the PPC405EX(r) and PPC460EX/GT
2894  *---------------------------------------------------------------------------*/
2895 phys_size_t initdram(int board_type)
2896 {
2897         /*
2898          * Only run this SDRAM init code once. For NAND booting
2899          * targets like Kilauea, we call initdram() early from the
2900          * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
2901          * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
2902          * which calls initdram() again. This time the controller
2903          * mustn't be reconfigured again since we're already running
2904          * from SDRAM.
2905          */
2906 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
2907         unsigned long val;
2908
2909 #if defined(CONFIG_440)
2910         mtdcr(SDRAM_R0BAS,      CONFIG_SYS_SDRAM_R0BAS);
2911         mtdcr(SDRAM_R1BAS,      CONFIG_SYS_SDRAM_R1BAS);
2912         mtdcr(SDRAM_R2BAS,      CONFIG_SYS_SDRAM_R2BAS);
2913         mtdcr(SDRAM_R3BAS,      CONFIG_SYS_SDRAM_R3BAS);
2914         mtdcr(SDRAM_PLBADDULL,  CONFIG_SYS_SDRAM_PLBADDULL);    /* MQ0_BAUL */
2915         mtdcr(SDRAM_PLBADDUHB,  CONFIG_SYS_SDRAM_PLBADDUHB);    /* MQ0_BAUH */
2916         mtdcr(SDRAM_CONF1LL,    CONFIG_SYS_SDRAM_CONF1LL);
2917         mtdcr(SDRAM_CONF1HB,    CONFIG_SYS_SDRAM_CONF1HB);
2918         mtdcr(SDRAM_CONFPATHB,  CONFIG_SYS_SDRAM_CONFPATHB);
2919 #endif
2920
2921         /* Set Memory Bank Configuration Registers */
2922
2923         mtsdram(SDRAM_MB0CF, CONFIG_SYS_SDRAM0_MB0CF);
2924         mtsdram(SDRAM_MB1CF, CONFIG_SYS_SDRAM0_MB1CF);
2925         mtsdram(SDRAM_MB2CF, CONFIG_SYS_SDRAM0_MB2CF);
2926         mtsdram(SDRAM_MB3CF, CONFIG_SYS_SDRAM0_MB3CF);
2927
2928         /* Set Memory Clock Timing Register */
2929
2930         mtsdram(SDRAM_CLKTR, CONFIG_SYS_SDRAM0_CLKTR);
2931
2932         /* Set Refresh Time Register */
2933
2934         mtsdram(SDRAM_RTR, CONFIG_SYS_SDRAM0_RTR);
2935
2936         /* Set SDRAM Timing Registers */
2937
2938         mtsdram(SDRAM_SDTR1, CONFIG_SYS_SDRAM0_SDTR1);
2939         mtsdram(SDRAM_SDTR2, CONFIG_SYS_SDRAM0_SDTR2);
2940         mtsdram(SDRAM_SDTR3, CONFIG_SYS_SDRAM0_SDTR3);
2941
2942         /* Set Mode and Extended Mode Registers */
2943
2944         mtsdram(SDRAM_MMODE, CONFIG_SYS_SDRAM0_MMODE);
2945         mtsdram(SDRAM_MEMODE, CONFIG_SYS_SDRAM0_MEMODE);
2946
2947         /* Set Memory Controller Options 1 Register */
2948
2949         mtsdram(SDRAM_MCOPT1, CONFIG_SYS_SDRAM0_MCOPT1);
2950
2951         /* Set Manual Initialization Control Registers */
2952
2953         mtsdram(SDRAM_INITPLR0, CONFIG_SYS_SDRAM0_INITPLR0);
2954         mtsdram(SDRAM_INITPLR1, CONFIG_SYS_SDRAM0_INITPLR1);
2955         mtsdram(SDRAM_INITPLR2, CONFIG_SYS_SDRAM0_INITPLR2);
2956         mtsdram(SDRAM_INITPLR3, CONFIG_SYS_SDRAM0_INITPLR3);
2957         mtsdram(SDRAM_INITPLR4, CONFIG_SYS_SDRAM0_INITPLR4);
2958         mtsdram(SDRAM_INITPLR5, CONFIG_SYS_SDRAM0_INITPLR5);
2959         mtsdram(SDRAM_INITPLR6, CONFIG_SYS_SDRAM0_INITPLR6);
2960         mtsdram(SDRAM_INITPLR7, CONFIG_SYS_SDRAM0_INITPLR7);
2961         mtsdram(SDRAM_INITPLR8, CONFIG_SYS_SDRAM0_INITPLR8);
2962         mtsdram(SDRAM_INITPLR9, CONFIG_SYS_SDRAM0_INITPLR9);
2963         mtsdram(SDRAM_INITPLR10, CONFIG_SYS_SDRAM0_INITPLR10);
2964         mtsdram(SDRAM_INITPLR11, CONFIG_SYS_SDRAM0_INITPLR11);
2965         mtsdram(SDRAM_INITPLR12, CONFIG_SYS_SDRAM0_INITPLR12);
2966         mtsdram(SDRAM_INITPLR13, CONFIG_SYS_SDRAM0_INITPLR13);
2967         mtsdram(SDRAM_INITPLR14, CONFIG_SYS_SDRAM0_INITPLR14);
2968         mtsdram(SDRAM_INITPLR15, CONFIG_SYS_SDRAM0_INITPLR15);
2969
2970         /* Set On-Die Termination Registers */
2971
2972         mtsdram(SDRAM_CODT, CONFIG_SYS_SDRAM0_CODT);
2973         mtsdram(SDRAM_MODT0, CONFIG_SYS_SDRAM0_MODT0);
2974         mtsdram(SDRAM_MODT1, CONFIG_SYS_SDRAM0_MODT1);
2975
2976         /* Set Write Timing Register */
2977
2978         mtsdram(SDRAM_WRDTR, CONFIG_SYS_SDRAM0_WRDTR);
2979
2980         /*
2981          * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
2982          * SDRAM0_MCOPT2[IPTR] = 1
2983          */
2984
2985         mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT |
2986                                SDRAM_MCOPT2_IPTR_EXECUTE));
2987
2988         /*
2989          * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
2990          * completion of initialization.
2991          */
2992
2993         do {
2994                 mfsdram(SDRAM_MCSTAT, val);
2995         } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
2996
2997         /* Set Delay Control Registers */
2998
2999         mtsdram(SDRAM_DLCR, CONFIG_SYS_SDRAM0_DLCR);
3000
3001 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
3002         mtsdram(SDRAM_RDCC, CONFIG_SYS_SDRAM0_RDCC);
3003         mtsdram(SDRAM_RQDC, CONFIG_SYS_SDRAM0_RQDC);
3004         mtsdram(SDRAM_RFDC, CONFIG_SYS_SDRAM0_RFDC);
3005 #endif /* !CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3006
3007         /*
3008          * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
3009          */
3010
3011         mfsdram(SDRAM_MCOPT2, val);
3012         mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
3013
3014 #if defined(CONFIG_440)
3015         /*
3016          * Program TLB entries with caches enabled, for best performace
3017          * while auto-calibrating and ECC generation
3018          */
3019         program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), 0);
3020 #endif
3021
3022 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
3023 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
3024         /*------------------------------------------------------------------
3025          | DQS calibration.
3026          +-----------------------------------------------------------------*/
3027         DQS_autocalibration();
3028 #endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
3029 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3030
3031         /*
3032          * Now complete RDSS configuration as mentioned on page 7 of the AMCC
3033          * PowerPC440SP/SPe DDR2 application note:
3034          * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
3035          */
3036         update_rdcc();
3037
3038 #if defined(CONFIG_DDR_ECC)
3039         do_program_ecc(0);
3040 #endif /* defined(CONFIG_DDR_ECC) */
3041
3042 #if defined(CONFIG_440)
3043         /*
3044          * Now after initialization (auto-calibration and ECC generation)
3045          * remove the TLB entries with caches enabled and program again with
3046          * desired cache functionality
3047          */
3048         remove_tlb(0, (CONFIG_SYS_MBYTES_SDRAM << 20));
3049         program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), MY_TLB_WORD2_I_ENABLE);
3050 #endif
3051
3052         ppc4xx_ibm_ddr2_register_dump();
3053
3054 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
3055         /*
3056          * Clear potential errors resulting from auto-calibration.
3057          * If not done, then we could get an interrupt later on when
3058          * exceptions are enabled.
3059          */
3060         set_mcsr(get_mcsr());
3061 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3062
3063 #endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
3064
3065         return (CONFIG_SYS_MBYTES_SDRAM << 20);
3066 }
3067 #endif /* CONFIG_SPD_EEPROM */
3068
3069 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
3070 #if defined(CONFIG_440)
3071 u32 mfdcr_any(u32 dcr)
3072 {
3073         u32 val;
3074
3075         switch (dcr) {
3076         case SDRAM_R0BAS + 0:
3077                 val = mfdcr(SDRAM_R0BAS + 0);
3078                 break;
3079         case SDRAM_R0BAS + 1:
3080                 val = mfdcr(SDRAM_R0BAS + 1);
3081                 break;
3082         case SDRAM_R0BAS + 2:
3083                 val = mfdcr(SDRAM_R0BAS + 2);
3084                 break;
3085         case SDRAM_R0BAS + 3:
3086                 val = mfdcr(SDRAM_R0BAS + 3);
3087                 break;
3088         default:
3089                 printf("DCR %d not defined in case statement!!!\n", dcr);
3090                 val = 0; /* just to satisfy the compiler */
3091         }
3092
3093         return val;
3094 }
3095
3096 void mtdcr_any(u32 dcr, u32 val)
3097 {
3098         switch (dcr) {
3099         case SDRAM_R0BAS + 0:
3100                 mtdcr(SDRAM_R0BAS + 0, val);
3101                 break;
3102         case SDRAM_R0BAS + 1:
3103                 mtdcr(SDRAM_R0BAS + 1, val);
3104                 break;
3105         case SDRAM_R0BAS + 2:
3106                 mtdcr(SDRAM_R0BAS + 2, val);
3107                 break;
3108         case SDRAM_R0BAS + 3:
3109                 mtdcr(SDRAM_R0BAS + 3, val);
3110                 break;
3111         default:
3112                 printf("DCR %d not defined in case statement!!!\n", dcr);
3113         }
3114 }
3115 #endif /* defined(CONFIG_440) */
3116 #endif /* !defined(CONFIG_NAND_U_BOOT) &&  !defined(CONFIG_NAND_SPL) */
3117
3118 inline void ppc4xx_ibm_ddr2_register_dump(void)
3119 {
3120 #if defined(DEBUG)
3121         printf("\nPPC4xx IBM DDR2 Register Dump:\n");
3122
3123 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3124      defined(CONFIG_460EX) || defined(CONFIG_460GT))
3125         PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R0BAS);
3126         PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R1BAS);
3127         PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R2BAS);
3128         PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R3BAS);
3129 #endif /* (defined(CONFIG_440SP) || ... */
3130 #if defined(CONFIG_405EX)
3131         PPC4xx_IBM_DDR2_DUMP_REGISTER(BESR);
3132         PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARL);
3133         PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARH);
3134         PPC4xx_IBM_DDR2_DUMP_REGISTER(WMIRQ);
3135         PPC4xx_IBM_DDR2_DUMP_REGISTER(PLBOPT);
3136         PPC4xx_IBM_DDR2_DUMP_REGISTER(PUABA);
3137 #endif /* defined(CONFIG_405EX) */
3138         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB0CF);
3139         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB1CF);
3140         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB2CF);
3141         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB3CF);
3142         PPC4xx_IBM_DDR2_DUMP_REGISTER(MCSTAT);
3143         PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT1);
3144         PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT2);
3145         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT0);
3146         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT1);
3147         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT2);
3148         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT3);
3149         PPC4xx_IBM_DDR2_DUMP_REGISTER(CODT);
3150 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3151      defined(CONFIG_460EX) || defined(CONFIG_460GT))
3152         PPC4xx_IBM_DDR2_DUMP_REGISTER(VVPR);
3153         PPC4xx_IBM_DDR2_DUMP_REGISTER(OPARS);
3154         /*
3155          * OPART is only used as a trigger register.
3156          *
3157          * No data is contained in this register, and reading or writing
3158          * to is can cause bad things to happen (hangs). Just skip it and
3159          * report "N/A".
3160          */
3161         printf("%20s = N/A\n", "SDRAM_OPART");
3162 #endif /* defined(CONFIG_440SP) || ... */
3163         PPC4xx_IBM_DDR2_DUMP_REGISTER(RTR);
3164         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR0);
3165         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR1);
3166         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR2);
3167         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR3);
3168         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR4);
3169         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR5);
3170         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR6);
3171         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR7);
3172         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR8);
3173         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR9);
3174         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR10);
3175         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR11);
3176         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR12);
3177         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR13);
3178         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR14);
3179         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR15);
3180         PPC4xx_IBM_DDR2_DUMP_REGISTER(RQDC);
3181         PPC4xx_IBM_DDR2_DUMP_REGISTER(RFDC);
3182         PPC4xx_IBM_DDR2_DUMP_REGISTER(RDCC);
3183         PPC4xx_IBM_DDR2_DUMP_REGISTER(DLCR);
3184         PPC4xx_IBM_DDR2_DUMP_REGISTER(CLKTR);
3185         PPC4xx_IBM_DDR2_DUMP_REGISTER(WRDTR);
3186         PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR1);
3187         PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR2);
3188         PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR3);
3189         PPC4xx_IBM_DDR2_DUMP_REGISTER(MMODE);
3190         PPC4xx_IBM_DDR2_DUMP_REGISTER(MEMODE);
3191         PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCES);
3192 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3193      defined(CONFIG_460EX) || defined(CONFIG_460GT))
3194         PPC4xx_IBM_DDR2_DUMP_REGISTER(CID);
3195 #endif /* defined(CONFIG_440SP) || ... */
3196         PPC4xx_IBM_DDR2_DUMP_REGISTER(RID);
3197         PPC4xx_IBM_DDR2_DUMP_REGISTER(FCSR);
3198         PPC4xx_IBM_DDR2_DUMP_REGISTER(RTSR);
3199 #endif /* defined(DEBUG) */
3200 }