arch/powerpc/cpu/mpc8xxx/ddr/util.c

   1 /*
   2  * Copyright 2008-2011 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/fsl_law.h>
  11
  12 #include "ddr.h"
  13
  14 /*
  15  * Round mclk_ps to nearest 10 ps in memory controller code.
  16  *
  17  * If an imprecise data rate is too high due to rounding error
  18  * propagation, compute a suitably rounded mclk_ps to compute
  19  * a working memory controller configuration.
  20  */
  21 unsigned int get_memory_clk_period_ps(void)
  22 {
  23         unsigned int mclk_ps;
  24
  25         mclk_ps = 2000000000000ULL / get_ddr_freq(0);
  26         /* round to nearest 10 ps */
  27         return 10 * ((mclk_ps + 5) / 10);
  28 }
  29
  30 /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
  31 unsigned int picos_to_mclk(unsigned int picos)
  32 {
  33         const unsigned long long ULL_2e12 = 2000000000000ULL;
  34         const unsigned long long ULL_8Fs = 0xFFFFFFFFULL;
  35         unsigned long long clks;
  36         unsigned long long clks_temp;
  37
  38         if (!picos)
  39                 return 0;
  40
  41         clks = get_ddr_freq(0) * (unsigned long long) picos;
  42         clks_temp = clks;
  43         clks = clks / ULL_2e12;
  44         if (clks_temp % ULL_2e12) {
  45                 clks++;
  46         }
  47
  48         if (clks > ULL_8Fs) {
  49                 clks = ULL_8Fs;
  50         }
  51
  52         return (unsigned int) clks;
  53 }
  54
  55 unsigned int mclk_to_picos(unsigned int mclk)
  56 {
  57         return get_memory_clk_period_ps() * mclk;
  58 }
  59
  60 void
  61 __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
  62                            unsigned int memctl_interleaved,
  63                            unsigned int ctrl_num)
  64 {
  65         unsigned long long base = memctl_common_params->base_address;
  66         unsigned long long size = memctl_common_params->total_mem;
  67
  68         /*
  69          * If no DIMMs on this controller, do not proceed any further.
  70          */
  71         if (!memctl_common_params->ndimms_present) {
  72                 return;
  73         }
  74
  75 #if !defined(CONFIG_PHYS_64BIT)
  76         if (base >= CONFIG_MAX_MEM_MAPPED)
  77                 return;
  78         if ((base + size) >= CONFIG_MAX_MEM_MAPPED)
  79                 size = CONFIG_MAX_MEM_MAPPED - base;
  80 #endif
  81
  82         if (ctrl_num == 0) {
  83                 /*
  84                  * Set up LAW for DDR controller 1 space.
  85                  */
  86                 unsigned int lawbar1_target_id = memctl_interleaved
  87                         ? LAW_TRGT_IF_DDR_INTRLV : LAW_TRGT_IF_DDR_1;
  88
  89                 if (set_ddr_laws(base, size, lawbar1_target_id) < 0) {
  90                         printf("%s: ERROR (ctrl #0, intrlv=%d)\n", __func__,
  91                                 memctl_interleaved);
  92                         return ;
  93                 }
  94         } else if (ctrl_num == 1) {
  95                 if (set_ddr_laws(base, size, LAW_TRGT_IF_DDR_2) < 0) {
  96                         printf("%s: ERROR (ctrl #1)\n", __func__);
  97                         return ;
  98                 }
  99         } else {
 100                 printf("%s: unexpected DDR controller number (%u)\n", __func__,
 101                         ctrl_num);
 102         }
 103 }
 104
 105 __attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void
 106 fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
 107                          unsigned int memctl_interleaved,
 108                          unsigned int ctrl_num);
 109
 110 void board_add_ram_info(int use_default)
 111 {
 112 #if defined(CONFIG_MPC85xx)
 113         volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
 114 #elif defined(CONFIG_MPC86xx)
 115         volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC86xx_DDR_ADDR);
 116 #endif
 117 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
 118         uint32_t cs0_config = in_be32(&ddr->cs0_config);
 119 #endif
 120         uint32_t sdram_cfg = in_be32(&ddr->sdram_cfg);
 121         int cas_lat;
 122
 123         puts(" (DDR");
 124         switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
 125                 SDRAM_CFG_SDRAM_TYPE_SHIFT) {
 126         case SDRAM_TYPE_DDR1:
 127                 puts("1");
 128                 break;
 129         case SDRAM_TYPE_DDR2:
 130                 puts("2");
 131                 break;
 132         case SDRAM_TYPE_DDR3:
 133                 puts("3");
 134                 break;
 135         default:
 136                 puts("?");
 137                 break;
 138         }
 139
 140         if (sdram_cfg & SDRAM_CFG_32_BE)
 141                 puts(", 32-bit");
 142         else if (sdram_cfg & SDRAM_CFG_16_BE)
 143                 puts(", 16-bit");
 144         else
 145                 puts(", 64-bit");
 146
 147         /* Calculate CAS latency based on timing cfg values */
 148         cas_lat = ((in_be32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1;
 149         if ((in_be32(&ddr->timing_cfg_3) >> 12) & 1)
 150                 cas_lat += (8 << 1);
 151         printf(", CL=%d", cas_lat >> 1);
 152         if (cas_lat & 0x1)
 153                 puts(".5");
 154
 155         if (sdram_cfg & SDRAM_CFG_ECC_EN)
 156                 puts(", ECC on)");
 157         else
 158                 puts(", ECC off)");
 159
 160 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
 161         if (cs0_config & 0x20000000) {
 162                 puts("\n");
 163                 puts("       DDR Controller Interleaving Mode: ");
 164
 165                 switch ((cs0_config >> 24) & 0xf) {
 166                 case FSL_DDR_CACHE_LINE_INTERLEAVING:
 167                         puts("cache line");
 168                         break;
 169                 case FSL_DDR_PAGE_INTERLEAVING:
 170                         puts("page");
 171                         break;
 172                 case FSL_DDR_BANK_INTERLEAVING:
 173                         puts("bank");
 174                         break;
 175                 case FSL_DDR_SUPERBANK_INTERLEAVING:
 176                         puts("super-bank");
 177                         break;
 178                 default:
 179                         puts("invalid");
 180                         break;
 181                 }
 182         }
 183 #endif
 184
 185         if ((sdram_cfg >> 8) & 0x7f) {
 186                 puts("\n");
 187                 puts("       DDR Chip-Select Interleaving Mode: ");
 188                 switch(sdram_cfg >> 8 & 0x7f) {
 189                 case FSL_DDR_CS0_CS1_CS2_CS3:
 190                         puts("CS0+CS1+CS2+CS3");
 191                         break;
 192                 case FSL_DDR_CS0_CS1:
 193                         puts("CS0+CS1");
 194                         break;
 195                 case FSL_DDR_CS2_CS3:
 196                         puts("CS2+CS3");
 197                         break;
 198                 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 199                         puts("CS0+CS1 and CS2+CS3");
 200                         break;
 201                 default:
 202                         puts("invalid");
 203                         break;
 204                 }
 205         }
 206 }