arch/powerpc/cpu/mpc8xxx/ddr/util.c

   1 /*
   2  * Copyright 2008-2011 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/fsl_law.h>
  11 #include <div64.h>
  12
  13 #include "ddr.h"
  14
  15 /* To avoid 64-bit full-divides, we factor this here */
  16 #define ULL_2E12 2000000000000ULL
  17 #define UL_5POW12 244140625UL
  18 #define UL_2POW13 (1UL << 13)
  19
  20 #define ULL_8FS 0xFFFFFFFFULL
  21
  22 /*
  23  * Round mclk_ps to nearest 10 ps in memory controller code.
  24  *
  25  * If an imprecise data rate is too high due to rounding error
  26  * propagation, compute a suitably rounded mclk_ps to compute
  27  * a working memory controller configuration.
  28  */
  29 unsigned int get_memory_clk_period_ps(void)
  30 {
  31         unsigned int data_rate = get_ddr_freq(0);
  32         unsigned int result;
  33
  34         /* Round to nearest 10ps, being careful about 64-bit multiply/divide */
  35         unsigned long long mclk_ps = ULL_2E12;
  36
  37         /* Add 5*data_rate, for rounding */
  38         mclk_ps += 5*(unsigned long long)data_rate;
  39
  40         /* Now perform the big divide, the result fits in 32-bits */
  41         do_div(mclk_ps, data_rate);
  42         result = mclk_ps;
  43
  44         /* We still need to round to 10ps */
  45         return 10 * (result/10);
  46 }
  47
  48 /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
  49 unsigned int picos_to_mclk(unsigned int picos)
  50 {
  51         unsigned long long clks, clks_rem;
  52
  53         /* Short circuit for zero picos */
  54         if (!picos)
  55                 return 0;
  56
  57         /* First multiply the time by the data rate (32x32 => 64) */
  58         clks = picos * (unsigned long long)get_ddr_freq(0);
  59
  60         /*
  61          * Now divide by 5^12 and track the 32-bit remainder, then divide
  62          * by 2*(2^12) using shifts (and updating the remainder).
  63          */
  64         clks_rem = do_div(clks, UL_5POW12);
  65         clks_rem <<= 13;
  66         clks_rem |= clks & (UL_2POW13-1);
  67         clks >>= 13;
  68
  69         /* If we had a remainder, then round up */
  70         if (clks_rem)
  71                 clks++;
  72
  73         /* Clamp to the maximum representable value */
  74         if (clks > ULL_8FS)
  75                 clks = ULL_8FS;
  76         return (unsigned int) clks;
  77 }
  78
  79 unsigned int mclk_to_picos(unsigned int mclk)
  80 {
  81         return get_memory_clk_period_ps() * mclk;
  82 }
  83
  84 void
  85 __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
  86                            unsigned int memctl_interleaved,
  87                            unsigned int ctrl_num)
  88 {
  89         unsigned long long base = memctl_common_params->base_address;
  90         unsigned long long size = memctl_common_params->total_mem;
  91
  92         /*
  93          * If no DIMMs on this controller, do not proceed any further.
  94          */
  95         if (!memctl_common_params->ndimms_present) {
  96                 return;
  97         }
  98
  99 #if !defined(CONFIG_PHYS_64BIT)
 100         if (base >= CONFIG_MAX_MEM_MAPPED)
 101                 return;
 102         if ((base + size) >= CONFIG_MAX_MEM_MAPPED)
 103                 size = CONFIG_MAX_MEM_MAPPED - base;
 104 #endif
 105
 106         if (ctrl_num == 0) {
 107                 /*
 108                  * Set up LAW for DDR controller 1 space.
 109                  */
 110                 unsigned int lawbar1_target_id = memctl_interleaved
 111                         ? LAW_TRGT_IF_DDR_INTRLV : LAW_TRGT_IF_DDR_1;
 112
 113                 if (set_ddr_laws(base, size, lawbar1_target_id) < 0) {
 114                         printf("%s: ERROR (ctrl #0, intrlv=%d)\n", __func__,
 115                                 memctl_interleaved);
 116                         return ;
 117                 }
 118         } else if (ctrl_num == 1) {
 119                 if (set_ddr_laws(base, size, LAW_TRGT_IF_DDR_2) < 0) {
 120                         printf("%s: ERROR (ctrl #1)\n", __func__);
 121                         return ;
 122                 }
 123         } else {
 124                 printf("%s: unexpected DDR controller number (%u)\n", __func__,
 125                         ctrl_num);
 126         }
 127 }
 128
 129 __attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void
 130 fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
 131                          unsigned int memctl_interleaved,
 132                          unsigned int ctrl_num);
 133
 134 void board_add_ram_info(int use_default)
 135 {
 136 #if defined(CONFIG_MPC85xx)
 137         volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
 138 #elif defined(CONFIG_MPC86xx)
 139         volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC86xx_DDR_ADDR);
 140 #endif
 141 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
 142         uint32_t cs0_config = in_be32(&ddr->cs0_config);
 143 #endif
 144         uint32_t sdram_cfg = in_be32(&ddr->sdram_cfg);
 145         int cas_lat;
 146
 147         puts(" (DDR");
 148         switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
 149                 SDRAM_CFG_SDRAM_TYPE_SHIFT) {
 150         case SDRAM_TYPE_DDR1:
 151                 puts("1");
 152                 break;
 153         case SDRAM_TYPE_DDR2:
 154                 puts("2");
 155                 break;
 156         case SDRAM_TYPE_DDR3:
 157                 puts("3");
 158                 break;
 159         default:
 160                 puts("?");
 161                 break;
 162         }
 163
 164         if (sdram_cfg & SDRAM_CFG_32_BE)
 165                 puts(", 32-bit");
 166         else if (sdram_cfg & SDRAM_CFG_16_BE)
 167                 puts(", 16-bit");
 168         else
 169                 puts(", 64-bit");
 170
 171         /* Calculate CAS latency based on timing cfg values */
 172         cas_lat = ((in_be32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1;
 173         if ((in_be32(&ddr->timing_cfg_3) >> 12) & 1)
 174                 cas_lat += (8 << 1);
 175         printf(", CL=%d", cas_lat >> 1);
 176         if (cas_lat & 0x1)
 177                 puts(".5");
 178
 179         if (sdram_cfg & SDRAM_CFG_ECC_EN)
 180                 puts(", ECC on)");
 181         else
 182                 puts(", ECC off)");
 183
 184 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
 185         if (cs0_config & 0x20000000) {
 186                 puts("\n");
 187                 puts("       DDR Controller Interleaving Mode: ");
 188
 189                 switch ((cs0_config >> 24) & 0xf) {
 190                 case FSL_DDR_CACHE_LINE_INTERLEAVING:
 191                         puts("cache line");
 192                         break;
 193                 case FSL_DDR_PAGE_INTERLEAVING:
 194                         puts("page");
 195                         break;
 196                 case FSL_DDR_BANK_INTERLEAVING:
 197                         puts("bank");
 198                         break;
 199                 case FSL_DDR_SUPERBANK_INTERLEAVING:
 200                         puts("super-bank");
 201                         break;
 202                 default:
 203                         puts("invalid");
 204                         break;
 205                 }
 206         }
 207 #endif
 208
 209         if ((sdram_cfg >> 8) & 0x7f) {
 210                 puts("\n");
 211                 puts("       DDR Chip-Select Interleaving Mode: ");
 212                 switch(sdram_cfg >> 8 & 0x7f) {
 213                 case FSL_DDR_CS0_CS1_CS2_CS3:
 214                         puts("CS0+CS1+CS2+CS3");
 215                         break;
 216                 case FSL_DDR_CS0_CS1:
 217                         puts("CS0+CS1");
 218                         break;
 219                 case FSL_DDR_CS2_CS3:
 220                         puts("CS2+CS3");
 221                         break;
 222                 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 223                         puts("CS0+CS1 and CS2+CS3");
 224                         break;
 225                 default:
 226                         puts("invalid");
 227                         break;
 228                 }
 229         }
 230 }