arch/powerpc/cpu/mpc8xxx/ddr/options.c

   1 /*
   2  * Copyright 2008, 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the Free
   6  * Software Foundation; either version 2 of the License, or (at your option)
   7  * any later version.
   8  */
   9
  10 #include <common.h>
  11 #include <hwconfig.h>
  12 #include <asm/fsl_ddr_sdram.h>
  13
  14 #include "ddr.h"
  15
  16 /*
  17  * Use our own stack based buffer before relocation to allow accessing longer
  18  * hwconfig strings that might be in the environment before we've relocated.
  19  * This is pretty fragile on both the use of stack and if the buffer is big
  20  * enough. However we will get a warning from getenv_f for the later.
  21  */
  22 #define HWCONFIG_BUFFER_SIZE    128
  23
  24 /* Board-specific functions defined in each board's ddr.c */
  25 extern void fsl_ddr_board_options(memctl_options_t *popts,
  26                 dimm_params_t *pdimm,
  27                 unsigned int ctrl_num);
  28
  29 typedef struct {
  30         unsigned int odt_rd_cfg;
  31         unsigned int odt_wr_cfg;
  32         unsigned int odt_rtt_norm;
  33         unsigned int odt_rtt_wr;
  34 } dynamic_odt_t;
  35
  36 static const dynamic_odt_t single_Q[4] = {
  37         {       /* cs0 */
  38                 FSL_DDR_ODT_NEVER,
  39                 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
  40                 DDR3_RTT_20_OHM,
  41                 DDR3_RTT_120_OHM
  42         },
  43         {       /* cs1 */
  44                 FSL_DDR_ODT_NEVER,
  45                 FSL_DDR_ODT_NEVER,      /* tied high */
  46                 DDR3_RTT_OFF,
  47                 DDR3_RTT_120_OHM
  48         },
  49         {       /* cs2 */
  50                 FSL_DDR_ODT_NEVER,
  51                 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
  52                 DDR3_RTT_20_OHM,
  53                 DDR3_RTT_120_OHM
  54         },
  55         {       /* cs3 */
  56                 FSL_DDR_ODT_NEVER,
  57                 FSL_DDR_ODT_NEVER,      /* tied high */
  58                 DDR3_RTT_OFF,
  59                 DDR3_RTT_120_OHM
  60         }
  61 };
  62
  63 static const dynamic_odt_t single_D[4] = {
  64         {       /* cs0 */
  65                 FSL_DDR_ODT_NEVER,
  66                 FSL_DDR_ODT_ALL,
  67                 DDR3_RTT_40_OHM,
  68                 DDR3_RTT_OFF
  69         },
  70         {       /* cs1 */
  71                 FSL_DDR_ODT_NEVER,
  72                 FSL_DDR_ODT_NEVER,
  73                 DDR3_RTT_OFF,
  74                 DDR3_RTT_OFF
  75         },
  76         {0, 0, 0, 0},
  77         {0, 0, 0, 0}
  78 };
  79
  80 static const dynamic_odt_t single_S[4] = {
  81         {       /* cs0 */
  82                 FSL_DDR_ODT_NEVER,
  83                 FSL_DDR_ODT_ALL,
  84                 DDR3_RTT_40_OHM,
  85                 DDR3_RTT_OFF
  86         },
  87         {0, 0, 0, 0},
  88         {0, 0, 0, 0},
  89         {0, 0, 0, 0},
  90 };
  91
  92 static const dynamic_odt_t dual_DD[4] = {
  93         {       /* cs0 */
  94                 FSL_DDR_ODT_NEVER,
  95                 FSL_DDR_ODT_SAME_DIMM,
  96                 DDR3_RTT_120_OHM,
  97                 DDR3_RTT_OFF
  98         },
  99         {       /* cs1 */
 100                 FSL_DDR_ODT_OTHER_DIMM,
 101                 FSL_DDR_ODT_OTHER_DIMM,
 102                 DDR3_RTT_30_OHM,
 103                 DDR3_RTT_OFF
 104         },
 105         {       /* cs2 */
 106                 FSL_DDR_ODT_NEVER,
 107                 FSL_DDR_ODT_SAME_DIMM,
 108                 DDR3_RTT_120_OHM,
 109                 DDR3_RTT_OFF
 110         },
 111         {       /* cs3 */
 112                 FSL_DDR_ODT_OTHER_DIMM,
 113                 FSL_DDR_ODT_OTHER_DIMM,
 114                 DDR3_RTT_30_OHM,
 115                 DDR3_RTT_OFF
 116         }
 117 };
 118
 119 static const dynamic_odt_t dual_DS[4] = {
 120         {       /* cs0 */
 121                 FSL_DDR_ODT_NEVER,
 122                 FSL_DDR_ODT_SAME_DIMM,
 123                 DDR3_RTT_120_OHM,
 124                 DDR3_RTT_OFF
 125         },
 126         {       /* cs1 */
 127                 FSL_DDR_ODT_OTHER_DIMM,
 128                 FSL_DDR_ODT_OTHER_DIMM,
 129                 DDR3_RTT_30_OHM,
 130                 DDR3_RTT_OFF
 131         },
 132         {       /* cs2 */
 133                 FSL_DDR_ODT_OTHER_DIMM,
 134                 FSL_DDR_ODT_ALL,
 135                 DDR3_RTT_20_OHM,
 136                 DDR3_RTT_120_OHM
 137         },
 138         {0, 0, 0, 0}
 139 };
 140 static const dynamic_odt_t dual_SD[4] = {
 141         {       /* cs0 */
 142                 FSL_DDR_ODT_OTHER_DIMM,
 143                 FSL_DDR_ODT_ALL,
 144                 DDR3_RTT_20_OHM,
 145                 DDR3_RTT_120_OHM
 146         },
 147         {0, 0, 0, 0},
 148         {       /* cs2 */
 149                 FSL_DDR_ODT_NEVER,
 150                 FSL_DDR_ODT_SAME_DIMM,
 151                 DDR3_RTT_120_OHM,
 152                 DDR3_RTT_OFF
 153         },
 154         {       /* cs3 */
 155                 FSL_DDR_ODT_OTHER_DIMM,
 156                 FSL_DDR_ODT_OTHER_DIMM,
 157                 DDR3_RTT_20_OHM,
 158                 DDR3_RTT_OFF
 159         }
 160 };
 161
 162 static const dynamic_odt_t dual_SS[4] = {
 163         {       /* cs0 */
 164                 FSL_DDR_ODT_OTHER_DIMM,
 165                 FSL_DDR_ODT_ALL,
 166                 DDR3_RTT_30_OHM,
 167                 DDR3_RTT_120_OHM
 168         },
 169         {0, 0, 0, 0},
 170         {       /* cs2 */
 171                 FSL_DDR_ODT_OTHER_DIMM,
 172                 FSL_DDR_ODT_ALL,
 173                 DDR3_RTT_30_OHM,
 174                 DDR3_RTT_120_OHM
 175         },
 176         {0, 0, 0, 0}
 177 };
 178
 179 static const dynamic_odt_t dual_D0[4] = {
 180         {       /* cs0 */
 181                 FSL_DDR_ODT_NEVER,
 182                 FSL_DDR_ODT_SAME_DIMM,
 183                 DDR3_RTT_40_OHM,
 184                 DDR3_RTT_OFF
 185         },
 186         {       /* cs1 */
 187                 FSL_DDR_ODT_NEVER,
 188                 FSL_DDR_ODT_NEVER,
 189                 DDR3_RTT_OFF,
 190                 DDR3_RTT_OFF
 191         },
 192         {0, 0, 0, 0},
 193         {0, 0, 0, 0}
 194 };
 195
 196 static const dynamic_odt_t dual_0D[4] = {
 197         {0, 0, 0, 0},
 198         {0, 0, 0, 0},
 199         {       /* cs2 */
 200                 FSL_DDR_ODT_NEVER,
 201                 FSL_DDR_ODT_SAME_DIMM,
 202                 DDR3_RTT_40_OHM,
 203                 DDR3_RTT_OFF
 204         },
 205         {       /* cs3 */
 206                 FSL_DDR_ODT_NEVER,
 207                 FSL_DDR_ODT_NEVER,
 208                 DDR3_RTT_OFF,
 209                 DDR3_RTT_OFF
 210         }
 211 };
 212
 213 static const dynamic_odt_t dual_S0[4] = {
 214         {       /* cs0 */
 215                 FSL_DDR_ODT_NEVER,
 216                 FSL_DDR_ODT_CS,
 217                 DDR3_RTT_40_OHM,
 218                 DDR3_RTT_OFF
 219         },
 220         {0, 0, 0, 0},
 221         {0, 0, 0, 0},
 222         {0, 0, 0, 0}
 223
 224 };
 225
 226 static const dynamic_odt_t dual_0S[4] = {
 227         {0, 0, 0, 0},
 228         {0, 0, 0, 0},
 229         {       /* cs2 */
 230                 FSL_DDR_ODT_NEVER,
 231                 FSL_DDR_ODT_CS,
 232                 DDR3_RTT_40_OHM,
 233                 DDR3_RTT_OFF
 234         },
 235         {0, 0, 0, 0}
 236
 237 };
 238
 239 static const dynamic_odt_t odt_unknown[4] = {
 240         {       /* cs0 */
 241                 FSL_DDR_ODT_NEVER,
 242                 FSL_DDR_ODT_CS,
 243                 DDR3_RTT_120_OHM,
 244                 DDR3_RTT_OFF
 245         },
 246         {       /* cs1 */
 247                 FSL_DDR_ODT_NEVER,
 248                 FSL_DDR_ODT_CS,
 249                 DDR3_RTT_120_OHM,
 250                 DDR3_RTT_OFF
 251         },
 252         {       /* cs2 */
 253                 FSL_DDR_ODT_NEVER,
 254                 FSL_DDR_ODT_CS,
 255                 DDR3_RTT_120_OHM,
 256                 DDR3_RTT_OFF
 257         },
 258         {       /* cs3 */
 259                 FSL_DDR_ODT_NEVER,
 260                 FSL_DDR_ODT_CS,
 261                 DDR3_RTT_120_OHM,
 262                 DDR3_RTT_OFF
 263         }
 264 };
 265
 266 unsigned int populate_memctl_options(int all_DIMMs_registered,
 267                         memctl_options_t *popts,
 268                         dimm_params_t *pdimm,
 269                         unsigned int ctrl_num)
 270 {
 271         unsigned int i;
 272         char buffer[HWCONFIG_BUFFER_SIZE];
 273         char *buf = NULL;
 274         const dynamic_odt_t *pdodt = odt_unknown;
 275
 276         /*
 277          * Extract hwconfig from environment since we have not properly setup
 278          * the environment but need it for ddr config params
 279          */
 280         if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
 281                 buf = buffer;
 282
 283         /* Chip select options. */
 284         if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
 285                 switch (pdimm[0].n_ranks) {
 286                 case 1:
 287                         pdodt = single_S;
 288                         break;
 289                 case 2:
 290                         pdodt = single_D;
 291                         break;
 292                 case 4:
 293                         pdodt = single_Q;
 294                         break;
 295                 }
 296         } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
 297                 switch (pdimm[0].n_ranks) {
 298                 case 2:
 299                         switch (pdimm[1].n_ranks) {
 300                         case 2:
 301                                 pdodt = dual_DD;
 302                                 break;
 303                         case 1:
 304                                 pdodt = dual_DS;
 305                                 break;
 306                         case 0:
 307                                 pdodt = dual_D0;
 308                                 break;
 309                         }
 310                         break;
 311                 case 1:
 312                         switch (pdimm[1].n_ranks) {
 313                         case 2:
 314                                 pdodt = dual_SD;
 315                                 break;
 316                         case 1:
 317                                 pdodt = dual_SS;
 318                                 break;
 319                         case 0:
 320                                 pdodt = dual_S0;
 321                                 break;
 322                         }
 323                         break;
 324                 case 0:
 325                         switch (pdimm[1].n_ranks) {
 326                         case 2:
 327                                 pdodt = dual_0D;
 328                                 break;
 329                         case 1:
 330                                 pdodt = dual_0S;
 331                                 break;
 332                         }
 333                         break;
 334                 }
 335         }
 336
 337         /* Pick chip-select local options. */
 338         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 339 #if defined(CONFIG_FSL_DDR3)
 340                 popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
 341                 popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
 342                 popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
 343                 popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr;
 344 #else
 345                 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
 346                 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
 347 #endif
 348                 popts->cs_local_opts[i].auto_precharge = 0;
 349         }
 350
 351         /* Pick interleaving mode. */
 352
 353         /*
 354          * 0 = no interleaving
 355          * 1 = interleaving between 2 controllers
 356          */
 357         popts->memctl_interleaving = 0;
 358
 359         /*
 360          * 0 = cacheline
 361          * 1 = page
 362          * 2 = (logical) bank
 363          * 3 = superbank (only if CS interleaving is enabled)
 364          */
 365         popts->memctl_interleaving_mode = 0;
 366
 367         /*
 368          * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
 369          * 1: page:      bit to the left of the column bits selects the memctl
 370          * 2: bank:      bit to the left of the bank bits selects the memctl
 371          * 3: superbank: bit to the left of the chip select selects the memctl
 372          *
 373          * NOTE: ba_intlv (rank interleaving) is independent of memory
 374          * controller interleaving; it is only within a memory controller.
 375          * Must use superbank interleaving if rank interleaving is used and
 376          * memory controller interleaving is enabled.
 377          */
 378
 379         /*
 380          * 0 = no
 381          * 0x40 = CS0,CS1
 382          * 0x20 = CS2,CS3
 383          * 0x60 = CS0,CS1 + CS2,CS3
 384          * 0x04 = CS0,CS1,CS2,CS3
 385          */
 386         popts->ba_intlv_ctl = 0;
 387
 388         /* Memory Organization Parameters */
 389         popts->registered_dimm_en = all_DIMMs_registered;
 390
 391         /* Operational Mode Paramters */
 392
 393         /* Pick ECC modes */
 394         popts->ECC_mode = 0;              /* 0 = disabled, 1 = enabled */
 395 #ifdef CONFIG_DDR_ECC
 396         if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) {
 397                 if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf))
 398                         popts->ECC_mode = 1;
 399         } else
 400                 popts->ECC_mode = 1;
 401 #endif
 402         popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
 403
 404         /*
 405          * Choose DQS config
 406          * 0 for DDR1
 407          * 1 for DDR2
 408          */
 409 #if defined(CONFIG_FSL_DDR1)
 410         popts->DQS_config = 0;
 411 #elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
 412         popts->DQS_config = 1;
 413 #endif
 414
 415         /* Choose self-refresh during sleep. */
 416         popts->self_refresh_in_sleep = 1;
 417
 418         /* Choose dynamic power management mode. */
 419         popts->dynamic_power = 0;
 420
 421         /*
 422          * check first dimm for primary sdram width
 423          * presuming all dimms are similar
 424          * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
 425          */
 426 #if defined(CONFIG_FSL_DDR1) || defined(CONFIG_FSL_DDR2)
 427         if (pdimm[0].n_ranks != 0) {
 428                 if ((pdimm[0].data_width >= 64) && \
 429                         (pdimm[0].data_width <= 72))
 430                         popts->data_bus_width = 0;
 431                 else if ((pdimm[0].data_width >= 32) || \
 432                         (pdimm[0].data_width <= 40))
 433                         popts->data_bus_width = 1;
 434                 else {
 435                         panic("Error: data width %u is invalid!\n",
 436                                 pdimm[0].data_width);
 437                 }
 438         }
 439 #else
 440         if (pdimm[0].n_ranks != 0) {
 441                 if (pdimm[0].primary_sdram_width == 64)
 442                         popts->data_bus_width = 0;
 443                 else if (pdimm[0].primary_sdram_width == 32)
 444                         popts->data_bus_width = 1;
 445                 else if (pdimm[0].primary_sdram_width == 16)
 446                         popts->data_bus_width = 2;
 447                 else {
 448                         panic("Error: primary sdram width %u is invalid!\n",
 449                                 pdimm[0].primary_sdram_width);
 450                 }
 451         }
 452 #endif
 453
 454         /* Choose burst length. */
 455 #if defined(CONFIG_FSL_DDR3)
 456 #if defined(CONFIG_E500MC)
 457         popts->OTF_burst_chop_en = 0;   /* on-the-fly burst chop disable */
 458         popts->burst_length = DDR_BL8;  /* Fixed 8-beat burst len */
 459 #else
 460         if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) {
 461                 /* 32-bit or 16-bit bus */
 462                 popts->OTF_burst_chop_en = 0;
 463                 popts->burst_length = DDR_BL8;
 464         } else {
 465                 popts->OTF_burst_chop_en = 1;   /* on-the-fly burst chop */
 466                 popts->burst_length = DDR_OTF;  /* on-the-fly BC4 and BL8 */
 467         }
 468 #endif
 469 #else
 470         popts->burst_length = DDR_BL4;  /* has to be 4 for DDR2 */
 471 #endif
 472
 473         /* Choose ddr controller address mirror mode */
 474 #if defined(CONFIG_FSL_DDR3)
 475         popts->mirrored_dimm = pdimm[0].mirrored_dimm;
 476 #endif
 477
 478         /* Global Timing Parameters. */
 479         debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
 480
 481         /* Pick a caslat override. */
 482         popts->cas_latency_override = 0;
 483         popts->cas_latency_override_value = 3;
 484         if (popts->cas_latency_override) {
 485                 debug("using caslat override value = %u\n",
 486                        popts->cas_latency_override_value);
 487         }
 488
 489         /* Decide whether to use the computed derated latency */
 490         popts->use_derated_caslat = 0;
 491
 492         /* Choose an additive latency. */
 493         popts->additive_latency_override = 0;
 494         popts->additive_latency_override_value = 3;
 495         if (popts->additive_latency_override) {
 496                 debug("using additive latency override value = %u\n",
 497                        popts->additive_latency_override_value);
 498         }
 499
 500         /*
 501          * 2T_EN setting
 502          *
 503          * Factors to consider for 2T_EN:
 504          *      - number of DIMMs installed
 505          *      - number of components, number of active ranks
 506          *      - how much time you want to spend playing around
 507          */
 508         popts->twoT_en = 0;
 509         popts->threeT_en = 0;
 510
 511         /* for RDIMM, address parity enable */
 512         popts->ap_en = 1;
 513
 514         /*
 515          * BSTTOPRE precharge interval
 516          *
 517          * Set this to 0 for global auto precharge
 518          *
 519          * FIXME: Should this be configured in picoseconds?
 520          * Why it should be in ps:  better understanding of this
 521          * relative to actual DRAM timing parameters such as tRAS.
 522          * e.g. tRAS(min) = 40 ns
 523          */
 524         popts->bstopre = 0x100;
 525
 526         /* Minimum CKE pulse width -- tCKE(MIN) */
 527         popts->tCKE_clock_pulse_width_ps
 528                 = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
 529
 530         /*
 531          * Window for four activates -- tFAW
 532          *
 533          * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
 534          * FIXME: varies depending upon number of column addresses or data
 535          * FIXME: width, was considering looking at pdimm->primary_sdram_width
 536          */
 537 #if defined(CONFIG_FSL_DDR1)
 538         popts->tFAW_window_four_activates_ps = mclk_to_picos(1);
 539
 540 #elif defined(CONFIG_FSL_DDR2)
 541         /*
 542          * x4/x8;  some datasheets have 35000
 543          * x16 wide columns only?  Use 50000?
 544          */
 545         popts->tFAW_window_four_activates_ps = 37500;
 546
 547 #elif defined(CONFIG_FSL_DDR3)
 548         popts->tFAW_window_four_activates_ps = pdimm[0].tFAW_ps;
 549 #endif
 550         popts->zq_en = 0;
 551         popts->wrlvl_en = 0;
 552 #if defined(CONFIG_FSL_DDR3)
 553         /*
 554          * due to ddr3 dimm is fly-by topology
 555          * we suggest to enable write leveling to
 556          * meet the tQDSS under different loading.
 557          */
 558         popts->wrlvl_en = 1;
 559         popts->zq_en = 1;
 560         popts->wrlvl_override = 0;
 561 #endif
 562
 563         /*
 564          * Check interleaving configuration from environment.
 565          * Please refer to doc/README.fsl-ddr for the detail.
 566          *
 567          * If memory controller interleaving is enabled, then the data
 568          * bus widths must be programmed identically for all memory controllers.
 569          *
 570          * XXX: Attempt to set all controllers to the same chip select
 571          * interleaving mode. It will do a best effort to get the
 572          * requested ranks interleaved together such that the result
 573          * should be a subset of the requested configuration.
 574          */
 575 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
 576         if (hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf)) {
 577                 if (pdimm[0].n_ranks == 0) {
 578                         printf("There is no rank on CS0 for controller %d. Because only"
 579                                 " rank on CS0 and ranks chip-select interleaved with CS0"
 580                                 " are controller interleaved, force non memory "
 581                                 "controller interleaving\n", ctrl_num);
 582                         popts->memctl_interleaving = 0;
 583                 } else {
 584                         popts->memctl_interleaving = 1;
 585                         /*
 586                          * test null first. if CONFIG_HWCONFIG is not defined
 587                          * hwconfig_arg_cmp returns non-zero
 588                          */
 589                         if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
 590                                                     "null", buf)) {
 591                                 popts->memctl_interleaving = 0;
 592                                 debug("memory controller interleaving disabled.\n");
 593                         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
 594                                                          "ctlr_intlv",
 595                                                          "cacheline", buf))
 596                                 popts->memctl_interleaving_mode =
 597                                         FSL_DDR_CACHE_LINE_INTERLEAVING;
 598                         else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
 599                                                        "page", buf))
 600                                 popts->memctl_interleaving_mode =
 601                                         FSL_DDR_PAGE_INTERLEAVING;
 602                         else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
 603                                                        "bank", buf))
 604                                 popts->memctl_interleaving_mode =
 605                                         FSL_DDR_BANK_INTERLEAVING;
 606                         else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
 607                                                        "superbank", buf))
 608                                 popts->memctl_interleaving_mode =
 609                                         FSL_DDR_SUPERBANK_INTERLEAVING;
 610                         else {
 611                                 popts->memctl_interleaving = 0;
 612                                 printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
 613                         }
 614                 }
 615         }
 616 #endif
 617         if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
 618                 (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
 619                 /* test null first. if CONFIG_HWCONFIG is not defined,
 620                  * hwconfig_subarg_cmp_f returns non-zero */
 621                 if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 622                                             "null", buf))
 623                         debug("bank interleaving disabled.\n");
 624                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 625                                                  "cs0_cs1", buf))
 626                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
 627                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 628                                                  "cs2_cs3", buf))
 629                         popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
 630                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 631                                                  "cs0_cs1_and_cs2_cs3", buf))
 632                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
 633                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 634                                                  "cs0_cs1_cs2_cs3", buf))
 635                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
 636                 else
 637                         printf("hwconfig has unrecognized parameter for bank_intlv.\n");
 638                 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
 639                 case FSL_DDR_CS0_CS1_CS2_CS3:
 640 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
 641                         if (pdimm[0].n_ranks < 4) {
 642                                 popts->ba_intlv_ctl = 0;
 643                                 printf("Not enough bank(chip-select) for "
 644                                         "CS0+CS1+CS2+CS3 on controller %d, "
 645                                         "force non-interleaving!\n", ctrl_num);
 646                         }
 647 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
 648                         if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) {
 649                                 popts->ba_intlv_ctl = 0;
 650                                 printf("Not enough bank(chip-select) for "
 651                                         "CS0+CS1+CS2+CS3 on controller %d, "
 652                                         "force non-interleaving!\n", ctrl_num);
 653                         }
 654                         if (pdimm[0].capacity != pdimm[1].capacity) {
 655                                 popts->ba_intlv_ctl = 0;
 656                                 printf("Not identical DIMM size for "
 657                                         "CS0+CS1+CS2+CS3 on controller %d, "
 658                                         "force non-interleaving!\n", ctrl_num);
 659                         }
 660 #endif
 661                         break;
 662                 case FSL_DDR_CS0_CS1:
 663                         if (pdimm[0].n_ranks < 2) {
 664                                 popts->ba_intlv_ctl = 0;
 665                                 printf("Not enough bank(chip-select) for "
 666                                         "CS0+CS1 on controller %d, "
 667                                         "force non-interleaving!\n", ctrl_num);
 668                         }
 669                         break;
 670                 case FSL_DDR_CS2_CS3:
 671 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
 672                         if (pdimm[0].n_ranks < 4) {
 673                                 popts->ba_intlv_ctl = 0;
 674                                 printf("Not enough bank(chip-select) for CS2+CS3 "
 675                                         "on controller %d, force non-interleaving!\n", ctrl_num);
 676                         }
 677 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
 678                         if (pdimm[1].n_ranks < 2) {
 679                                 popts->ba_intlv_ctl = 0;
 680                                 printf("Not enough bank(chip-select) for CS2+CS3 "
 681                                         "on controller %d, force non-interleaving!\n", ctrl_num);
 682                         }
 683 #endif
 684                         break;
 685                 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 686 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
 687                         if (pdimm[0].n_ranks < 4) {
 688                                 popts->ba_intlv_ctl = 0;
 689                                 printf("Not enough bank(CS) for CS0+CS1 and "
 690                                         "CS2+CS3 on controller %d, "
 691                                         "force non-interleaving!\n", ctrl_num);
 692                         }
 693 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
 694                         if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) {
 695                                 popts->ba_intlv_ctl = 0;
 696                                 printf("Not enough bank(CS) for CS0+CS1 and "
 697                                         "CS2+CS3 on controller %d, "
 698                                         "force non-interleaving!\n", ctrl_num);
 699                         }
 700 #endif
 701                         break;
 702                 default:
 703                         popts->ba_intlv_ctl = 0;
 704                         break;
 705                 }
 706         }
 707
 708         if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) {
 709                 if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf))
 710                         popts->addr_hash = 0;
 711                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash",
 712                                                "true", buf))
 713                         popts->addr_hash = 1;
 714         }
 715
 716         if (pdimm[0].n_ranks == 4)
 717                 popts->quad_rank_present = 1;
 718
 719         fsl_ddr_board_options(popts, pdimm, ctrl_num);
 720
 721         return 0;
 722 }
 723
 724 void check_interleaving_options(fsl_ddr_info_t *pinfo)
 725 {
 726         int i, j, check_n_ranks, intlv_fixed = 0;
 727         unsigned long long check_rank_density;
 728         /*
 729          * Check if all controllers are configured for memory
 730          * controller interleaving. Identical dimms are recommended. At least
 731          * the size should be checked.
 732          */
 733         j = 0;
 734         check_n_ranks = pinfo->dimm_params[0][0].n_ranks;
 735         check_rank_density = pinfo->dimm_params[0][0].rank_density;
 736         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 737                 if ((pinfo->memctl_opts[i].memctl_interleaving) && \
 738                     (check_rank_density == pinfo->dimm_params[i][0].rank_density) && \
 739                     (check_n_ranks == pinfo->dimm_params[i][0].n_ranks)) {
 740                         j++;
 741                 }
 742         }
 743         if (j != CONFIG_NUM_DDR_CONTROLLERS) {
 744                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
 745                         if (pinfo->memctl_opts[i].memctl_interleaving) {
 746                                 pinfo->memctl_opts[i].memctl_interleaving = 0;
 747                                 intlv_fixed = 1;
 748                         }
 749                 if (intlv_fixed)
 750                         printf("Not all DIMMs are identical in size. "
 751                                 "Memory controller interleaving disabled.\n");
 752         }
 753 }
 754
 755 int fsl_use_spd(void)
 756 {
 757         int use_spd = 0;
 758
 759 #ifdef CONFIG_DDR_SPD
 760         char buffer[HWCONFIG_BUFFER_SIZE];
 761         char *buf = NULL;
 762
 763         /*
 764          * Extract hwconfig from environment since we have not properly setup
 765          * the environment but need it for ddr config params
 766          */
 767         if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
 768                 buf = buffer;
 769
 770         /* if hwconfig is not enabled, or "sdram" is not defined, use spd */
 771         if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) {
 772                 if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf))
 773                         use_spd = 1;
 774                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram",
 775                                                "fixed", buf))
 776                         use_spd = 0;
 777                 else
 778                         use_spd = 1;
 779         } else
 780                 use_spd = 1;
 781 #endif
 782
 783         return use_spd;
 784 }