2 * Copyright 2008-2012 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
5 * calculate the organization and timing parameter
6 * from ddr3 spd, please refer to the spec
7 * JEDEC standard No.21-C 4_01_02_11R18.pdf
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * Version 2 as published by the Free Software Foundation.
15 #include <asm/fsl_ddr_sdram.h>
20 * Calculate the Density of each Physical Rank.
21 * Returned size is in bytes.
24 * sdram capacity(bit) / 8 * primary bus width / sdram width
26 * where: sdram capacity = spd byte4[3:0]
27 * primary bus width = spd byte8[2:0]
28 * sdram width = spd byte7[2:0]
30 * SPD byte4 - sdram density and banks
31 * bit[3:0] size(bit) size(byte)
40 * SPD byte8 - module memory bus width
41 * bit[2:0] primary bus width
47 * SPD byte7 - module organiztion
48 * bit[2:0] sdram device width
55 static unsigned long long
56 compute_ranksize(const ddr3_spd_eeprom_t *spd)
58 unsigned long long bsize;
60 int nbit_sdram_cap_bsize = 0;
61 int nbit_primary_bus_width = 0;
62 int nbit_sdram_width = 0;
64 if ((spd->density_banks & 0xf) < 7)
65 nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28;
66 if ((spd->bus_width & 0x7) < 4)
67 nbit_primary_bus_width = (spd->bus_width & 0x7) + 3;
68 if ((spd->organization & 0x7) < 4)
69 nbit_sdram_width = (spd->organization & 0x7) + 2;
71 bsize = 1ULL << (nbit_sdram_cap_bsize - 3
72 + nbit_primary_bus_width - nbit_sdram_width);
74 debug("DDR: DDR III rank density = 0x%16llx\n", bsize);
80 * ddr_compute_dimm_parameters for DDR3 SPD
82 * Compute DIMM parameters based upon the SPD information in spd.
83 * Writes the results to the dimm_params_t structure pointed by pdimm.
87 ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
89 unsigned int dimm_number)
97 if (spd->mem_type != SPD_MEMTYPE_DDR3) {
98 printf("DIMM %u: is not a DDR3 SPD.\n", dimm_number);
102 memset(pdimm, 0, sizeof(dimm_params_t));
106 retval = ddr3_spd_check(spd);
108 printf("DIMM %u: failed checksum\n", dimm_number);
113 * The part name in ASCII in the SPD EEPROM is not null terminated.
114 * Guarantee null termination here by presetting all bytes to 0
115 * and copying the part name in ASCII from the SPD onto it
117 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
118 if ((spd->info_size_crc & 0xF) > 1)
119 memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
121 /* DIMM organization parameters */
122 pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1;
123 pdimm->rank_density = compute_ranksize(spd);
124 pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
125 pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7));
126 if ((spd->bus_width >> 3) & 0x3)
127 pdimm->ec_sdram_width = 8;
129 pdimm->ec_sdram_width = 0;
130 pdimm->data_width = pdimm->primary_sdram_width
131 + pdimm->ec_sdram_width;
133 /* These are the types defined by the JEDEC DDR3 SPD spec */
134 pdimm->mirrored_dimm = 0;
135 pdimm->registered_dimm = 0;
136 switch (spd->module_type & DDR3_SPD_MODULETYPE_MASK) {
137 case DDR3_SPD_MODULETYPE_RDIMM:
138 case DDR3_SPD_MODULETYPE_MINI_RDIMM:
139 case DDR3_SPD_MODULETYPE_72B_SO_RDIMM:
140 /* Registered/buffered DIMMs */
141 pdimm->registered_dimm = 1;
142 for (i = 0; i < 16; i += 2) {
143 u8 rcw = spd->mod_section.registered.rcw[i/2];
144 pdimm->rcw[i] = (rcw >> 0) & 0x0F;
145 pdimm->rcw[i+1] = (rcw >> 4) & 0x0F;
149 case DDR3_SPD_MODULETYPE_UDIMM:
150 case DDR3_SPD_MODULETYPE_SO_DIMM:
151 case DDR3_SPD_MODULETYPE_MICRO_DIMM:
152 case DDR3_SPD_MODULETYPE_MINI_UDIMM:
153 case DDR3_SPD_MODULETYPE_MINI_CDIMM:
154 case DDR3_SPD_MODULETYPE_72B_SO_UDIMM:
155 case DDR3_SPD_MODULETYPE_72B_SO_CDIMM:
156 case DDR3_SPD_MODULETYPE_LRDIMM:
157 case DDR3_SPD_MODULETYPE_16B_SO_DIMM:
158 case DDR3_SPD_MODULETYPE_32B_SO_DIMM:
159 /* Unbuffered DIMMs */
160 if (spd->mod_section.unbuffered.addr_mapping & 0x1)
161 pdimm->mirrored_dimm = 1;
165 printf("unknown module_type 0x%02X\n", spd->module_type);
169 /* SDRAM device parameters */
170 pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12;
171 pdimm->n_col_addr = (spd->addressing & 0x7) + 9;
172 pdimm->n_banks_per_sdram_device = 8 << ((spd->density_banks >> 4) & 0x7);
175 * The SPD spec has not the ECC bit,
176 * We consider the DIMM as ECC capability
177 * when the extension bus exist
179 if (pdimm->ec_sdram_width)
180 pdimm->edc_config = 0x02;
182 pdimm->edc_config = 0x00;
185 * The SPD spec has not the burst length byte
186 * but DDR3 spec has nature BL8 and BC4,
187 * BL8 -bit3, BC4 -bit2
189 pdimm->burst_lengths_bitmask = 0x0c;
190 pdimm->row_density = __ilog2(pdimm->rank_density);
192 /* MTB - medium timebase
193 * The unit in the SPD spec is ns,
194 * We convert it to ps.
195 * eg: MTB = 0.125ns (125ps)
197 mtb_ps = (spd->mtb_dividend * 1000) /spd->mtb_divisor;
198 pdimm->mtb_ps = mtb_ps;
201 * FTB - fine timebase
202 * use 1/10th of ps as our unit to avoid floating point
203 * eg, 10 for 1ps, 25 for 2.5ps, 50 for 5ps
206 ((spd->ftb_div & 0xf0) >> 4) * 10 / (spd->ftb_div & 0x0f);
207 pdimm->ftb_10th_ps = ftb_10th_ps;
209 * sdram minimum cycle time
210 * we assume the MTB is 0.125ns
212 * tCK_min=15 MTB (1.875ns) ->DDR3-1066
213 * =12 MTB (1.5ns) ->DDR3-1333
214 * =10 MTB (1.25ns) ->DDR3-1600
216 pdimm->tCKmin_X_ps = spd->tCK_min * mtb_ps +
217 (spd->fine_tCK_min * ftb_10th_ps) / 10;
220 * CAS latency supported
225 pdimm->caslat_X = ((spd->caslat_msb << 8) | spd->caslat_lsb) << 4;
228 * min CAS latency time
230 * DDR3-800D 100 MTB (12.5ns)
231 * DDR3-1066F 105 MTB (13.125ns)
232 * DDR3-1333H 108 MTB (13.5ns)
233 * DDR3-1600H 90 MTB (11.25ns)
235 pdimm->tAA_ps = spd->tAA_min * mtb_ps +
236 (spd->fine_tAA_min * ftb_10th_ps) / 10;
239 * min write recovery time
241 * tWR_min = 120 MTB (15ns) -> all speed grades.
243 pdimm->tWR_ps = spd->tWR_min * mtb_ps;
246 * min RAS to CAS delay time
248 * DDR3-800 100 MTB (12.5ns)
249 * DDR3-1066F 105 MTB (13.125ns)
250 * DDR3-1333H 108 MTB (13.5ns)
251 * DDR3-1600H 90 MTB (11.25)
253 pdimm->tRCD_ps = spd->tRCD_min * mtb_ps +
254 (spd->fine_tRCD_min * ftb_10th_ps) / 10;
257 * min row active to row active delay time
259 * DDR3-800(1KB page) 80 MTB (10ns)
260 * DDR3-1333(1KB page) 48 MTB (6ns)
262 pdimm->tRRD_ps = spd->tRRD_min * mtb_ps;
265 * min row precharge delay time
267 * DDR3-800D 100 MTB (12.5ns)
268 * DDR3-1066F 105 MTB (13.125ns)
269 * DDR3-1333H 108 MTB (13.5ns)
270 * DDR3-1600H 90 MTB (11.25ns)
272 pdimm->tRP_ps = spd->tRP_min * mtb_ps +
273 (spd->fine_tRP_min * ftb_10th_ps) / 10;
275 /* min active to precharge delay time
277 * DDR3-800D 300 MTB (37.5ns)
278 * DDR3-1066F 300 MTB (37.5ns)
279 * DDR3-1333H 288 MTB (36ns)
280 * DDR3-1600H 280 MTB (35ns)
282 pdimm->tRAS_ps = (((spd->tRAS_tRC_ext & 0xf) << 8) | spd->tRAS_min_lsb)
285 * min active to actice/refresh delay time
287 * DDR3-800D 400 MTB (50ns)
288 * DDR3-1066F 405 MTB (50.625ns)
289 * DDR3-1333H 396 MTB (49.5ns)
290 * DDR3-1600H 370 MTB (46.25ns)
292 pdimm->tRC_ps = (((spd->tRAS_tRC_ext & 0xf0) << 4) | spd->tRC_min_lsb)
293 * mtb_ps + (spd->fine_tRC_min * ftb_10th_ps) / 10;
295 * min refresh recovery delay time
297 * 512Mb 720 MTB (90ns)
298 * 1Gb 880 MTB (110ns)
299 * 2Gb 1280 MTB (160ns)
301 pdimm->tRFC_ps = ((spd->tRFC_min_msb << 8) | spd->tRFC_min_lsb)
304 * min internal write to read command delay time
305 * eg: tWTR_min = 40 MTB (7.5ns) - all speed bins.
306 * tWRT is at least 4 mclk independent of operating freq.
308 pdimm->tWTR_ps = spd->tWTR_min * mtb_ps;
311 * min internal read to precharge command delay time
312 * eg: tRTP_min = 40 MTB (7.5ns) - all speed bins.
313 * tRTP is at least 4 mclk independent of operating freq.
315 pdimm->tRTP_ps = spd->tRTP_min * mtb_ps;
318 * Average periodic refresh interval
319 * tREFI = 7.8 us at normal temperature range
320 * = 3.9 us at ext temperature range
322 pdimm->refresh_rate_ps = 7800000;
325 * min four active window delay time
327 * DDR3-800(1KB page) 320 MTB (40ns)
328 * DDR3-1066(1KB page) 300 MTB (37.5ns)
329 * DDR3-1333(1KB page) 240 MTB (30ns)
330 * DDR3-1600(1KB page) 240 MTB (30ns)
332 pdimm->tFAW_ps = (((spd->tFAW_msb & 0xf) << 8) | spd->tFAW_min)