arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c

   1 /*
   2  * Copyright 2008-2011 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the Free
   6  * Software Foundation; either version 2 of the License, or (at your option)
   7  * any later version.
   8  */
   9
  10 /*
  11  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
  12  * Based on code from spd_sdram.c
  13  * Author: James Yang [at freescale.com]
  14  */
  15
  16 #include <common.h>
  17 #include <asm/fsl_ddr_sdram.h>
  18
  19 #include "ddr.h"
  20
  21 #ifdef CONFIG_MPC85xx
  22         #define _DDR_ADDR CONFIG_SYS_MPC85xx_DDR_ADDR
  23 #elif defined(CONFIG_MPC86xx)
  24         #define _DDR_ADDR CONFIG_SYS_MPC86xx_DDR_ADDR
  25 #else
  26         #error "Undefined _DDR_ADDR"
  27 #endif
  28
  29 u32 fsl_ddr_get_version(void)
  30 {
  31         ccsr_ddr_t *ddr;
  32         u32 ver_major_minor_errata;
  33
  34         ddr = (void *)_DDR_ADDR;
  35         ver_major_minor_errata = (in_be32(&ddr->ip_rev1) & 0xFFFF) << 8;
  36         ver_major_minor_errata |= (in_be32(&ddr->ip_rev2) & 0xFF00) >> 8;
  37
  38         return ver_major_minor_errata;
  39 }
  40
  41 unsigned int picos_to_mclk(unsigned int picos);
  42
  43 /*
  44  * Determine Rtt value.
  45  *
  46  * This should likely be either board or controller specific.
  47  *
  48  * Rtt(nominal) - DDR2:
  49  *      0 = Rtt disabled
  50  *      1 = 75 ohm
  51  *      2 = 150 ohm
  52  *      3 = 50 ohm
  53  * Rtt(nominal) - DDR3:
  54  *      0 = Rtt disabled
  55  *      1 = 60 ohm
  56  *      2 = 120 ohm
  57  *      3 = 40 ohm
  58  *      4 = 20 ohm
  59  *      5 = 30 ohm
  60  *
  61  * FIXME: Apparently 8641 needs a value of 2
  62  * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
  63  *
  64  * FIXME: There was some effort down this line earlier:
  65  *
  66  *      unsigned int i;
  67  *      for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
  68  *              if (popts->dimmslot[i].num_valid_cs
  69  *                  && (popts->cs_local_opts[2*i].odt_rd_cfg
  70  *                      || popts->cs_local_opts[2*i].odt_wr_cfg)) {
  71  *                      rtt = 2;
  72  *                      break;
  73  *              }
  74  *      }
  75  */
  76 static inline int fsl_ddr_get_rtt(void)
  77 {
  78         int rtt;
  79
  80 #if defined(CONFIG_FSL_DDR1)
  81         rtt = 0;
  82 #elif defined(CONFIG_FSL_DDR2)
  83         rtt = 3;
  84 #else
  85         rtt = 0;
  86 #endif
  87
  88         return rtt;
  89 }
  90
  91 /*
  92  * compute the CAS write latency according to DDR3 spec
  93  * CWL = 5 if tCK >= 2.5ns
  94  *       6 if 2.5ns > tCK >= 1.875ns
  95  *       7 if 1.875ns > tCK >= 1.5ns
  96  *       8 if 1.5ns > tCK >= 1.25ns
  97  */
  98 static inline unsigned int compute_cas_write_latency(void)
  99 {
 100         unsigned int cwl;
 101         const unsigned int mclk_ps = get_memory_clk_period_ps();
 102
 103         if (mclk_ps >= 2500)
 104                 cwl = 5;
 105         else if (mclk_ps >= 1875)
 106                 cwl = 6;
 107         else if (mclk_ps >= 1500)
 108                 cwl = 7;
 109         else if (mclk_ps >= 1250)
 110                 cwl = 8;
 111         else
 112                 cwl = 8;
 113         return cwl;
 114 }
 115
 116 /* Chip Select Configuration (CSn_CONFIG) */
 117 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
 118                                const memctl_options_t *popts,
 119                                const dimm_params_t *dimm_params)
 120 {
 121         unsigned int cs_n_en = 0; /* Chip Select enable */
 122         unsigned int intlv_en = 0; /* Memory controller interleave enable */
 123         unsigned int intlv_ctl = 0; /* Interleaving control */
 124         unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
 125         unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
 126         unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
 127         unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
 128         unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
 129         unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
 130         int go_config = 0;
 131
 132         /* Compute CS_CONFIG only for existing ranks of each DIMM.  */
 133         switch (i) {
 134         case 0:
 135                 if (dimm_params[dimm_number].n_ranks > 0) {
 136                         go_config = 1;
 137                         /* These fields only available in CS0_CONFIG */
 138                         intlv_en = popts->memctl_interleaving;
 139                         intlv_ctl = popts->memctl_interleaving_mode;
 140                 }
 141                 break;
 142         case 1:
 143                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
 144                     (dimm_number == 1 && dimm_params[1].n_ranks > 0))
 145                         go_config = 1;
 146                 break;
 147         case 2:
 148                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
 149                    (dimm_number > 1 && dimm_params[dimm_number].n_ranks > 0))
 150                         go_config = 1;
 151                 break;
 152         case 3:
 153                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
 154                     (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
 155                     (dimm_number == 3 && dimm_params[3].n_ranks > 0))
 156                         go_config = 1;
 157                 break;
 158         default:
 159                 break;
 160         }
 161         if (go_config) {
 162                 unsigned int n_banks_per_sdram_device;
 163                 cs_n_en = 1;
 164                 ap_n_en = popts->cs_local_opts[i].auto_precharge;
 165                 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
 166                 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
 167                 n_banks_per_sdram_device
 168                         = dimm_params[dimm_number].n_banks_per_sdram_device;
 169                 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
 170                 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
 171                 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
 172         }
 173         ddr->cs[i].config = (0
 174                 | ((cs_n_en & 0x1) << 31)
 175                 | ((intlv_en & 0x3) << 29)
 176                 | ((intlv_ctl & 0xf) << 24)
 177                 | ((ap_n_en & 0x1) << 23)
 178
 179                 /* XXX: some implementation only have 1 bit starting at left */
 180                 | ((odt_rd_cfg & 0x7) << 20)
 181
 182                 /* XXX: Some implementation only have 1 bit starting at left */
 183                 | ((odt_wr_cfg & 0x7) << 16)
 184
 185                 | ((ba_bits_cs_n & 0x3) << 14)
 186                 | ((row_bits_cs_n & 0x7) << 8)
 187                 | ((col_bits_cs_n & 0x7) << 0)
 188                 );
 189         debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
 190 }
 191
 192 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
 193 /* FIXME: 8572 */
 194 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
 195 {
 196         unsigned int pasr_cfg = 0;      /* Partial array self refresh config */
 197
 198         ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
 199         debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
 200 }
 201
 202 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
 203
 204 #if !defined(CONFIG_FSL_DDR1)
 205 /*
 206  * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
 207  *
 208  * Avoid writing for DDR I.  The new PQ38 DDR controller
 209  * dreams up non-zero default values to be backwards compatible.
 210  */
 211 static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
 212                                 const memctl_options_t *popts)
 213 {
 214         unsigned char trwt_mclk = 0;   /* Read-to-write turnaround */
 215         unsigned char twrt_mclk = 0;   /* Write-to-read turnaround */
 216         /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
 217         unsigned char trrt_mclk = 0;   /* Read-to-read turnaround */
 218         unsigned char twwt_mclk = 0;   /* Write-to-write turnaround */
 219
 220         /* Active powerdown exit timing (tXARD and tXARDS). */
 221         unsigned char act_pd_exit_mclk;
 222         /* Precharge powerdown exit timing (tXP). */
 223         unsigned char pre_pd_exit_mclk;
 224         /* ODT powerdown exit timing (tAXPD). */
 225         unsigned char taxpd_mclk;
 226         /* Mode register set cycle time (tMRD). */
 227         unsigned char tmrd_mclk;
 228
 229 #ifdef CONFIG_FSL_DDR3
 230         /*
 231          * (tXARD and tXARDS). Empirical?
 232          * The DDR3 spec has not tXARD,
 233          * we use the tXP instead of it.
 234          * tXP=max(3nCK, 7.5ns) for DDR3.
 235          * spec has not the tAXPD, we use
 236          * tAXPD=1, need design to confirm.
 237          */
 238         int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
 239         unsigned int data_rate = get_ddr_freq(0);
 240         tmrd_mclk = 4;
 241         /* set the turnaround time */
 242         trwt_mclk = 1;
 243         if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
 244                 twrt_mclk = 1;
 245
 246         if (popts->dynamic_power == 0) {        /* powerdown is not used */
 247                 act_pd_exit_mclk = 1;
 248                 pre_pd_exit_mclk = 1;
 249                 taxpd_mclk = 1;
 250         } else {
 251                 /* act_pd_exit_mclk = tXARD, see above */
 252                 act_pd_exit_mclk = picos_to_mclk(tXP);
 253                 /* Mode register MR0[A12] is '1' - fast exit */
 254                 pre_pd_exit_mclk = act_pd_exit_mclk;
 255                 taxpd_mclk = 1;
 256         }
 257 #else /* CONFIG_FSL_DDR2 */
 258         /*
 259          * (tXARD and tXARDS). Empirical?
 260          * tXARD = 2 for DDR2
 261          * tXP=2
 262          * tAXPD=8
 263          */
 264         act_pd_exit_mclk = 2;
 265         pre_pd_exit_mclk = 2;
 266         taxpd_mclk = 8;
 267         tmrd_mclk = 2;
 268 #endif
 269
 270         if (popts->trwt_override)
 271                 trwt_mclk = popts->trwt;
 272
 273         ddr->timing_cfg_0 = (0
 274                 | ((trwt_mclk & 0x3) << 30)     /* RWT */
 275                 | ((twrt_mclk & 0x3) << 28)     /* WRT */
 276                 | ((trrt_mclk & 0x3) << 26)     /* RRT */
 277                 | ((twwt_mclk & 0x3) << 24)     /* WWT */
 278                 | ((act_pd_exit_mclk & 0x7) << 20)  /* ACT_PD_EXIT */
 279                 | ((pre_pd_exit_mclk & 0xF) << 16)  /* PRE_PD_EXIT */
 280                 | ((taxpd_mclk & 0xf) << 8)     /* ODT_PD_EXIT */
 281                 | ((tmrd_mclk & 0xf) << 0)      /* MRS_CYC */
 282                 );
 283         debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
 284 }
 285 #endif  /* defined(CONFIG_FSL_DDR2) */
 286
 287 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
 288 static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
 289                                const common_timing_params_t *common_dimm,
 290                                unsigned int cas_latency)
 291 {
 292         /* Extended Activate to precharge interval (tRAS) */
 293         unsigned int ext_acttopre = 0;
 294         unsigned int ext_refrec; /* Extended refresh recovery time (tRFC) */
 295         unsigned int ext_caslat = 0; /* Extended MCAS latency from READ cmd */
 296         unsigned int cntl_adj = 0; /* Control Adjust */
 297
 298         /* If the tRAS > 19 MCLK, we use the ext mode */
 299         if (picos_to_mclk(common_dimm->tRAS_ps) > 0x13)
 300                 ext_acttopre = 1;
 301
 302         ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4;
 303
 304         /* If the CAS latency more than 8, use the ext mode */
 305         if (cas_latency > 8)
 306                 ext_caslat = 1;
 307
 308         ddr->timing_cfg_3 = (0
 309                 | ((ext_acttopre & 0x1) << 24)
 310                 | ((ext_refrec & 0xF) << 16)
 311                 | ((ext_caslat & 0x1) << 12)
 312                 | ((cntl_adj & 0x7) << 0)
 313                 );
 314         debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
 315 }
 316
 317 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
 318 static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
 319                                const memctl_options_t *popts,
 320                                const common_timing_params_t *common_dimm,
 321                                unsigned int cas_latency)
 322 {
 323         /* Precharge-to-activate interval (tRP) */
 324         unsigned char pretoact_mclk;
 325         /* Activate to precharge interval (tRAS) */
 326         unsigned char acttopre_mclk;
 327         /*  Activate to read/write interval (tRCD) */
 328         unsigned char acttorw_mclk;
 329         /* CASLAT */
 330         unsigned char caslat_ctrl;
 331         /*  Refresh recovery time (tRFC) ; trfc_low */
 332         unsigned char refrec_ctrl;
 333         /* Last data to precharge minimum interval (tWR) */
 334         unsigned char wrrec_mclk;
 335         /* Activate-to-activate interval (tRRD) */
 336         unsigned char acttoact_mclk;
 337         /* Last write data pair to read command issue interval (tWTR) */
 338         unsigned char wrtord_mclk;
 339         /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
 340         static const u8 wrrec_table[] = {
 341                 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
 342
 343         pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps);
 344         acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps);
 345         acttorw_mclk = picos_to_mclk(common_dimm->tRCD_ps);
 346
 347         /*
 348          * Translate CAS Latency to a DDR controller field value:
 349          *
 350          *      CAS Lat DDR I   DDR II  Ctrl
 351          *      Clocks  SPD Bit SPD Bit Value
 352          *      ------- ------- ------- -----
 353          *      1.0     0               0001
 354          *      1.5     1               0010
 355          *      2.0     2       2       0011
 356          *      2.5     3               0100
 357          *      3.0     4       3       0101
 358          *      3.5     5               0110
 359          *      4.0             4       0111
 360          *      4.5                     1000
 361          *      5.0             5       1001
 362          */
 363 #if defined(CONFIG_FSL_DDR1)
 364         caslat_ctrl = (cas_latency + 1) & 0x07;
 365 #elif defined(CONFIG_FSL_DDR2)
 366         caslat_ctrl = 2 * cas_latency - 1;
 367 #else
 368         /*
 369          * if the CAS latency more than 8 cycle,
 370          * we need set extend bit for it at
 371          * TIMING_CFG_3[EXT_CASLAT]
 372          */
 373         if (cas_latency > 8)
 374                 cas_latency -= 8;
 375         caslat_ctrl = 2 * cas_latency - 1;
 376 #endif
 377
 378         refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8;
 379         wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps);
 380
 381         wrrec_mclk = wrrec_table[wrrec_mclk - 1];
 382         if (popts->OTF_burst_chop_en)
 383                 wrrec_mclk += 2;
 384
 385         acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps);
 386         /*
 387          * JEDEC has min requirement for tRRD
 388          */
 389 #if defined(CONFIG_FSL_DDR3)
 390         if (acttoact_mclk < 4)
 391                 acttoact_mclk = 4;
 392 #endif
 393         wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps);
 394         /*
 395          * JEDEC has some min requirements for tWTR
 396          */
 397 #if defined(CONFIG_FSL_DDR2)
 398         if (wrtord_mclk < 2)
 399                 wrtord_mclk = 2;
 400 #elif defined(CONFIG_FSL_DDR3)
 401         if (wrtord_mclk < 4)
 402                 wrtord_mclk = 4;
 403 #endif
 404         if (popts->OTF_burst_chop_en)
 405                 wrtord_mclk += 2;
 406
 407         ddr->timing_cfg_1 = (0
 408                 | ((pretoact_mclk & 0x0F) << 28)
 409                 | ((acttopre_mclk & 0x0F) << 24)
 410                 | ((acttorw_mclk & 0xF) << 20)
 411                 | ((caslat_ctrl & 0xF) << 16)
 412                 | ((refrec_ctrl & 0xF) << 12)
 413                 | ((wrrec_mclk & 0x0F) << 8)
 414                 | ((acttoact_mclk & 0x07) << 4)
 415                 | ((wrtord_mclk & 0x07) << 0)
 416                 );
 417         debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
 418 }
 419
 420 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
 421 static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 422                                const memctl_options_t *popts,
 423                                const common_timing_params_t *common_dimm,
 424                                unsigned int cas_latency,
 425                                unsigned int additive_latency)
 426 {
 427         /* Additive latency */
 428         unsigned char add_lat_mclk;
 429         /* CAS-to-preamble override */
 430         unsigned short cpo;
 431         /* Write latency */
 432         unsigned char wr_lat;
 433         /*  Read to precharge (tRTP) */
 434         unsigned char rd_to_pre;
 435         /* Write command to write data strobe timing adjustment */
 436         unsigned char wr_data_delay;
 437         /* Minimum CKE pulse width (tCKE) */
 438         unsigned char cke_pls;
 439         /* Window for four activates (tFAW) */
 440         unsigned short four_act;
 441
 442         /* FIXME add check that this must be less than acttorw_mclk */
 443         add_lat_mclk = additive_latency;
 444         cpo = popts->cpo_override;
 445
 446 #if defined(CONFIG_FSL_DDR1)
 447         /*
 448          * This is a lie.  It should really be 1, but if it is
 449          * set to 1, bits overlap into the old controller's
 450          * otherwise unused ACSM field.  If we leave it 0, then
 451          * the HW will magically treat it as 1 for DDR 1.  Oh Yea.
 452          */
 453         wr_lat = 0;
 454 #elif defined(CONFIG_FSL_DDR2)
 455         wr_lat = cas_latency - 1;
 456 #else
 457         wr_lat = compute_cas_write_latency();
 458 #endif
 459
 460         rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps);
 461         /*
 462          * JEDEC has some min requirements for tRTP
 463          */
 464 #if defined(CONFIG_FSL_DDR2)
 465         if (rd_to_pre  < 2)
 466                 rd_to_pre  = 2;
 467 #elif defined(CONFIG_FSL_DDR3)
 468         if (rd_to_pre < 4)
 469                 rd_to_pre = 4;
 470 #endif
 471         if (additive_latency)
 472                 rd_to_pre += additive_latency;
 473         if (popts->OTF_burst_chop_en)
 474                 rd_to_pre += 2; /* according to UM */
 475
 476         wr_data_delay = popts->write_data_delay;
 477         cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps);
 478         four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
 479
 480         ddr->timing_cfg_2 = (0
 481                 | ((add_lat_mclk & 0xf) << 28)
 482                 | ((cpo & 0x1f) << 23)
 483                 | ((wr_lat & 0xf) << 19)
 484                 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
 485                 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
 486                 | ((cke_pls & 0x7) << 6)
 487                 | ((four_act & 0x3f) << 0)
 488                 );
 489         debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
 490 }
 491
 492 /* DDR SDRAM Register Control Word */
 493 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
 494                                const memctl_options_t *popts,
 495                                const common_timing_params_t *common_dimm)
 496 {
 497         if (common_dimm->all_DIMMs_registered
 498                 && !common_dimm->all_DIMMs_unbuffered) {
 499                 if (popts->rcw_override) {
 500                         ddr->ddr_sdram_rcw_1 = popts->rcw_1;
 501                         ddr->ddr_sdram_rcw_2 = popts->rcw_2;
 502                 } else {
 503                         ddr->ddr_sdram_rcw_1 =
 504                                 common_dimm->rcw[0] << 28 | \
 505                                 common_dimm->rcw[1] << 24 | \
 506                                 common_dimm->rcw[2] << 20 | \
 507                                 common_dimm->rcw[3] << 16 | \
 508                                 common_dimm->rcw[4] << 12 | \
 509                                 common_dimm->rcw[5] << 8 | \
 510                                 common_dimm->rcw[6] << 4 | \
 511                                 common_dimm->rcw[7];
 512                         ddr->ddr_sdram_rcw_2 =
 513                                 common_dimm->rcw[8] << 28 | \
 514                                 common_dimm->rcw[9] << 24 | \
 515                                 common_dimm->rcw[10] << 20 | \
 516                                 common_dimm->rcw[11] << 16 | \
 517                                 common_dimm->rcw[12] << 12 | \
 518                                 common_dimm->rcw[13] << 8 | \
 519                                 common_dimm->rcw[14] << 4 | \
 520                                 common_dimm->rcw[15];
 521                 }
 522                 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
 523                 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
 524         }
 525 }
 526
 527 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
 528 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 529                                const memctl_options_t *popts,
 530                                const common_timing_params_t *common_dimm)
 531 {
 532         unsigned int mem_en;            /* DDR SDRAM interface logic enable */
 533         unsigned int sren;              /* Self refresh enable (during sleep) */
 534         unsigned int ecc_en;            /* ECC enable. */
 535         unsigned int rd_en;             /* Registered DIMM enable */
 536         unsigned int sdram_type;        /* Type of SDRAM */
 537         unsigned int dyn_pwr;           /* Dynamic power management mode */
 538         unsigned int dbw;               /* DRAM dta bus width */
 539         unsigned int eight_be = 0;      /* 8-beat burst enable, DDR2 is zero */
 540         unsigned int ncap = 0;          /* Non-concurrent auto-precharge */
 541         unsigned int threeT_en;         /* Enable 3T timing */
 542         unsigned int twoT_en;           /* Enable 2T timing */
 543         unsigned int ba_intlv_ctl;      /* Bank (CS) interleaving control */
 544         unsigned int x32_en = 0;        /* x32 enable */
 545         unsigned int pchb8 = 0;         /* precharge bit 8 enable */
 546         unsigned int hse;               /* Global half strength override */
 547         unsigned int mem_halt = 0;      /* memory controller halt */
 548         unsigned int bi = 0;            /* Bypass initialization */
 549
 550         mem_en = 1;
 551         sren = popts->self_refresh_in_sleep;
 552         if (common_dimm->all_DIMMs_ECC_capable) {
 553                 /* Allow setting of ECC only if all DIMMs are ECC. */
 554                 ecc_en = popts->ECC_mode;
 555         } else {
 556                 ecc_en = 0;
 557         }
 558
 559         if (common_dimm->all_DIMMs_registered
 560                 && !common_dimm->all_DIMMs_unbuffered) {
 561                 rd_en = 1;
 562                 twoT_en = 0;
 563         } else {
 564                 rd_en = 0;
 565                 twoT_en = popts->twoT_en;
 566         }
 567
 568         sdram_type = CONFIG_FSL_SDRAM_TYPE;
 569
 570         dyn_pwr = popts->dynamic_power;
 571         dbw = popts->data_bus_width;
 572         /* 8-beat burst enable DDR-III case
 573          * we must clear it when use the on-the-fly mode,
 574          * must set it when use the 32-bits bus mode.
 575          */
 576         if (sdram_type == SDRAM_TYPE_DDR3) {
 577                 if (popts->burst_length == DDR_BL8)
 578                         eight_be = 1;
 579                 if (popts->burst_length == DDR_OTF)
 580                         eight_be = 0;
 581                 if (dbw == 0x1)
 582                         eight_be = 1;
 583         }
 584
 585         threeT_en = popts->threeT_en;
 586         ba_intlv_ctl = popts->ba_intlv_ctl;
 587         hse = popts->half_strength_driver_enable;
 588
 589         ddr->ddr_sdram_cfg = (0
 590                         | ((mem_en & 0x1) << 31)
 591                         | ((sren & 0x1) << 30)
 592                         | ((ecc_en & 0x1) << 29)
 593                         | ((rd_en & 0x1) << 28)
 594                         | ((sdram_type & 0x7) << 24)
 595                         | ((dyn_pwr & 0x1) << 21)
 596                         | ((dbw & 0x3) << 19)
 597                         | ((eight_be & 0x1) << 18)
 598                         | ((ncap & 0x1) << 17)
 599                         | ((threeT_en & 0x1) << 16)
 600                         | ((twoT_en & 0x1) << 15)
 601                         | ((ba_intlv_ctl & 0x7F) << 8)
 602                         | ((x32_en & 0x1) << 5)
 603                         | ((pchb8 & 0x1) << 4)
 604                         | ((hse & 0x1) << 3)
 605                         | ((mem_halt & 0x1) << 1)
 606                         | ((bi & 0x1) << 0)
 607                         );
 608         debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
 609 }
 610
 611 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
 612 static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 613                                const memctl_options_t *popts,
 614                                const unsigned int unq_mrs_en)
 615 {
 616         unsigned int frc_sr = 0;        /* Force self refresh */
 617         unsigned int sr_ie = 0;         /* Self-refresh interrupt enable */
 618         unsigned int dll_rst_dis;       /* DLL reset disable */
 619         unsigned int dqs_cfg;           /* DQS configuration */
 620         unsigned int odt_cfg;           /* ODT configuration */
 621         unsigned int num_pr;            /* Number of posted refreshes */
 622         unsigned int obc_cfg;           /* On-The-Fly Burst Chop Cfg */
 623         unsigned int ap_en;             /* Address Parity Enable */
 624         unsigned int d_init;            /* DRAM data initialization */
 625         unsigned int rcw_en = 0;        /* Register Control Word Enable */
 626         unsigned int md_en = 0;         /* Mirrored DIMM Enable */
 627         unsigned int qd_en = 0;         /* quad-rank DIMM Enable */
 628
 629         dll_rst_dis = 1;        /* Make this configurable */
 630         dqs_cfg = popts->DQS_config;
 631         if (popts->cs_local_opts[0].odt_rd_cfg
 632             || popts->cs_local_opts[0].odt_wr_cfg) {
 633                 /* FIXME */
 634                 odt_cfg = 2;
 635         } else {
 636                 odt_cfg = 0;
 637         }
 638
 639         num_pr = 1;     /* Make this configurable */
 640
 641         /*
 642          * 8572 manual says
 643          *     {TIMING_CFG_1[PRETOACT]
 644          *      + [DDR_SDRAM_CFG_2[NUM_PR]
 645          *        * ({EXT_REFREC || REFREC} + 8 + 2)]}
 646          *      << DDR_SDRAM_INTERVAL[REFINT]
 647          */
 648 #if defined(CONFIG_FSL_DDR3)
 649         obc_cfg = popts->OTF_burst_chop_en;
 650 #else
 651         obc_cfg = 0;
 652 #endif
 653
 654         if (popts->registered_dimm_en) {
 655                 rcw_en = 1;
 656                 ap_en = popts->ap_en;
 657         } else {
 658                 rcw_en = 0;
 659                 ap_en = 0;
 660         }
 661
 662 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 663         /* Use the DDR controller to auto initialize memory. */
 664         d_init = popts->ECC_init_using_memctl;
 665         ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
 666         debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
 667 #else
 668         /* Memory will be initialized via DMA, or not at all. */
 669         d_init = 0;
 670 #endif
 671
 672 #if defined(CONFIG_FSL_DDR3)
 673         md_en = popts->mirrored_dimm;
 674 #endif
 675         qd_en = popts->quad_rank_present ? 1 : 0;
 676         ddr->ddr_sdram_cfg_2 = (0
 677                 | ((frc_sr & 0x1) << 31)
 678                 | ((sr_ie & 0x1) << 30)
 679                 | ((dll_rst_dis & 0x1) << 29)
 680                 | ((dqs_cfg & 0x3) << 26)
 681                 | ((odt_cfg & 0x3) << 21)
 682                 | ((num_pr & 0xf) << 12)
 683                 | (qd_en << 9)
 684                 | (unq_mrs_en << 8)
 685                 | ((obc_cfg & 0x1) << 6)
 686                 | ((ap_en & 0x1) << 5)
 687                 | ((d_init & 0x1) << 4)
 688 #ifdef CONFIG_FSL_DDR3
 689                 | ((rcw_en & 0x1) << 2)
 690 #endif
 691                 | ((md_en & 0x1) << 0)
 692                 );
 693         debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
 694 }
 695
 696 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
 697 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
 698                                 const memctl_options_t *popts,
 699                                 const unsigned int unq_mrs_en)
 700 {
 701         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
 702         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
 703
 704 #if defined(CONFIG_FSL_DDR3)
 705         int i;
 706         unsigned int rtt_wr = 0;        /* Rtt_WR - dynamic ODT off */
 707         unsigned int srt = 0;   /* self-refresh temerature, normal range */
 708         unsigned int asr = 0;   /* auto self-refresh disable */
 709         unsigned int cwl = compute_cas_write_latency() - 5;
 710         unsigned int pasr = 0;  /* partial array self refresh disable */
 711
 712         if (popts->rtt_override)
 713                 rtt_wr = popts->rtt_wr_override_value;
 714         else
 715                 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
 716         esdmode2 = (0
 717                 | ((rtt_wr & 0x3) << 9)
 718                 | ((srt & 0x1) << 7)
 719                 | ((asr & 0x1) << 6)
 720                 | ((cwl & 0x7) << 3)
 721                 | ((pasr & 0x7) << 0));
 722 #endif
 723         ddr->ddr_sdram_mode_2 = (0
 724                                  | ((esdmode2 & 0xFFFF) << 16)
 725                                  | ((esdmode3 & 0xFFFF) << 0)
 726                                  );
 727         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
 728
 729 #ifdef CONFIG_FSL_DDR3
 730         if (unq_mrs_en) {       /* unique mode registers are supported */
 731                 for (i = 1; i < 4; i++) {
 732                         if (popts->rtt_override)
 733                                 rtt_wr = popts->rtt_wr_override_value;
 734                         else
 735                                 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
 736
 737                         esdmode2 &= 0xF9FF;     /* clear bit 10, 9 */
 738                         esdmode2 |= (rtt_wr & 0x3) << 9;
 739                         switch (i) {
 740                         case 1:
 741                                 ddr->ddr_sdram_mode_4 = (0
 742                                         | ((esdmode2 & 0xFFFF) << 16)
 743                                         | ((esdmode3 & 0xFFFF) << 0)
 744                                         );
 745                                 break;
 746                         case 2:
 747                                 ddr->ddr_sdram_mode_6 = (0
 748                                         | ((esdmode2 & 0xFFFF) << 16)
 749                                         | ((esdmode3 & 0xFFFF) << 0)
 750                                         );
 751                                 break;
 752                         case 3:
 753                                 ddr->ddr_sdram_mode_8 = (0
 754                                         | ((esdmode2 & 0xFFFF) << 16)
 755                                         | ((esdmode3 & 0xFFFF) << 0)
 756                                         );
 757                                 break;
 758                         }
 759                 }
 760                 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
 761                         ddr->ddr_sdram_mode_4);
 762                 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
 763                         ddr->ddr_sdram_mode_6);
 764                 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
 765                         ddr->ddr_sdram_mode_8);
 766         }
 767 #endif
 768 }
 769
 770 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
 771 static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
 772                                const memctl_options_t *popts,
 773                                const common_timing_params_t *common_dimm)
 774 {
 775         unsigned int refint;    /* Refresh interval */
 776         unsigned int bstopre;   /* Precharge interval */
 777
 778         refint = picos_to_mclk(common_dimm->refresh_rate_ps);
 779
 780         bstopre = popts->bstopre;
 781
 782         /* refint field used 0x3FFF in earlier controllers */
 783         ddr->ddr_sdram_interval = (0
 784                                    | ((refint & 0xFFFF) << 16)
 785                                    | ((bstopre & 0x3FFF) << 0)
 786                                    );
 787         debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
 788 }
 789
 790 #if defined(CONFIG_FSL_DDR3)
 791 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
 792 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 793                                const memctl_options_t *popts,
 794                                const common_timing_params_t *common_dimm,
 795                                unsigned int cas_latency,
 796                                unsigned int additive_latency,
 797                                const unsigned int unq_mrs_en)
 798 {
 799         unsigned short esdmode;         /* Extended SDRAM mode */
 800         unsigned short sdmode;          /* SDRAM mode */
 801
 802         /* Mode Register - MR1 */
 803         unsigned int qoff = 0;          /* Output buffer enable 0=yes, 1=no */
 804         unsigned int tdqs_en = 0;       /* TDQS Enable: 0=no, 1=yes */
 805         unsigned int rtt;
 806         unsigned int wrlvl_en = 0;      /* Write level enable: 0=no, 1=yes */
 807         unsigned int al = 0;            /* Posted CAS# additive latency (AL) */
 808         unsigned int dic = 0;           /* Output driver impedance, 40ohm */
 809         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
 810                                                        1=Disable (Test/Debug) */
 811
 812         /* Mode Register - MR0 */
 813         unsigned int dll_on;    /* DLL control for precharge PD, 0=off, 1=on */
 814         unsigned int wr;        /* Write Recovery */
 815         unsigned int dll_rst;   /* DLL Reset */
 816         unsigned int mode;      /* Normal=0 or Test=1 */
 817         unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
 818         /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
 819         unsigned int bt;
 820         unsigned int bl;        /* BL: Burst Length */
 821
 822         unsigned int wr_mclk;
 823         /*
 824          * DDR_SDRAM_MODE doesn't support 9,11,13,15
 825          * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
 826          * for this table
 827          */
 828         static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
 829
 830         const unsigned int mclk_ps = get_memory_clk_period_ps();
 831         int i;
 832
 833         if (popts->rtt_override)
 834                 rtt = popts->rtt_override_value;
 835         else
 836                 rtt = popts->cs_local_opts[0].odt_rtt_norm;
 837
 838         if (additive_latency == (cas_latency - 1))
 839                 al = 1;
 840         if (additive_latency == (cas_latency - 2))
 841                 al = 2;
 842
 843         if (popts->quad_rank_present)
 844                 dic = 1;        /* output driver impedance 240/7 ohm */
 845
 846         /*
 847          * The esdmode value will also be used for writing
 848          * MR1 during write leveling for DDR3, although the
 849          * bits specifically related to the write leveling
 850          * scheme will be handled automatically by the DDR
 851          * controller. so we set the wrlvl_en = 0 here.
 852          */
 853         esdmode = (0
 854                 | ((qoff & 0x1) << 12)
 855                 | ((tdqs_en & 0x1) << 11)
 856                 | ((rtt & 0x4) << 7)   /* rtt field is split */
 857                 | ((wrlvl_en & 0x1) << 7)
 858                 | ((rtt & 0x2) << 5)   /* rtt field is split */
 859                 | ((dic & 0x2) << 4)   /* DIC field is split */
 860                 | ((al & 0x3) << 3)
 861                 | ((rtt & 0x1) << 2)  /* rtt field is split */
 862                 | ((dic & 0x1) << 1)   /* DIC field is split */
 863                 | ((dll_en & 0x1) << 0)
 864                 );
 865
 866         /*
 867          * DLL control for precharge PD
 868          * 0=slow exit DLL off (tXPDLL)
 869          * 1=fast exit DLL on (tXP)
 870          */
 871         dll_on = 1;
 872
 873         wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps;
 874         wr = wr_table[wr_mclk - 5];
 875
 876         dll_rst = 0;    /* dll no reset */
 877         mode = 0;       /* normal mode */
 878
 879         /* look up table to get the cas latency bits */
 880         if (cas_latency >= 5 && cas_latency <= 11) {
 881                 unsigned char cas_latency_table[7] = {
 882                         0x2,    /* 5 clocks */
 883                         0x4,    /* 6 clocks */
 884                         0x6,    /* 7 clocks */
 885                         0x8,    /* 8 clocks */
 886                         0xa,    /* 9 clocks */
 887                         0xc,    /* 10 clocks */
 888                         0xe     /* 11 clocks */
 889                 };
 890                 caslat = cas_latency_table[cas_latency - 5];
 891         }
 892         bt = 0; /* Nibble sequential */
 893
 894         switch (popts->burst_length) {
 895         case DDR_BL8:
 896                 bl = 0;
 897                 break;
 898         case DDR_OTF:
 899                 bl = 1;
 900                 break;
 901         case DDR_BC4:
 902                 bl = 2;
 903                 break;
 904         default:
 905                 printf("Error: invalid burst length of %u specified. "
 906                         " Defaulting to on-the-fly BC4 or BL8 beats.\n",
 907                         popts->burst_length);
 908                 bl = 1;
 909                 break;
 910         }
 911
 912         sdmode = (0
 913                   | ((dll_on & 0x1) << 12)
 914                   | ((wr & 0x7) << 9)
 915                   | ((dll_rst & 0x1) << 8)
 916                   | ((mode & 0x1) << 7)
 917                   | (((caslat >> 1) & 0x7) << 4)
 918                   | ((bt & 0x1) << 3)
 919                   | ((bl & 0x3) << 0)
 920                   );
 921
 922         ddr->ddr_sdram_mode = (0
 923                                | ((esdmode & 0xFFFF) << 16)
 924                                | ((sdmode & 0xFFFF) << 0)
 925                                );
 926
 927         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
 928
 929         if (unq_mrs_en) {       /* unique mode registers are supported */
 930                 for (i = 1; i < 4; i++) {
 931                         if (popts->rtt_override)
 932                                 rtt = popts->rtt_override_value;
 933                         else
 934                                 rtt = popts->cs_local_opts[i].odt_rtt_norm;
 935
 936                         esdmode &= 0xFDBB;      /* clear bit 9,6,2 */
 937                         esdmode |= (0
 938                                 | ((rtt & 0x4) << 7)   /* rtt field is split */
 939                                 | ((rtt & 0x2) << 5)   /* rtt field is split */
 940                                 | ((rtt & 0x1) << 2)  /* rtt field is split */
 941                                 );
 942                         switch (i) {
 943                         case 1:
 944                                 ddr->ddr_sdram_mode_3 = (0
 945                                        | ((esdmode & 0xFFFF) << 16)
 946                                        | ((sdmode & 0xFFFF) << 0)
 947                                        );
 948                                 break;
 949                         case 2:
 950                                 ddr->ddr_sdram_mode_5 = (0
 951                                        | ((esdmode & 0xFFFF) << 16)
 952                                        | ((sdmode & 0xFFFF) << 0)
 953                                        );
 954                                 break;
 955                         case 3:
 956                                 ddr->ddr_sdram_mode_7 = (0
 957                                        | ((esdmode & 0xFFFF) << 16)
 958                                        | ((sdmode & 0xFFFF) << 0)
 959                                        );
 960                                 break;
 961                         }
 962                 }
 963                 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
 964                         ddr->ddr_sdram_mode_3);
 965                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
 966                         ddr->ddr_sdram_mode_5);
 967                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
 968                         ddr->ddr_sdram_mode_5);
 969         }
 970 }
 971
 972 #else /* !CONFIG_FSL_DDR3 */
 973
 974 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
 975 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 976                                const memctl_options_t *popts,
 977                                const common_timing_params_t *common_dimm,
 978                                unsigned int cas_latency,
 979                                unsigned int additive_latency,
 980                                const unsigned int unq_mrs_en)
 981 {
 982         unsigned short esdmode;         /* Extended SDRAM mode */
 983         unsigned short sdmode;          /* SDRAM mode */
 984
 985         /*
 986          * FIXME: This ought to be pre-calculated in a
 987          * technology-specific routine,
 988          * e.g. compute_DDR2_mode_register(), and then the
 989          * sdmode and esdmode passed in as part of common_dimm.
 990          */
 991
 992         /* Extended Mode Register */
 993         unsigned int mrs = 0;           /* Mode Register Set */
 994         unsigned int outputs = 0;       /* 0=Enabled, 1=Disabled */
 995         unsigned int rdqs_en = 0;       /* RDQS Enable: 0=no, 1=yes */
 996         unsigned int dqs_en = 0;        /* DQS# Enable: 0=enable, 1=disable */
 997         unsigned int ocd = 0;           /* 0x0=OCD not supported,
 998                                            0x7=OCD default state */
 999         unsigned int rtt;
1000         unsigned int al;                /* Posted CAS# additive latency (AL) */
1001         unsigned int ods = 0;           /* Output Drive Strength:
1002                                                 0 = Full strength (18ohm)
1003                                                 1 = Reduced strength (4ohm) */
1004         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
1005                                                        1=Disable (Test/Debug) */
1006
1007         /* Mode Register (MR) */
1008         unsigned int mr;        /* Mode Register Definition */
1009         unsigned int pd;        /* Power-Down Mode */
1010         unsigned int wr;        /* Write Recovery */
1011         unsigned int dll_res;   /* DLL Reset */
1012         unsigned int mode;      /* Normal=0 or Test=1 */
1013         unsigned int caslat = 0;/* CAS# latency */
1014         /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1015         unsigned int bt;
1016         unsigned int bl;        /* BL: Burst Length */
1017
1018 #if defined(CONFIG_FSL_DDR2)
1019         const unsigned int mclk_ps = get_memory_clk_period_ps();
1020 #endif
1021
1022         rtt = fsl_ddr_get_rtt();
1023
1024         al = additive_latency;
1025
1026         esdmode = (0
1027                 | ((mrs & 0x3) << 14)
1028                 | ((outputs & 0x1) << 12)
1029                 | ((rdqs_en & 0x1) << 11)
1030                 | ((dqs_en & 0x1) << 10)
1031                 | ((ocd & 0x7) << 7)
1032                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1033                 | ((al & 0x7) << 3)
1034                 | ((rtt & 0x1) << 2)   /* rtt field is split */
1035                 | ((ods & 0x1) << 1)
1036                 | ((dll_en & 0x1) << 0)
1037                 );
1038
1039         mr = 0;          /* FIXME: CHECKME */
1040
1041         /*
1042          * 0 = Fast Exit (Normal)
1043          * 1 = Slow Exit (Low Power)
1044          */
1045         pd = 0;
1046
1047 #if defined(CONFIG_FSL_DDR1)
1048         wr = 0;       /* Historical */
1049 #elif defined(CONFIG_FSL_DDR2)
1050         wr = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps - 1;
1051 #endif
1052         dll_res = 0;
1053         mode = 0;
1054
1055 #if defined(CONFIG_FSL_DDR1)
1056         if (1 <= cas_latency && cas_latency <= 4) {
1057                 unsigned char mode_caslat_table[4] = {
1058                         0x5,    /* 1.5 clocks */
1059                         0x2,    /* 2.0 clocks */
1060                         0x6,    /* 2.5 clocks */
1061                         0x3     /* 3.0 clocks */
1062                 };
1063                 caslat = mode_caslat_table[cas_latency - 1];
1064         } else {
1065                 printf("Warning: unknown cas_latency %d\n", cas_latency);
1066         }
1067 #elif defined(CONFIG_FSL_DDR2)
1068         caslat = cas_latency;
1069 #endif
1070         bt = 0;
1071
1072         switch (popts->burst_length) {
1073         case DDR_BL4:
1074                 bl = 2;
1075                 break;
1076         case DDR_BL8:
1077                 bl = 3;
1078                 break;
1079         default:
1080                 printf("Error: invalid burst length of %u specified. "
1081                         " Defaulting to 4 beats.\n",
1082                         popts->burst_length);
1083                 bl = 2;
1084                 break;
1085         }
1086
1087         sdmode = (0
1088                   | ((mr & 0x3) << 14)
1089                   | ((pd & 0x1) << 12)
1090                   | ((wr & 0x7) << 9)
1091                   | ((dll_res & 0x1) << 8)
1092                   | ((mode & 0x1) << 7)
1093                   | ((caslat & 0x7) << 4)
1094                   | ((bt & 0x1) << 3)
1095                   | ((bl & 0x7) << 0)
1096                   );
1097
1098         ddr->ddr_sdram_mode = (0
1099                                | ((esdmode & 0xFFFF) << 16)
1100                                | ((sdmode & 0xFFFF) << 0)
1101                                );
1102         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1103 }
1104 #endif
1105
1106 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1107 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1108 {
1109         unsigned int init_value;        /* Initialization value */
1110
1111         init_value = 0xDEADBEEF;
1112         ddr->ddr_data_init = init_value;
1113 }
1114
1115 /*
1116  * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1117  * The old controller on the 8540/60 doesn't have this register.
1118  * Hope it's OK to set it (to 0) anyway.
1119  */
1120 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1121                                          const memctl_options_t *popts)
1122 {
1123         unsigned int clk_adjust;        /* Clock adjust */
1124
1125         clk_adjust = popts->clk_adjust;
1126         ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
1127         debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1128 }
1129
1130 /* DDR Initialization Address (DDR_INIT_ADDR) */
1131 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1132 {
1133         unsigned int init_addr = 0;     /* Initialization address */
1134
1135         ddr->ddr_init_addr = init_addr;
1136 }
1137
1138 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1139 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1140 {
1141         unsigned int uia = 0;   /* Use initialization address */
1142         unsigned int init_ext_addr = 0; /* Initialization address */
1143
1144         ddr->ddr_init_ext_addr = (0
1145                                   | ((uia & 0x1) << 31)
1146                                   | (init_ext_addr & 0xF)
1147                                   );
1148 }
1149
1150 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
1151 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1152                                 const memctl_options_t *popts)
1153 {
1154         unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1155         unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1156         unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1157         unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1158         unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1159
1160 #if defined(CONFIG_FSL_DDR3)
1161         if (popts->burst_length == DDR_BL8) {
1162                 /* We set BL/2 for fixed BL8 */
1163                 rrt = 0;        /* BL/2 clocks */
1164                 wwt = 0;        /* BL/2 clocks */
1165         } else {
1166                 /* We need to set BL/2 + 2 to BC4 and OTF */
1167                 rrt = 2;        /* BL/2 + 2 clocks */
1168                 wwt = 2;        /* BL/2 + 2 clocks */
1169         }
1170         dll_lock = 1;   /* tDLLK = 512 clocks from spec */
1171 #endif
1172         ddr->timing_cfg_4 = (0
1173                              | ((rwt & 0xf) << 28)
1174                              | ((wrt & 0xf) << 24)
1175                              | ((rrt & 0xf) << 20)
1176                              | ((wwt & 0xf) << 16)
1177                              | (dll_lock & 0x3)
1178                              );
1179         debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1180 }
1181
1182 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1183 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1184 {
1185         unsigned int rodt_on = 0;       /* Read to ODT on */
1186         unsigned int rodt_off = 0;      /* Read to ODT off */
1187         unsigned int wodt_on = 0;       /* Write to ODT on */
1188         unsigned int wodt_off = 0;      /* Write to ODT off */
1189
1190 #if defined(CONFIG_FSL_DDR3)
1191         /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1192         rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1;
1193         rodt_off = 4;   /*  4 clocks */
1194         wodt_on = 1;    /*  1 clocks */
1195         wodt_off = 4;   /*  4 clocks */
1196 #endif
1197
1198         ddr->timing_cfg_5 = (0
1199                              | ((rodt_on & 0x1f) << 24)
1200                              | ((rodt_off & 0x7) << 20)
1201                              | ((wodt_on & 0x1f) << 12)
1202                              | ((wodt_off & 0x7) << 8)
1203                              );
1204         debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1205 }
1206
1207 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
1208 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
1209 {
1210         unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
1211         /* Normal Operation Full Calibration Time (tZQoper) */
1212         unsigned int zqoper = 0;
1213         /* Normal Operation Short Calibration Time (tZQCS) */
1214         unsigned int zqcs = 0;
1215
1216         if (zq_en) {
1217                 zqinit = 9;     /* 512 clocks */
1218                 zqoper = 8;     /* 256 clocks */
1219                 zqcs = 6;       /* 64 clocks */
1220         }
1221
1222         ddr->ddr_zq_cntl = (0
1223                             | ((zq_en & 0x1) << 31)
1224                             | ((zqinit & 0xF) << 24)
1225                             | ((zqoper & 0xF) << 16)
1226                             | ((zqcs & 0xF) << 8)
1227                             );
1228         debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
1229 }
1230
1231 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
1232 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
1233                                 const memctl_options_t *popts)
1234 {
1235         /*
1236          * First DQS pulse rising edge after margining mode
1237          * is programmed (tWL_MRD)
1238          */
1239         unsigned int wrlvl_mrd = 0;
1240         /* ODT delay after margining mode is programmed (tWL_ODTEN) */
1241         unsigned int wrlvl_odten = 0;
1242         /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
1243         unsigned int wrlvl_dqsen = 0;
1244         /* WRLVL_SMPL: Write leveling sample time */
1245         unsigned int wrlvl_smpl = 0;
1246         /* WRLVL_WLR: Write leveling repeition time */
1247         unsigned int wrlvl_wlr = 0;
1248         /* WRLVL_START: Write leveling start time */
1249         unsigned int wrlvl_start = 0;
1250
1251         /* suggest enable write leveling for DDR3 due to fly-by topology */
1252         if (wrlvl_en) {
1253                 /* tWL_MRD min = 40 nCK, we set it 64 */
1254                 wrlvl_mrd = 0x6;
1255                 /* tWL_ODTEN 128 */
1256                 wrlvl_odten = 0x7;
1257                 /* tWL_DQSEN min = 25 nCK, we set it 32 */
1258                 wrlvl_dqsen = 0x5;
1259                 /*
1260                  * Write leveling sample time at least need 6 clocks
1261                  * higher than tWLO to allow enough time for progagation
1262                  * delay and sampling the prime data bits.
1263                  */
1264                 wrlvl_smpl = 0xf;
1265                 /*
1266                  * Write leveling repetition time
1267                  * at least tWLO + 6 clocks clocks
1268                  * we set it 64
1269                  */
1270                 wrlvl_wlr = 0x6;
1271                 /*
1272                  * Write leveling start time
1273                  * The value use for the DQS_ADJUST for the first sample
1274                  * when write leveling is enabled. It probably needs to be
1275                  * overriden per platform.
1276                  */
1277                 wrlvl_start = 0x8;
1278                 /*
1279                  * Override the write leveling sample and start time
1280                  * according to specific board
1281                  */
1282                 if (popts->wrlvl_override) {
1283                         wrlvl_smpl = popts->wrlvl_sample;
1284                         wrlvl_start = popts->wrlvl_start;
1285                 }
1286         }
1287
1288         ddr->ddr_wrlvl_cntl = (0
1289                                | ((wrlvl_en & 0x1) << 31)
1290                                | ((wrlvl_mrd & 0x7) << 24)
1291                                | ((wrlvl_odten & 0x7) << 20)
1292                                | ((wrlvl_dqsen & 0x7) << 16)
1293                                | ((wrlvl_smpl & 0xf) << 12)
1294                                | ((wrlvl_wlr & 0x7) << 8)
1295                                | ((wrlvl_start & 0x1F) << 0)
1296                                );
1297         debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
1298 }
1299
1300 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
1301 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
1302 {
1303         /* Self Refresh Idle Threshold */
1304         ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
1305 }
1306
1307 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1308 {
1309         if (popts->addr_hash) {
1310                 ddr->ddr_eor = 0x40000000;      /* address hash enable */
1311                 puts("Address hashing enabled.\n");
1312         }
1313 }
1314
1315 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1316 {
1317         ddr->ddr_cdr1 = popts->ddr_cdr1;
1318         debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
1319 }
1320
1321 unsigned int
1322 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
1323 {
1324         unsigned int res = 0;
1325
1326         /*
1327          * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
1328          * not set at the same time.
1329          */
1330         if (ddr->ddr_sdram_cfg & 0x10000000
1331             && ddr->ddr_sdram_cfg & 0x00008000) {
1332                 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
1333                                 " should not be set at the same time.\n");
1334                 res++;
1335         }
1336
1337         return res;
1338 }
1339
1340 unsigned int
1341 compute_fsl_memctl_config_regs(const memctl_options_t *popts,
1342                                fsl_ddr_cfg_regs_t *ddr,
1343                                const common_timing_params_t *common_dimm,
1344                                const dimm_params_t *dimm_params,
1345                                unsigned int dbw_cap_adj,
1346                                unsigned int size_only)
1347 {
1348         unsigned int i;
1349         unsigned int cas_latency;
1350         unsigned int additive_latency;
1351         unsigned int sr_it;
1352         unsigned int zq_en;
1353         unsigned int wrlvl_en;
1354         unsigned int ip_rev = 0;
1355         unsigned int unq_mrs_en = 0;
1356         int cs_en = 1;
1357
1358         memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
1359
1360         if (common_dimm == NULL) {
1361                 printf("Error: subset DIMM params struct null pointer\n");
1362                 return 1;
1363         }
1364
1365         /*
1366          * Process overrides first.
1367          *
1368          * FIXME: somehow add dereated caslat to this
1369          */
1370         cas_latency = (popts->cas_latency_override)
1371                 ? popts->cas_latency_override_value
1372                 : common_dimm->lowest_common_SPD_caslat;
1373
1374         additive_latency = (popts->additive_latency_override)
1375                 ? popts->additive_latency_override_value
1376                 : common_dimm->additive_latency;
1377
1378         sr_it = (popts->auto_self_refresh_en)
1379                 ? popts->sr_it
1380                 : 0;
1381         /* ZQ calibration */
1382         zq_en = (popts->zq_en) ? 1 : 0;
1383         /* write leveling */
1384         wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
1385
1386         /* Chip Select Memory Bounds (CSn_BNDS) */
1387         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1388                 unsigned long long ea = 0, sa = 0;
1389                 unsigned int cs_per_dimm
1390                         = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
1391                 unsigned int dimm_number
1392                         = i / cs_per_dimm;
1393                 unsigned long long rank_density
1394                         = dimm_params[dimm_number].rank_density;
1395
1396                 if (((i == 1) && (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1)) ||
1397                         ((i == 2) && (popts->ba_intlv_ctl & 0x04)) ||
1398                         ((i == 3) && (popts->ba_intlv_ctl & FSL_DDR_CS2_CS3))) {
1399                         /*
1400                          * Don't set up boundaries for unused CS
1401                          * cs1 for cs0_cs1, cs0_cs1_and_cs2_cs3, cs0_cs1_cs2_cs3
1402                          * cs2 for cs0_cs1_cs2_cs3
1403                          * cs3 for cs2_cs3, cs0_cs1_and_cs2_cs3, cs0_cs1_cs2_cs3
1404                          * But we need to set the ODT_RD_CFG and
1405                          * ODT_WR_CFG for CS1_CONFIG here.
1406                          */
1407                         set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1408                         continue;
1409                 }
1410                 if (dimm_params[dimm_number].n_ranks == 0) {
1411                         debug("Skipping setup of CS%u "
1412                                 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
1413                         continue;
1414                 }
1415                 if (popts->memctl_interleaving && popts->ba_intlv_ctl) {
1416                         /*
1417                          * This works superbank 2CS
1418                          * There are 2 or more memory controllers configured
1419                          * identically, memory is interleaved between them,
1420                          * and each controller uses rank interleaving within
1421                          * itself. Therefore the starting and ending address
1422                          * on each controller is twice the amount present on
1423                          * each controller. If any CS is not included in the
1424                          * interleaving, the memory on that CS is not accssible
1425                          * and the total memory size is reduced. The CS is also
1426                          * disabled.
1427                          */
1428                         unsigned long long ctlr_density = 0;
1429                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1430                         case FSL_DDR_CS0_CS1:
1431                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1432                                 ctlr_density = dimm_params[0].rank_density * 2;
1433                                 if (i > 1)
1434                                         cs_en = 0;
1435                                 break;
1436                         case FSL_DDR_CS2_CS3:
1437                                 ctlr_density = dimm_params[0].rank_density;
1438                                 if (i > 0)
1439                                         cs_en = 0;
1440                                 break;
1441                         case FSL_DDR_CS0_CS1_CS2_CS3:
1442                                 /*
1443                                  * The four CS interleaving should have been verified by
1444                                  * populate_memctl_options()
1445                                  */
1446                                 ctlr_density = dimm_params[0].rank_density * 4;
1447                                 break;
1448                         default:
1449                                 break;
1450                         }
1451                         ea = (CONFIG_NUM_DDR_CONTROLLERS *
1452                                 (ctlr_density >> dbw_cap_adj)) - 1;
1453                 }
1454                 else if (!popts->memctl_interleaving && popts->ba_intlv_ctl) {
1455                         /*
1456                          * If memory interleaving between controllers is NOT
1457                          * enabled, the starting address for each memory
1458                          * controller is distinct.  However, because rank
1459                          * interleaving is enabled, the starting and ending
1460                          * addresses of the total memory on that memory
1461                          * controller needs to be programmed into its
1462                          * respective CS0_BNDS.
1463                          */
1464                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1465                         case FSL_DDR_CS0_CS1_CS2_CS3:
1466                                 /* CS0+CS1+CS2+CS3 interleaving, only CS0_CNDS
1467                                  * needs to be set.
1468                                  */
1469                                 sa = common_dimm->base_address;
1470                                 ea = sa + (4 * (rank_density >> dbw_cap_adj))-1;
1471                                 break;
1472                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1473                                 /* CS0+CS1 and CS2+CS3 interleaving, CS0_CNDS
1474                                  * and CS2_CNDS need to be set.
1475                                  */
1476                                 if ((i == 2) && (dimm_number == 0)) {
1477                                         sa = dimm_params[dimm_number].base_address +
1478                                               2 * (rank_density >> dbw_cap_adj);
1479                                         ea = sa + 2 * (rank_density >> dbw_cap_adj) - 1;
1480                                 } else {
1481                                         sa = dimm_params[dimm_number].base_address;
1482                                         ea = sa + (2 * (rank_density >>
1483                                                 dbw_cap_adj)) - 1;
1484                                 }
1485                                 break;
1486                         case FSL_DDR_CS0_CS1:
1487                                 /* CS0+CS1 interleaving, CS0_CNDS needs
1488                                  * to be set
1489                                  */
1490                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1491                                         sa = dimm_params[dimm_number].base_address;
1492                                         ea = sa + (rank_density >> dbw_cap_adj) - 1;
1493                                         sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1494                                         ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1495                                 } else {
1496                                         sa = 0;
1497                                         ea = 0;
1498                                 }
1499                                 if (i == 0)
1500                                         ea += (rank_density >> dbw_cap_adj);
1501                                 break;
1502                         case FSL_DDR_CS2_CS3:
1503                                 /* CS2+CS3 interleaving*/
1504                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1505                                         sa = dimm_params[dimm_number].base_address;
1506                                         ea = sa + (rank_density >> dbw_cap_adj) - 1;
1507                                         sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1508                                         ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1509                                 } else {
1510                                         sa = 0;
1511                                         ea = 0;
1512                                 }
1513                                 if (i == 2)
1514                                         ea += (rank_density >> dbw_cap_adj);
1515                                 break;
1516                         default:  /* No bank(chip-select) interleaving */
1517                                 break;
1518                         }
1519                 }
1520                 else if (popts->memctl_interleaving && !popts->ba_intlv_ctl) {
1521                         /*
1522                          * Only the rank on CS0 of each memory controller may
1523                          * be used if memory controller interleaving is used
1524                          * without rank interleaving within each memory
1525                          * controller.  However, the ending address programmed
1526                          * into each CS0 must be the sum of the amount of
1527                          * memory in the two CS0 ranks.
1528                          */
1529                         if (i == 0) {
1530                                 ea = (2 * (rank_density >> dbw_cap_adj)) - 1;
1531                         }
1532
1533                 }
1534                 else if (!popts->memctl_interleaving && !popts->ba_intlv_ctl) {
1535                         /*
1536                          * No rank interleaving and no memory controller
1537                          * interleaving.
1538                          */
1539                         sa = dimm_params[dimm_number].base_address;
1540                         ea = sa + (rank_density >> dbw_cap_adj) - 1;
1541                         if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1542                                 sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1543                                 ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1544                         } else {
1545                                 sa = 0;
1546                                 ea = 0;
1547                         }
1548                 }
1549
1550                 sa >>= 24;
1551                 ea >>= 24;
1552
1553                 ddr->cs[i].bnds = (0
1554                         | ((sa & 0xFFF) << 16)  /* starting address MSB */
1555                         | ((ea & 0xFFF) << 0)   /* ending address MSB */
1556                         );
1557
1558                 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
1559                 if (cs_en) {
1560                         set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1561                         set_csn_config_2(i, ddr);
1562                 } else
1563                         printf("CS%d is disabled.\n", i);
1564         }
1565
1566         /*
1567          * In the case we only need to compute the ddr sdram size, we only need
1568          * to set csn registers, so return from here.
1569          */
1570         if (size_only)
1571                 return 0;
1572
1573         set_ddr_eor(ddr, popts);
1574
1575 #if !defined(CONFIG_FSL_DDR1)
1576         set_timing_cfg_0(ddr, popts);
1577 #endif
1578
1579         set_timing_cfg_3(ddr, common_dimm, cas_latency);
1580         set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
1581         set_timing_cfg_2(ddr, popts, common_dimm,
1582                                 cas_latency, additive_latency);
1583
1584         set_ddr_cdr1(ddr, popts);
1585         set_ddr_sdram_cfg(ddr, popts, common_dimm);
1586         ip_rev = fsl_ddr_get_version();
1587         if (ip_rev > 0x40400)
1588                 unq_mrs_en = 1;
1589
1590         set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
1591         set_ddr_sdram_mode(ddr, popts, common_dimm,
1592                                 cas_latency, additive_latency, unq_mrs_en);
1593         set_ddr_sdram_mode_2(ddr, popts, unq_mrs_en);
1594         set_ddr_sdram_interval(ddr, popts, common_dimm);
1595         set_ddr_data_init(ddr);
1596         set_ddr_sdram_clk_cntl(ddr, popts);
1597         set_ddr_init_addr(ddr);
1598         set_ddr_init_ext_addr(ddr);
1599         set_timing_cfg_4(ddr, popts);
1600         set_timing_cfg_5(ddr, cas_latency);
1601
1602         set_ddr_zq_cntl(ddr, zq_en);
1603         set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
1604
1605         set_ddr_sr_cntr(ddr, sr_it);
1606
1607         set_ddr_sdram_rcw(ddr, popts, common_dimm);
1608
1609         return check_fsl_memctl_config_regs(ddr);
1610 }