arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c

   1 /*
   2  * Copyright 2008-2012 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the Free
   6  * Software Foundation; either version 2 of the License, or (at your option)
   7  * any later version.
   8  */
   9
  10 /*
  11  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
  12  * Based on code from spd_sdram.c
  13  * Author: James Yang [at freescale.com]
  14  */
  15
  16 #include <common.h>
  17 #include <asm/fsl_ddr_sdram.h>
  18
  19 #include "ddr.h"
  20
  21 #ifdef CONFIG_MPC83xx
  22         #define _DDR_ADDR CONFIG_SYS_MPC83xx_DDR_ADDR
  23 #elif defined(CONFIG_MPC85xx)
  24         #define _DDR_ADDR CONFIG_SYS_MPC85xx_DDR_ADDR
  25 #elif defined(CONFIG_MPC86xx)
  26         #define _DDR_ADDR CONFIG_SYS_MPC86xx_DDR_ADDR
  27 #else
  28         #error "Undefined _DDR_ADDR"
  29 #endif
  30
  31 static u32 fsl_ddr_get_version(void)
  32 {
  33         ccsr_ddr_t *ddr;
  34         u32 ver_major_minor_errata;
  35
  36         ddr = (void *)_DDR_ADDR;
  37         ver_major_minor_errata = (in_be32(&ddr->ip_rev1) & 0xFFFF) << 8;
  38         ver_major_minor_errata |= (in_be32(&ddr->ip_rev2) & 0xFF00) >> 8;
  39
  40         return ver_major_minor_errata;
  41 }
  42
  43 unsigned int picos_to_mclk(unsigned int picos);
  44
  45 /*
  46  * Determine Rtt value.
  47  *
  48  * This should likely be either board or controller specific.
  49  *
  50  * Rtt(nominal) - DDR2:
  51  *      0 = Rtt disabled
  52  *      1 = 75 ohm
  53  *      2 = 150 ohm
  54  *      3 = 50 ohm
  55  * Rtt(nominal) - DDR3:
  56  *      0 = Rtt disabled
  57  *      1 = 60 ohm
  58  *      2 = 120 ohm
  59  *      3 = 40 ohm
  60  *      4 = 20 ohm
  61  *      5 = 30 ohm
  62  *
  63  * FIXME: Apparently 8641 needs a value of 2
  64  * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
  65  *
  66  * FIXME: There was some effort down this line earlier:
  67  *
  68  *      unsigned int i;
  69  *      for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
  70  *              if (popts->dimmslot[i].num_valid_cs
  71  *                  && (popts->cs_local_opts[2*i].odt_rd_cfg
  72  *                      || popts->cs_local_opts[2*i].odt_wr_cfg)) {
  73  *                      rtt = 2;
  74  *                      break;
  75  *              }
  76  *      }
  77  */
  78 static inline int fsl_ddr_get_rtt(void)
  79 {
  80         int rtt;
  81
  82 #if defined(CONFIG_FSL_DDR1)
  83         rtt = 0;
  84 #elif defined(CONFIG_FSL_DDR2)
  85         rtt = 3;
  86 #else
  87         rtt = 0;
  88 #endif
  89
  90         return rtt;
  91 }
  92
  93 /*
  94  * compute the CAS write latency according to DDR3 spec
  95  * CWL = 5 if tCK >= 2.5ns
  96  *       6 if 2.5ns > tCK >= 1.875ns
  97  *       7 if 1.875ns > tCK >= 1.5ns
  98  *       8 if 1.5ns > tCK >= 1.25ns
  99  *       9 if 1.25ns > tCK >= 1.07ns
 100  *       10 if 1.07ns > tCK >= 0.935ns
 101  *       11 if 0.935ns > tCK >= 0.833ns
 102  *       12 if 0.833ns > tCK >= 0.75ns
 103  */
 104 static inline unsigned int compute_cas_write_latency(void)
 105 {
 106         unsigned int cwl;
 107         const unsigned int mclk_ps = get_memory_clk_period_ps();
 108
 109         if (mclk_ps >= 2500)
 110                 cwl = 5;
 111         else if (mclk_ps >= 1875)
 112                 cwl = 6;
 113         else if (mclk_ps >= 1500)
 114                 cwl = 7;
 115         else if (mclk_ps >= 1250)
 116                 cwl = 8;
 117         else if (mclk_ps >= 1070)
 118                 cwl = 9;
 119         else if (mclk_ps >= 935)
 120                 cwl = 10;
 121         else if (mclk_ps >= 833)
 122                 cwl = 11;
 123         else if (mclk_ps >= 750)
 124                 cwl = 12;
 125         else {
 126                 cwl = 12;
 127                 printf("Warning: CWL is out of range\n");
 128         }
 129         return cwl;
 130 }
 131
 132 /* Chip Select Configuration (CSn_CONFIG) */
 133 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
 134                                const memctl_options_t *popts,
 135                                const dimm_params_t *dimm_params)
 136 {
 137         unsigned int cs_n_en = 0; /* Chip Select enable */
 138         unsigned int intlv_en = 0; /* Memory controller interleave enable */
 139         unsigned int intlv_ctl = 0; /* Interleaving control */
 140         unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
 141         unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
 142         unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
 143         unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
 144         unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
 145         unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
 146         int go_config = 0;
 147
 148         /* Compute CS_CONFIG only for existing ranks of each DIMM.  */
 149         switch (i) {
 150         case 0:
 151                 if (dimm_params[dimm_number].n_ranks > 0) {
 152                         go_config = 1;
 153                         /* These fields only available in CS0_CONFIG */
 154                         if (!popts->memctl_interleaving)
 155                                 break;
 156                         switch (popts->memctl_interleaving_mode) {
 157                         case FSL_DDR_CACHE_LINE_INTERLEAVING:
 158                         case FSL_DDR_PAGE_INTERLEAVING:
 159                         case FSL_DDR_BANK_INTERLEAVING:
 160                         case FSL_DDR_SUPERBANK_INTERLEAVING:
 161                                 intlv_en = popts->memctl_interleaving;
 162                                 intlv_ctl = popts->memctl_interleaving_mode;
 163                                 break;
 164                         default:
 165                                 break;
 166                         }
 167                 }
 168                 break;
 169         case 1:
 170                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
 171                     (dimm_number == 1 && dimm_params[1].n_ranks > 0))
 172                         go_config = 1;
 173                 break;
 174         case 2:
 175                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
 176                    (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
 177                         go_config = 1;
 178                 break;
 179         case 3:
 180                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
 181                     (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
 182                     (dimm_number == 3 && dimm_params[3].n_ranks > 0))
 183                         go_config = 1;
 184                 break;
 185         default:
 186                 break;
 187         }
 188         if (go_config) {
 189                 unsigned int n_banks_per_sdram_device;
 190                 cs_n_en = 1;
 191                 ap_n_en = popts->cs_local_opts[i].auto_precharge;
 192                 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
 193                 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
 194                 n_banks_per_sdram_device
 195                         = dimm_params[dimm_number].n_banks_per_sdram_device;
 196                 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
 197                 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
 198                 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
 199         }
 200         ddr->cs[i].config = (0
 201                 | ((cs_n_en & 0x1) << 31)
 202                 | ((intlv_en & 0x3) << 29)
 203                 | ((intlv_ctl & 0xf) << 24)
 204                 | ((ap_n_en & 0x1) << 23)
 205
 206                 /* XXX: some implementation only have 1 bit starting at left */
 207                 | ((odt_rd_cfg & 0x7) << 20)
 208
 209                 /* XXX: Some implementation only have 1 bit starting at left */
 210                 | ((odt_wr_cfg & 0x7) << 16)
 211
 212                 | ((ba_bits_cs_n & 0x3) << 14)
 213                 | ((row_bits_cs_n & 0x7) << 8)
 214                 | ((col_bits_cs_n & 0x7) << 0)
 215                 );
 216         debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
 217 }
 218
 219 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
 220 /* FIXME: 8572 */
 221 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
 222 {
 223         unsigned int pasr_cfg = 0;      /* Partial array self refresh config */
 224
 225         ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
 226         debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
 227 }
 228
 229 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
 230
 231 #if !defined(CONFIG_FSL_DDR1)
 232 static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
 233 {
 234 #if CONFIG_DIMM_SLOTS_PER_CTLR == 1
 235         if (dimm_params[0].n_ranks == 4)
 236                 return 1;
 237 #endif
 238
 239 #if CONFIG_DIMM_SLOTS_PER_CTLR == 2
 240         if ((dimm_params[0].n_ranks == 2) &&
 241                 (dimm_params[1].n_ranks == 2))
 242                 return 1;
 243
 244 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 245         if (dimm_params[0].n_ranks == 4)
 246                 return 1;
 247 #endif
 248 #endif
 249         return 0;
 250 }
 251
 252 /*
 253  * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
 254  *
 255  * Avoid writing for DDR I.  The new PQ38 DDR controller
 256  * dreams up non-zero default values to be backwards compatible.
 257  */
 258 static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
 259                                 const memctl_options_t *popts,
 260                                 const dimm_params_t *dimm_params)
 261 {
 262         unsigned char trwt_mclk = 0;   /* Read-to-write turnaround */
 263         unsigned char twrt_mclk = 0;   /* Write-to-read turnaround */
 264         /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
 265         unsigned char trrt_mclk = 0;   /* Read-to-read turnaround */
 266         unsigned char twwt_mclk = 0;   /* Write-to-write turnaround */
 267
 268         /* Active powerdown exit timing (tXARD and tXARDS). */
 269         unsigned char act_pd_exit_mclk;
 270         /* Precharge powerdown exit timing (tXP). */
 271         unsigned char pre_pd_exit_mclk;
 272         /* ODT powerdown exit timing (tAXPD). */
 273         unsigned char taxpd_mclk;
 274         /* Mode register set cycle time (tMRD). */
 275         unsigned char tmrd_mclk;
 276
 277 #ifdef CONFIG_FSL_DDR3
 278         /*
 279          * (tXARD and tXARDS). Empirical?
 280          * The DDR3 spec has not tXARD,
 281          * we use the tXP instead of it.
 282          * tXP=max(3nCK, 7.5ns) for DDR3.
 283          * spec has not the tAXPD, we use
 284          * tAXPD=1, need design to confirm.
 285          */
 286         int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
 287         unsigned int data_rate = get_ddr_freq(0);
 288         tmrd_mclk = 4;
 289         /* set the turnaround time */
 290
 291         /*
 292          * for single quad-rank DIMM and two dual-rank DIMMs
 293          * to avoid ODT overlap
 294          */
 295         if (avoid_odt_overlap(dimm_params)) {
 296                 twwt_mclk = 2;
 297                 trrt_mclk = 1;
 298         }
 299         /* for faster clock, need more time for data setup */
 300         trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
 301
 302         if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
 303                 twrt_mclk = 1;
 304
 305         if (popts->dynamic_power == 0) {        /* powerdown is not used */
 306                 act_pd_exit_mclk = 1;
 307                 pre_pd_exit_mclk = 1;
 308                 taxpd_mclk = 1;
 309         } else {
 310                 /* act_pd_exit_mclk = tXARD, see above */
 311                 act_pd_exit_mclk = picos_to_mclk(tXP);
 312                 /* Mode register MR0[A12] is '1' - fast exit */
 313                 pre_pd_exit_mclk = act_pd_exit_mclk;
 314                 taxpd_mclk = 1;
 315         }
 316 #else /* CONFIG_FSL_DDR2 */
 317         /*
 318          * (tXARD and tXARDS). Empirical?
 319          * tXARD = 2 for DDR2
 320          * tXP=2
 321          * tAXPD=8
 322          */
 323         act_pd_exit_mclk = 2;
 324         pre_pd_exit_mclk = 2;
 325         taxpd_mclk = 8;
 326         tmrd_mclk = 2;
 327 #endif
 328
 329         if (popts->trwt_override)
 330                 trwt_mclk = popts->trwt;
 331
 332         ddr->timing_cfg_0 = (0
 333                 | ((trwt_mclk & 0x3) << 30)     /* RWT */
 334                 | ((twrt_mclk & 0x3) << 28)     /* WRT */
 335                 | ((trrt_mclk & 0x3) << 26)     /* RRT */
 336                 | ((twwt_mclk & 0x3) << 24)     /* WWT */
 337                 | ((act_pd_exit_mclk & 0x7) << 20)  /* ACT_PD_EXIT */
 338                 | ((pre_pd_exit_mclk & 0xF) << 16)  /* PRE_PD_EXIT */
 339                 | ((taxpd_mclk & 0xf) << 8)     /* ODT_PD_EXIT */
 340                 | ((tmrd_mclk & 0xf) << 0)      /* MRS_CYC */
 341                 );
 342         debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
 343 }
 344 #endif  /* defined(CONFIG_FSL_DDR2) */
 345
 346 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
 347 static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
 348                                const memctl_options_t *popts,
 349                                const common_timing_params_t *common_dimm,
 350                                unsigned int cas_latency)
 351 {
 352         /* Extended precharge to activate interval (tRP) */
 353         unsigned int ext_pretoact = 0;
 354         /* Extended Activate to precharge interval (tRAS) */
 355         unsigned int ext_acttopre = 0;
 356         /* Extended activate to read/write interval (tRCD) */
 357         unsigned int ext_acttorw = 0;
 358         /* Extended refresh recovery time (tRFC) */
 359         unsigned int ext_refrec;
 360         /* Extended MCAS latency from READ cmd */
 361         unsigned int ext_caslat = 0;
 362         /* Extended last data to precharge interval (tWR) */
 363         unsigned int ext_wrrec = 0;
 364         /* Control Adjust */
 365         unsigned int cntl_adj = 0;
 366
 367         ext_pretoact = picos_to_mclk(common_dimm->tRP_ps) >> 4;
 368         ext_acttopre = picos_to_mclk(common_dimm->tRAS_ps) >> 4;
 369         ext_acttorw = picos_to_mclk(common_dimm->tRCD_ps) >> 4;
 370         ext_caslat = (2 * cas_latency - 1) >> 4;
 371         ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4;
 372         /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
 373         ext_wrrec = (picos_to_mclk(common_dimm->tWR_ps) +
 374                 (popts->OTF_burst_chop_en ? 2 : 0)) >> 4;
 375
 376         ddr->timing_cfg_3 = (0
 377                 | ((ext_pretoact & 0x1) << 28)
 378                 | ((ext_acttopre & 0x2) << 24)
 379                 | ((ext_acttorw & 0x1) << 22)
 380                 | ((ext_refrec & 0x1F) << 16)
 381                 | ((ext_caslat & 0x3) << 12)
 382                 | ((ext_wrrec & 0x1) << 8)
 383                 | ((cntl_adj & 0x7) << 0)
 384                 );
 385         debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
 386 }
 387
 388 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
 389 static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
 390                                const memctl_options_t *popts,
 391                                const common_timing_params_t *common_dimm,
 392                                unsigned int cas_latency)
 393 {
 394         /* Precharge-to-activate interval (tRP) */
 395         unsigned char pretoact_mclk;
 396         /* Activate to precharge interval (tRAS) */
 397         unsigned char acttopre_mclk;
 398         /*  Activate to read/write interval (tRCD) */
 399         unsigned char acttorw_mclk;
 400         /* CASLAT */
 401         unsigned char caslat_ctrl;
 402         /*  Refresh recovery time (tRFC) ; trfc_low */
 403         unsigned char refrec_ctrl;
 404         /* Last data to precharge minimum interval (tWR) */
 405         unsigned char wrrec_mclk;
 406         /* Activate-to-activate interval (tRRD) */
 407         unsigned char acttoact_mclk;
 408         /* Last write data pair to read command issue interval (tWTR) */
 409         unsigned char wrtord_mclk;
 410         /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
 411         static const u8 wrrec_table[] = {
 412                 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
 413
 414         pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps);
 415         acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps);
 416         acttorw_mclk = picos_to_mclk(common_dimm->tRCD_ps);
 417
 418         /*
 419          * Translate CAS Latency to a DDR controller field value:
 420          *
 421          *      CAS Lat DDR I   DDR II  Ctrl
 422          *      Clocks  SPD Bit SPD Bit Value
 423          *      ------- ------- ------- -----
 424          *      1.0     0               0001
 425          *      1.5     1               0010
 426          *      2.0     2       2       0011
 427          *      2.5     3               0100
 428          *      3.0     4       3       0101
 429          *      3.5     5               0110
 430          *      4.0             4       0111
 431          *      4.5                     1000
 432          *      5.0             5       1001
 433          */
 434 #if defined(CONFIG_FSL_DDR1)
 435         caslat_ctrl = (cas_latency + 1) & 0x07;
 436 #elif defined(CONFIG_FSL_DDR2)
 437         caslat_ctrl = 2 * cas_latency - 1;
 438 #else
 439         /*
 440          * if the CAS latency more than 8 cycle,
 441          * we need set extend bit for it at
 442          * TIMING_CFG_3[EXT_CASLAT]
 443          */
 444         caslat_ctrl = 2 * cas_latency - 1;
 445 #endif
 446
 447         refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8;
 448         wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps);
 449
 450         if (wrrec_mclk > 16)
 451                 printf("Error: WRREC doesn't support more than 16 clocks\n");
 452         else
 453                 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
 454         if (popts->OTF_burst_chop_en)
 455                 wrrec_mclk += 2;
 456
 457         acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps);
 458         /*
 459          * JEDEC has min requirement for tRRD
 460          */
 461 #if defined(CONFIG_FSL_DDR3)
 462         if (acttoact_mclk < 4)
 463                 acttoact_mclk = 4;
 464 #endif
 465         wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps);
 466         /*
 467          * JEDEC has some min requirements for tWTR
 468          */
 469 #if defined(CONFIG_FSL_DDR2)
 470         if (wrtord_mclk < 2)
 471                 wrtord_mclk = 2;
 472 #elif defined(CONFIG_FSL_DDR3)
 473         if (wrtord_mclk < 4)
 474                 wrtord_mclk = 4;
 475 #endif
 476         if (popts->OTF_burst_chop_en)
 477                 wrtord_mclk += 2;
 478
 479         ddr->timing_cfg_1 = (0
 480                 | ((pretoact_mclk & 0x0F) << 28)
 481                 | ((acttopre_mclk & 0x0F) << 24)
 482                 | ((acttorw_mclk & 0xF) << 20)
 483                 | ((caslat_ctrl & 0xF) << 16)
 484                 | ((refrec_ctrl & 0xF) << 12)
 485                 | ((wrrec_mclk & 0x0F) << 8)
 486                 | ((acttoact_mclk & 0x0F) << 4)
 487                 | ((wrtord_mclk & 0x0F) << 0)
 488                 );
 489         debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
 490 }
 491
 492 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
 493 static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 494                                const memctl_options_t *popts,
 495                                const common_timing_params_t *common_dimm,
 496                                unsigned int cas_latency,
 497                                unsigned int additive_latency)
 498 {
 499         /* Additive latency */
 500         unsigned char add_lat_mclk;
 501         /* CAS-to-preamble override */
 502         unsigned short cpo;
 503         /* Write latency */
 504         unsigned char wr_lat;
 505         /*  Read to precharge (tRTP) */
 506         unsigned char rd_to_pre;
 507         /* Write command to write data strobe timing adjustment */
 508         unsigned char wr_data_delay;
 509         /* Minimum CKE pulse width (tCKE) */
 510         unsigned char cke_pls;
 511         /* Window for four activates (tFAW) */
 512         unsigned short four_act;
 513
 514         /* FIXME add check that this must be less than acttorw_mclk */
 515         add_lat_mclk = additive_latency;
 516         cpo = popts->cpo_override;
 517
 518 #if defined(CONFIG_FSL_DDR1)
 519         /*
 520          * This is a lie.  It should really be 1, but if it is
 521          * set to 1, bits overlap into the old controller's
 522          * otherwise unused ACSM field.  If we leave it 0, then
 523          * the HW will magically treat it as 1 for DDR 1.  Oh Yea.
 524          */
 525         wr_lat = 0;
 526 #elif defined(CONFIG_FSL_DDR2)
 527         wr_lat = cas_latency - 1;
 528 #else
 529         wr_lat = compute_cas_write_latency();
 530 #endif
 531
 532         rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps);
 533         /*
 534          * JEDEC has some min requirements for tRTP
 535          */
 536 #if defined(CONFIG_FSL_DDR2)
 537         if (rd_to_pre  < 2)
 538                 rd_to_pre  = 2;
 539 #elif defined(CONFIG_FSL_DDR3)
 540         if (rd_to_pre < 4)
 541                 rd_to_pre = 4;
 542 #endif
 543         if (additive_latency)
 544                 rd_to_pre += additive_latency;
 545         if (popts->OTF_burst_chop_en)
 546                 rd_to_pre += 2; /* according to UM */
 547
 548         wr_data_delay = popts->write_data_delay;
 549         cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps);
 550         four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
 551
 552         ddr->timing_cfg_2 = (0
 553                 | ((add_lat_mclk & 0xf) << 28)
 554                 | ((cpo & 0x1f) << 23)
 555                 | ((wr_lat & 0xf) << 19)
 556                 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
 557                 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
 558                 | ((cke_pls & 0x7) << 6)
 559                 | ((four_act & 0x3f) << 0)
 560                 );
 561         debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
 562 }
 563
 564 /* DDR SDRAM Register Control Word */
 565 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
 566                                const memctl_options_t *popts,
 567                                const common_timing_params_t *common_dimm)
 568 {
 569         if (common_dimm->all_DIMMs_registered
 570                 && !common_dimm->all_DIMMs_unbuffered) {
 571                 if (popts->rcw_override) {
 572                         ddr->ddr_sdram_rcw_1 = popts->rcw_1;
 573                         ddr->ddr_sdram_rcw_2 = popts->rcw_2;
 574                 } else {
 575                         ddr->ddr_sdram_rcw_1 =
 576                                 common_dimm->rcw[0] << 28 | \
 577                                 common_dimm->rcw[1] << 24 | \
 578                                 common_dimm->rcw[2] << 20 | \
 579                                 common_dimm->rcw[3] << 16 | \
 580                                 common_dimm->rcw[4] << 12 | \
 581                                 common_dimm->rcw[5] << 8 | \
 582                                 common_dimm->rcw[6] << 4 | \
 583                                 common_dimm->rcw[7];
 584                         ddr->ddr_sdram_rcw_2 =
 585                                 common_dimm->rcw[8] << 28 | \
 586                                 common_dimm->rcw[9] << 24 | \
 587                                 common_dimm->rcw[10] << 20 | \
 588                                 common_dimm->rcw[11] << 16 | \
 589                                 common_dimm->rcw[12] << 12 | \
 590                                 common_dimm->rcw[13] << 8 | \
 591                                 common_dimm->rcw[14] << 4 | \
 592                                 common_dimm->rcw[15];
 593                 }
 594                 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
 595                 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
 596         }
 597 }
 598
 599 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
 600 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 601                                const memctl_options_t *popts,
 602                                const common_timing_params_t *common_dimm)
 603 {
 604         unsigned int mem_en;            /* DDR SDRAM interface logic enable */
 605         unsigned int sren;              /* Self refresh enable (during sleep) */
 606         unsigned int ecc_en;            /* ECC enable. */
 607         unsigned int rd_en;             /* Registered DIMM enable */
 608         unsigned int sdram_type;        /* Type of SDRAM */
 609         unsigned int dyn_pwr;           /* Dynamic power management mode */
 610         unsigned int dbw;               /* DRAM dta bus width */
 611         unsigned int eight_be = 0;      /* 8-beat burst enable, DDR2 is zero */
 612         unsigned int ncap = 0;          /* Non-concurrent auto-precharge */
 613         unsigned int threeT_en;         /* Enable 3T timing */
 614         unsigned int twoT_en;           /* Enable 2T timing */
 615         unsigned int ba_intlv_ctl;      /* Bank (CS) interleaving control */
 616         unsigned int x32_en = 0;        /* x32 enable */
 617         unsigned int pchb8 = 0;         /* precharge bit 8 enable */
 618         unsigned int hse;               /* Global half strength override */
 619         unsigned int mem_halt = 0;      /* memory controller halt */
 620         unsigned int bi = 0;            /* Bypass initialization */
 621
 622         mem_en = 1;
 623         sren = popts->self_refresh_in_sleep;
 624         if (common_dimm->all_DIMMs_ECC_capable) {
 625                 /* Allow setting of ECC only if all DIMMs are ECC. */
 626                 ecc_en = popts->ECC_mode;
 627         } else {
 628                 ecc_en = 0;
 629         }
 630
 631         if (common_dimm->all_DIMMs_registered
 632                 && !common_dimm->all_DIMMs_unbuffered) {
 633                 rd_en = 1;
 634                 twoT_en = 0;
 635         } else {
 636                 rd_en = 0;
 637                 twoT_en = popts->twoT_en;
 638         }
 639
 640         sdram_type = CONFIG_FSL_SDRAM_TYPE;
 641
 642         dyn_pwr = popts->dynamic_power;
 643         dbw = popts->data_bus_width;
 644         /* 8-beat burst enable DDR-III case
 645          * we must clear it when use the on-the-fly mode,
 646          * must set it when use the 32-bits bus mode.
 647          */
 648         if (sdram_type == SDRAM_TYPE_DDR3) {
 649                 if (popts->burst_length == DDR_BL8)
 650                         eight_be = 1;
 651                 if (popts->burst_length == DDR_OTF)
 652                         eight_be = 0;
 653                 if (dbw == 0x1)
 654                         eight_be = 1;
 655         }
 656
 657         threeT_en = popts->threeT_en;
 658         ba_intlv_ctl = popts->ba_intlv_ctl;
 659         hse = popts->half_strength_driver_enable;
 660
 661         ddr->ddr_sdram_cfg = (0
 662                         | ((mem_en & 0x1) << 31)
 663                         | ((sren & 0x1) << 30)
 664                         | ((ecc_en & 0x1) << 29)
 665                         | ((rd_en & 0x1) << 28)
 666                         | ((sdram_type & 0x7) << 24)
 667                         | ((dyn_pwr & 0x1) << 21)
 668                         | ((dbw & 0x3) << 19)
 669                         | ((eight_be & 0x1) << 18)
 670                         | ((ncap & 0x1) << 17)
 671                         | ((threeT_en & 0x1) << 16)
 672                         | ((twoT_en & 0x1) << 15)
 673                         | ((ba_intlv_ctl & 0x7F) << 8)
 674                         | ((x32_en & 0x1) << 5)
 675                         | ((pchb8 & 0x1) << 4)
 676                         | ((hse & 0x1) << 3)
 677                         | ((mem_halt & 0x1) << 1)
 678                         | ((bi & 0x1) << 0)
 679                         );
 680         debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
 681 }
 682
 683 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
 684 static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 685                                const memctl_options_t *popts,
 686                                const unsigned int unq_mrs_en)
 687 {
 688         unsigned int frc_sr = 0;        /* Force self refresh */
 689         unsigned int sr_ie = 0;         /* Self-refresh interrupt enable */
 690         unsigned int dll_rst_dis;       /* DLL reset disable */
 691         unsigned int dqs_cfg;           /* DQS configuration */
 692         unsigned int odt_cfg = 0;       /* ODT configuration */
 693         unsigned int num_pr;            /* Number of posted refreshes */
 694         unsigned int slow = 0;          /* DDR will be run less than 1250 */
 695         unsigned int obc_cfg;           /* On-The-Fly Burst Chop Cfg */
 696         unsigned int ap_en;             /* Address Parity Enable */
 697         unsigned int d_init;            /* DRAM data initialization */
 698         unsigned int rcw_en = 0;        /* Register Control Word Enable */
 699         unsigned int md_en = 0;         /* Mirrored DIMM Enable */
 700         unsigned int qd_en = 0;         /* quad-rank DIMM Enable */
 701         int i;
 702
 703         dll_rst_dis = 1;        /* Make this configurable */
 704         dqs_cfg = popts->DQS_config;
 705         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 706                 if (popts->cs_local_opts[i].odt_rd_cfg
 707                         || popts->cs_local_opts[i].odt_wr_cfg) {
 708                         odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
 709                         break;
 710                 }
 711         }
 712
 713         num_pr = 1;     /* Make this configurable */
 714
 715         /*
 716          * 8572 manual says
 717          *     {TIMING_CFG_1[PRETOACT]
 718          *      + [DDR_SDRAM_CFG_2[NUM_PR]
 719          *        * ({EXT_REFREC || REFREC} + 8 + 2)]}
 720          *      << DDR_SDRAM_INTERVAL[REFINT]
 721          */
 722 #if defined(CONFIG_FSL_DDR3)
 723         obc_cfg = popts->OTF_burst_chop_en;
 724 #else
 725         obc_cfg = 0;
 726 #endif
 727
 728 #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
 729         slow = get_ddr_freq(0) < 1249000000;
 730 #endif
 731
 732         if (popts->registered_dimm_en) {
 733                 rcw_en = 1;
 734                 ap_en = popts->ap_en;
 735         } else {
 736                 ap_en = 0;
 737         }
 738
 739 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 740         /* Use the DDR controller to auto initialize memory. */
 741         d_init = popts->ECC_init_using_memctl;
 742         ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
 743         debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
 744 #else
 745         /* Memory will be initialized via DMA, or not at all. */
 746         d_init = 0;
 747 #endif
 748
 749 #if defined(CONFIG_FSL_DDR3)
 750         md_en = popts->mirrored_dimm;
 751 #endif
 752         qd_en = popts->quad_rank_present ? 1 : 0;
 753         ddr->ddr_sdram_cfg_2 = (0
 754                 | ((frc_sr & 0x1) << 31)
 755                 | ((sr_ie & 0x1) << 30)
 756                 | ((dll_rst_dis & 0x1) << 29)
 757                 | ((dqs_cfg & 0x3) << 26)
 758                 | ((odt_cfg & 0x3) << 21)
 759                 | ((num_pr & 0xf) << 12)
 760                 | ((slow & 1) << 11)
 761                 | (qd_en << 9)
 762                 | (unq_mrs_en << 8)
 763                 | ((obc_cfg & 0x1) << 6)
 764                 | ((ap_en & 0x1) << 5)
 765                 | ((d_init & 0x1) << 4)
 766                 | ((rcw_en & 0x1) << 2)
 767                 | ((md_en & 0x1) << 0)
 768                 );
 769         debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
 770 }
 771
 772 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
 773 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
 774                                 const memctl_options_t *popts,
 775                                 const unsigned int unq_mrs_en)
 776 {
 777         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
 778         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
 779
 780 #if defined(CONFIG_FSL_DDR3)
 781         int i;
 782         unsigned int rtt_wr = 0;        /* Rtt_WR - dynamic ODT off */
 783         unsigned int srt = 0;   /* self-refresh temerature, normal range */
 784         unsigned int asr = 0;   /* auto self-refresh disable */
 785         unsigned int cwl = compute_cas_write_latency() - 5;
 786         unsigned int pasr = 0;  /* partial array self refresh disable */
 787
 788         if (popts->rtt_override)
 789                 rtt_wr = popts->rtt_wr_override_value;
 790         else
 791                 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
 792         esdmode2 = (0
 793                 | ((rtt_wr & 0x3) << 9)
 794                 | ((srt & 0x1) << 7)
 795                 | ((asr & 0x1) << 6)
 796                 | ((cwl & 0x7) << 3)
 797                 | ((pasr & 0x7) << 0));
 798 #endif
 799         ddr->ddr_sdram_mode_2 = (0
 800                                  | ((esdmode2 & 0xFFFF) << 16)
 801                                  | ((esdmode3 & 0xFFFF) << 0)
 802                                  );
 803         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
 804
 805 #ifdef CONFIG_FSL_DDR3
 806         if (unq_mrs_en) {       /* unique mode registers are supported */
 807                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 808                         if (popts->rtt_override)
 809                                 rtt_wr = popts->rtt_wr_override_value;
 810                         else
 811                                 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
 812
 813                         esdmode2 &= 0xF9FF;     /* clear bit 10, 9 */
 814                         esdmode2 |= (rtt_wr & 0x3) << 9;
 815                         switch (i) {
 816                         case 1:
 817                                 ddr->ddr_sdram_mode_4 = (0
 818                                         | ((esdmode2 & 0xFFFF) << 16)
 819                                         | ((esdmode3 & 0xFFFF) << 0)
 820                                         );
 821                                 break;
 822                         case 2:
 823                                 ddr->ddr_sdram_mode_6 = (0
 824                                         | ((esdmode2 & 0xFFFF) << 16)
 825                                         | ((esdmode3 & 0xFFFF) << 0)
 826                                         );
 827                                 break;
 828                         case 3:
 829                                 ddr->ddr_sdram_mode_8 = (0
 830                                         | ((esdmode2 & 0xFFFF) << 16)
 831                                         | ((esdmode3 & 0xFFFF) << 0)
 832                                         );
 833                                 break;
 834                         }
 835                 }
 836                 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
 837                         ddr->ddr_sdram_mode_4);
 838                 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
 839                         ddr->ddr_sdram_mode_6);
 840                 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
 841                         ddr->ddr_sdram_mode_8);
 842         }
 843 #endif
 844 }
 845
 846 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
 847 static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
 848                                const memctl_options_t *popts,
 849                                const common_timing_params_t *common_dimm)
 850 {
 851         unsigned int refint;    /* Refresh interval */
 852         unsigned int bstopre;   /* Precharge interval */
 853
 854         refint = picos_to_mclk(common_dimm->refresh_rate_ps);
 855
 856         bstopre = popts->bstopre;
 857
 858         /* refint field used 0x3FFF in earlier controllers */
 859         ddr->ddr_sdram_interval = (0
 860                                    | ((refint & 0xFFFF) << 16)
 861                                    | ((bstopre & 0x3FFF) << 0)
 862                                    );
 863         debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
 864 }
 865
 866 #if defined(CONFIG_FSL_DDR3)
 867 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
 868 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 869                                const memctl_options_t *popts,
 870                                const common_timing_params_t *common_dimm,
 871                                unsigned int cas_latency,
 872                                unsigned int additive_latency,
 873                                const unsigned int unq_mrs_en)
 874 {
 875         unsigned short esdmode;         /* Extended SDRAM mode */
 876         unsigned short sdmode;          /* SDRAM mode */
 877
 878         /* Mode Register - MR1 */
 879         unsigned int qoff = 0;          /* Output buffer enable 0=yes, 1=no */
 880         unsigned int tdqs_en = 0;       /* TDQS Enable: 0=no, 1=yes */
 881         unsigned int rtt;
 882         unsigned int wrlvl_en = 0;      /* Write level enable: 0=no, 1=yes */
 883         unsigned int al = 0;            /* Posted CAS# additive latency (AL) */
 884         unsigned int dic = 0;           /* Output driver impedance, 40ohm */
 885         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
 886                                                        1=Disable (Test/Debug) */
 887
 888         /* Mode Register - MR0 */
 889         unsigned int dll_on;    /* DLL control for precharge PD, 0=off, 1=on */
 890         unsigned int wr = 0;    /* Write Recovery */
 891         unsigned int dll_rst;   /* DLL Reset */
 892         unsigned int mode;      /* Normal=0 or Test=1 */
 893         unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
 894         /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
 895         unsigned int bt;
 896         unsigned int bl;        /* BL: Burst Length */
 897
 898         unsigned int wr_mclk;
 899         /*
 900          * DDR_SDRAM_MODE doesn't support 9,11,13,15
 901          * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
 902          * for this table
 903          */
 904         static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
 905
 906         const unsigned int mclk_ps = get_memory_clk_period_ps();
 907         int i;
 908
 909         if (popts->rtt_override)
 910                 rtt = popts->rtt_override_value;
 911         else
 912                 rtt = popts->cs_local_opts[0].odt_rtt_norm;
 913
 914         if (additive_latency == (cas_latency - 1))
 915                 al = 1;
 916         if (additive_latency == (cas_latency - 2))
 917                 al = 2;
 918
 919         if (popts->quad_rank_present)
 920                 dic = 1;        /* output driver impedance 240/7 ohm */
 921
 922         /*
 923          * The esdmode value will also be used for writing
 924          * MR1 during write leveling for DDR3, although the
 925          * bits specifically related to the write leveling
 926          * scheme will be handled automatically by the DDR
 927          * controller. so we set the wrlvl_en = 0 here.
 928          */
 929         esdmode = (0
 930                 | ((qoff & 0x1) << 12)
 931                 | ((tdqs_en & 0x1) << 11)
 932                 | ((rtt & 0x4) << 7)   /* rtt field is split */
 933                 | ((wrlvl_en & 0x1) << 7)
 934                 | ((rtt & 0x2) << 5)   /* rtt field is split */
 935                 | ((dic & 0x2) << 4)   /* DIC field is split */
 936                 | ((al & 0x3) << 3)
 937                 | ((rtt & 0x1) << 2)  /* rtt field is split */
 938                 | ((dic & 0x1) << 1)   /* DIC field is split */
 939                 | ((dll_en & 0x1) << 0)
 940                 );
 941
 942         /*
 943          * DLL control for precharge PD
 944          * 0=slow exit DLL off (tXPDLL)
 945          * 1=fast exit DLL on (tXP)
 946          */
 947         dll_on = 1;
 948
 949         wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps;
 950         if (wr_mclk <= 16) {
 951                 wr = wr_table[wr_mclk - 5];
 952         } else {
 953                 printf("Error: unsupported write recovery for mode register "
 954                        "wr_mclk = %d\n", wr_mclk);
 955         }
 956
 957         dll_rst = 0;    /* dll no reset */
 958         mode = 0;       /* normal mode */
 959
 960         /* look up table to get the cas latency bits */
 961         if (cas_latency >= 5 && cas_latency <= 16) {
 962                 unsigned char cas_latency_table[] = {
 963                         0x2,    /* 5 clocks */
 964                         0x4,    /* 6 clocks */
 965                         0x6,    /* 7 clocks */
 966                         0x8,    /* 8 clocks */
 967                         0xa,    /* 9 clocks */
 968                         0xc,    /* 10 clocks */
 969                         0xe,    /* 11 clocks */
 970                         0x1,    /* 12 clocks */
 971                         0x3,    /* 13 clocks */
 972                         0x5,    /* 14 clocks */
 973                         0x7,    /* 15 clocks */
 974                         0x9,    /* 16 clocks */
 975                 };
 976                 caslat = cas_latency_table[cas_latency - 5];
 977         } else {
 978                 printf("Error: unsupported cas latency for mode register\n");
 979         }
 980
 981         bt = 0; /* Nibble sequential */
 982
 983         switch (popts->burst_length) {
 984         case DDR_BL8:
 985                 bl = 0;
 986                 break;
 987         case DDR_OTF:
 988                 bl = 1;
 989                 break;
 990         case DDR_BC4:
 991                 bl = 2;
 992                 break;
 993         default:
 994                 printf("Error: invalid burst length of %u specified. "
 995                         " Defaulting to on-the-fly BC4 or BL8 beats.\n",
 996                         popts->burst_length);
 997                 bl = 1;
 998                 break;
 999         }
1000
1001         sdmode = (0
1002                   | ((dll_on & 0x1) << 12)
1003                   | ((wr & 0x7) << 9)
1004                   | ((dll_rst & 0x1) << 8)
1005                   | ((mode & 0x1) << 7)
1006                   | (((caslat >> 1) & 0x7) << 4)
1007                   | ((bt & 0x1) << 3)
1008                   | ((caslat & 1) << 2)
1009                   | ((bl & 0x3) << 0)
1010                   );
1011
1012         ddr->ddr_sdram_mode = (0
1013                                | ((esdmode & 0xFFFF) << 16)
1014                                | ((sdmode & 0xFFFF) << 0)
1015                                );
1016
1017         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1018
1019         if (unq_mrs_en) {       /* unique mode registers are supported */
1020                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1021                         if (popts->rtt_override)
1022                                 rtt = popts->rtt_override_value;
1023                         else
1024                                 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1025
1026                         esdmode &= 0xFDBB;      /* clear bit 9,6,2 */
1027                         esdmode |= (0
1028                                 | ((rtt & 0x4) << 7)   /* rtt field is split */
1029                                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1030                                 | ((rtt & 0x1) << 2)  /* rtt field is split */
1031                                 );
1032                         switch (i) {
1033                         case 1:
1034                                 ddr->ddr_sdram_mode_3 = (0
1035                                        | ((esdmode & 0xFFFF) << 16)
1036                                        | ((sdmode & 0xFFFF) << 0)
1037                                        );
1038                                 break;
1039                         case 2:
1040                                 ddr->ddr_sdram_mode_5 = (0
1041                                        | ((esdmode & 0xFFFF) << 16)
1042                                        | ((sdmode & 0xFFFF) << 0)
1043                                        );
1044                                 break;
1045                         case 3:
1046                                 ddr->ddr_sdram_mode_7 = (0
1047                                        | ((esdmode & 0xFFFF) << 16)
1048                                        | ((sdmode & 0xFFFF) << 0)
1049                                        );
1050                                 break;
1051                         }
1052                 }
1053                 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1054                         ddr->ddr_sdram_mode_3);
1055                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1056                         ddr->ddr_sdram_mode_5);
1057                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1058                         ddr->ddr_sdram_mode_5);
1059         }
1060 }
1061
1062 #else /* !CONFIG_FSL_DDR3 */
1063
1064 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1065 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
1066                                const memctl_options_t *popts,
1067                                const common_timing_params_t *common_dimm,
1068                                unsigned int cas_latency,
1069                                unsigned int additive_latency,
1070                                const unsigned int unq_mrs_en)
1071 {
1072         unsigned short esdmode;         /* Extended SDRAM mode */
1073         unsigned short sdmode;          /* SDRAM mode */
1074
1075         /*
1076          * FIXME: This ought to be pre-calculated in a
1077          * technology-specific routine,
1078          * e.g. compute_DDR2_mode_register(), and then the
1079          * sdmode and esdmode passed in as part of common_dimm.
1080          */
1081
1082         /* Extended Mode Register */
1083         unsigned int mrs = 0;           /* Mode Register Set */
1084         unsigned int outputs = 0;       /* 0=Enabled, 1=Disabled */
1085         unsigned int rdqs_en = 0;       /* RDQS Enable: 0=no, 1=yes */
1086         unsigned int dqs_en = 0;        /* DQS# Enable: 0=enable, 1=disable */
1087         unsigned int ocd = 0;           /* 0x0=OCD not supported,
1088                                            0x7=OCD default state */
1089         unsigned int rtt;
1090         unsigned int al;                /* Posted CAS# additive latency (AL) */
1091         unsigned int ods = 0;           /* Output Drive Strength:
1092                                                 0 = Full strength (18ohm)
1093                                                 1 = Reduced strength (4ohm) */
1094         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
1095                                                        1=Disable (Test/Debug) */
1096
1097         /* Mode Register (MR) */
1098         unsigned int mr;        /* Mode Register Definition */
1099         unsigned int pd;        /* Power-Down Mode */
1100         unsigned int wr;        /* Write Recovery */
1101         unsigned int dll_res;   /* DLL Reset */
1102         unsigned int mode;      /* Normal=0 or Test=1 */
1103         unsigned int caslat = 0;/* CAS# latency */
1104         /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1105         unsigned int bt;
1106         unsigned int bl;        /* BL: Burst Length */
1107
1108 #if defined(CONFIG_FSL_DDR2)
1109         const unsigned int mclk_ps = get_memory_clk_period_ps();
1110 #endif
1111         dqs_en = !popts->DQS_config;
1112         rtt = fsl_ddr_get_rtt();
1113
1114         al = additive_latency;
1115
1116         esdmode = (0
1117                 | ((mrs & 0x3) << 14)
1118                 | ((outputs & 0x1) << 12)
1119                 | ((rdqs_en & 0x1) << 11)
1120                 | ((dqs_en & 0x1) << 10)
1121                 | ((ocd & 0x7) << 7)
1122                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1123                 | ((al & 0x7) << 3)
1124                 | ((rtt & 0x1) << 2)   /* rtt field is split */
1125                 | ((ods & 0x1) << 1)
1126                 | ((dll_en & 0x1) << 0)
1127                 );
1128
1129         mr = 0;          /* FIXME: CHECKME */
1130
1131         /*
1132          * 0 = Fast Exit (Normal)
1133          * 1 = Slow Exit (Low Power)
1134          */
1135         pd = 0;
1136
1137 #if defined(CONFIG_FSL_DDR1)
1138         wr = 0;       /* Historical */
1139 #elif defined(CONFIG_FSL_DDR2)
1140         wr = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps - 1;
1141 #endif
1142         dll_res = 0;
1143         mode = 0;
1144
1145 #if defined(CONFIG_FSL_DDR1)
1146         if (1 <= cas_latency && cas_latency <= 4) {
1147                 unsigned char mode_caslat_table[4] = {
1148                         0x5,    /* 1.5 clocks */
1149                         0x2,    /* 2.0 clocks */
1150                         0x6,    /* 2.5 clocks */
1151                         0x3     /* 3.0 clocks */
1152                 };
1153                 caslat = mode_caslat_table[cas_latency - 1];
1154         } else {
1155                 printf("Warning: unknown cas_latency %d\n", cas_latency);
1156         }
1157 #elif defined(CONFIG_FSL_DDR2)
1158         caslat = cas_latency;
1159 #endif
1160         bt = 0;
1161
1162         switch (popts->burst_length) {
1163         case DDR_BL4:
1164                 bl = 2;
1165                 break;
1166         case DDR_BL8:
1167                 bl = 3;
1168                 break;
1169         default:
1170                 printf("Error: invalid burst length of %u specified. "
1171                         " Defaulting to 4 beats.\n",
1172                         popts->burst_length);
1173                 bl = 2;
1174                 break;
1175         }
1176
1177         sdmode = (0
1178                   | ((mr & 0x3) << 14)
1179                   | ((pd & 0x1) << 12)
1180                   | ((wr & 0x7) << 9)
1181                   | ((dll_res & 0x1) << 8)
1182                   | ((mode & 0x1) << 7)
1183                   | ((caslat & 0x7) << 4)
1184                   | ((bt & 0x1) << 3)
1185                   | ((bl & 0x7) << 0)
1186                   );
1187
1188         ddr->ddr_sdram_mode = (0
1189                                | ((esdmode & 0xFFFF) << 16)
1190                                | ((sdmode & 0xFFFF) << 0)
1191                                );
1192         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1193 }
1194 #endif
1195
1196 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1197 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1198 {
1199         unsigned int init_value;        /* Initialization value */
1200
1201         init_value = 0xDEADBEEF;
1202         ddr->ddr_data_init = init_value;
1203 }
1204
1205 /*
1206  * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1207  * The old controller on the 8540/60 doesn't have this register.
1208  * Hope it's OK to set it (to 0) anyway.
1209  */
1210 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1211                                          const memctl_options_t *popts)
1212 {
1213         unsigned int clk_adjust;        /* Clock adjust */
1214
1215         clk_adjust = popts->clk_adjust;
1216         ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
1217         debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1218 }
1219
1220 /* DDR Initialization Address (DDR_INIT_ADDR) */
1221 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1222 {
1223         unsigned int init_addr = 0;     /* Initialization address */
1224
1225         ddr->ddr_init_addr = init_addr;
1226 }
1227
1228 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1229 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1230 {
1231         unsigned int uia = 0;   /* Use initialization address */
1232         unsigned int init_ext_addr = 0; /* Initialization address */
1233
1234         ddr->ddr_init_ext_addr = (0
1235                                   | ((uia & 0x1) << 31)
1236                                   | (init_ext_addr & 0xF)
1237                                   );
1238 }
1239
1240 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
1241 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1242                                 const memctl_options_t *popts)
1243 {
1244         unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1245         unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1246         unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1247         unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1248         unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1249
1250 #if defined(CONFIG_FSL_DDR3)
1251         if (popts->burst_length == DDR_BL8) {
1252                 /* We set BL/2 for fixed BL8 */
1253                 rrt = 0;        /* BL/2 clocks */
1254                 wwt = 0;        /* BL/2 clocks */
1255         } else {
1256                 /* We need to set BL/2 + 2 to BC4 and OTF */
1257                 rrt = 2;        /* BL/2 + 2 clocks */
1258                 wwt = 2;        /* BL/2 + 2 clocks */
1259         }
1260         dll_lock = 1;   /* tDLLK = 512 clocks from spec */
1261 #endif
1262         ddr->timing_cfg_4 = (0
1263                              | ((rwt & 0xf) << 28)
1264                              | ((wrt & 0xf) << 24)
1265                              | ((rrt & 0xf) << 20)
1266                              | ((wwt & 0xf) << 16)
1267                              | (dll_lock & 0x3)
1268                              );
1269         debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1270 }
1271
1272 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1273 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1274 {
1275         unsigned int rodt_on = 0;       /* Read to ODT on */
1276         unsigned int rodt_off = 0;      /* Read to ODT off */
1277         unsigned int wodt_on = 0;       /* Write to ODT on */
1278         unsigned int wodt_off = 0;      /* Write to ODT off */
1279
1280 #if defined(CONFIG_FSL_DDR3)
1281         /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1282         rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1;
1283         rodt_off = 4;   /*  4 clocks */
1284         wodt_on = 1;    /*  1 clocks */
1285         wodt_off = 4;   /*  4 clocks */
1286 #endif
1287
1288         ddr->timing_cfg_5 = (0
1289                              | ((rodt_on & 0x1f) << 24)
1290                              | ((rodt_off & 0x7) << 20)
1291                              | ((wodt_on & 0x1f) << 12)
1292                              | ((wodt_off & 0x7) << 8)
1293                              );
1294         debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1295 }
1296
1297 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
1298 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
1299 {
1300         unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
1301         /* Normal Operation Full Calibration Time (tZQoper) */
1302         unsigned int zqoper = 0;
1303         /* Normal Operation Short Calibration Time (tZQCS) */
1304         unsigned int zqcs = 0;
1305
1306         if (zq_en) {
1307                 zqinit = 9;     /* 512 clocks */
1308                 zqoper = 8;     /* 256 clocks */
1309                 zqcs = 6;       /* 64 clocks */
1310         }
1311
1312         ddr->ddr_zq_cntl = (0
1313                             | ((zq_en & 0x1) << 31)
1314                             | ((zqinit & 0xF) << 24)
1315                             | ((zqoper & 0xF) << 16)
1316                             | ((zqcs & 0xF) << 8)
1317                             );
1318         debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
1319 }
1320
1321 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
1322 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
1323                                 const memctl_options_t *popts)
1324 {
1325         /*
1326          * First DQS pulse rising edge after margining mode
1327          * is programmed (tWL_MRD)
1328          */
1329         unsigned int wrlvl_mrd = 0;
1330         /* ODT delay after margining mode is programmed (tWL_ODTEN) */
1331         unsigned int wrlvl_odten = 0;
1332         /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
1333         unsigned int wrlvl_dqsen = 0;
1334         /* WRLVL_SMPL: Write leveling sample time */
1335         unsigned int wrlvl_smpl = 0;
1336         /* WRLVL_WLR: Write leveling repeition time */
1337         unsigned int wrlvl_wlr = 0;
1338         /* WRLVL_START: Write leveling start time */
1339         unsigned int wrlvl_start = 0;
1340
1341         /* suggest enable write leveling for DDR3 due to fly-by topology */
1342         if (wrlvl_en) {
1343                 /* tWL_MRD min = 40 nCK, we set it 64 */
1344                 wrlvl_mrd = 0x6;
1345                 /* tWL_ODTEN 128 */
1346                 wrlvl_odten = 0x7;
1347                 /* tWL_DQSEN min = 25 nCK, we set it 32 */
1348                 wrlvl_dqsen = 0x5;
1349                 /*
1350                  * Write leveling sample time at least need 6 clocks
1351                  * higher than tWLO to allow enough time for progagation
1352                  * delay and sampling the prime data bits.
1353                  */
1354                 wrlvl_smpl = 0xf;
1355                 /*
1356                  * Write leveling repetition time
1357                  * at least tWLO + 6 clocks clocks
1358                  * we set it 64
1359                  */
1360                 wrlvl_wlr = 0x6;
1361                 /*
1362                  * Write leveling start time
1363                  * The value use for the DQS_ADJUST for the first sample
1364                  * when write leveling is enabled. It probably needs to be
1365                  * overriden per platform.
1366                  */
1367                 wrlvl_start = 0x8;
1368                 /*
1369                  * Override the write leveling sample and start time
1370                  * according to specific board
1371                  */
1372                 if (popts->wrlvl_override) {
1373                         wrlvl_smpl = popts->wrlvl_sample;
1374                         wrlvl_start = popts->wrlvl_start;
1375                 }
1376         }
1377
1378         ddr->ddr_wrlvl_cntl = (0
1379                                | ((wrlvl_en & 0x1) << 31)
1380                                | ((wrlvl_mrd & 0x7) << 24)
1381                                | ((wrlvl_odten & 0x7) << 20)
1382                                | ((wrlvl_dqsen & 0x7) << 16)
1383                                | ((wrlvl_smpl & 0xf) << 12)
1384                                | ((wrlvl_wlr & 0x7) << 8)
1385                                | ((wrlvl_start & 0x1F) << 0)
1386                                );
1387         debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
1388         ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
1389         debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
1390         ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
1391         debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
1392
1393 }
1394
1395 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
1396 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
1397 {
1398         /* Self Refresh Idle Threshold */
1399         ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
1400 }
1401
1402 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1403 {
1404         if (popts->addr_hash) {
1405                 ddr->ddr_eor = 0x40000000;      /* address hash enable */
1406                 puts("Address hashing enabled.\n");
1407         }
1408 }
1409
1410 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1411 {
1412         ddr->ddr_cdr1 = popts->ddr_cdr1;
1413         debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
1414 }
1415
1416 static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1417 {
1418         ddr->ddr_cdr2 = popts->ddr_cdr2;
1419         debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
1420 }
1421
1422 unsigned int
1423 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
1424 {
1425         unsigned int res = 0;
1426
1427         /*
1428          * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
1429          * not set at the same time.
1430          */
1431         if (ddr->ddr_sdram_cfg & 0x10000000
1432             && ddr->ddr_sdram_cfg & 0x00008000) {
1433                 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
1434                                 " should not be set at the same time.\n");
1435                 res++;
1436         }
1437
1438         return res;
1439 }
1440
1441 unsigned int
1442 compute_fsl_memctl_config_regs(const memctl_options_t *popts,
1443                                fsl_ddr_cfg_regs_t *ddr,
1444                                const common_timing_params_t *common_dimm,
1445                                const dimm_params_t *dimm_params,
1446                                unsigned int dbw_cap_adj,
1447                                unsigned int size_only)
1448 {
1449         unsigned int i;
1450         unsigned int cas_latency;
1451         unsigned int additive_latency;
1452         unsigned int sr_it;
1453         unsigned int zq_en;
1454         unsigned int wrlvl_en;
1455         unsigned int ip_rev = 0;
1456         unsigned int unq_mrs_en = 0;
1457         int cs_en = 1;
1458
1459         memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
1460
1461         if (common_dimm == NULL) {
1462                 printf("Error: subset DIMM params struct null pointer\n");
1463                 return 1;
1464         }
1465
1466         /*
1467          * Process overrides first.
1468          *
1469          * FIXME: somehow add dereated caslat to this
1470          */
1471         cas_latency = (popts->cas_latency_override)
1472                 ? popts->cas_latency_override_value
1473                 : common_dimm->lowest_common_SPD_caslat;
1474
1475         additive_latency = (popts->additive_latency_override)
1476                 ? popts->additive_latency_override_value
1477                 : common_dimm->additive_latency;
1478
1479         sr_it = (popts->auto_self_refresh_en)
1480                 ? popts->sr_it
1481                 : 0;
1482         /* ZQ calibration */
1483         zq_en = (popts->zq_en) ? 1 : 0;
1484         /* write leveling */
1485         wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
1486
1487         /* Chip Select Memory Bounds (CSn_BNDS) */
1488         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1489                 unsigned long long ea, sa;
1490                 unsigned int cs_per_dimm
1491                         = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
1492                 unsigned int dimm_number
1493                         = i / cs_per_dimm;
1494                 unsigned long long rank_density
1495                         = dimm_params[dimm_number].rank_density >> dbw_cap_adj;
1496
1497                 if (dimm_params[dimm_number].n_ranks == 0) {
1498                         debug("Skipping setup of CS%u "
1499                                 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
1500                         continue;
1501                 }
1502                 if (popts->memctl_interleaving) {
1503                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1504                         case FSL_DDR_CS0_CS1_CS2_CS3:
1505                                 break;
1506                         case FSL_DDR_CS0_CS1:
1507                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1508                                 if (i > 1)
1509                                         cs_en = 0;
1510                                 break;
1511                         case FSL_DDR_CS2_CS3:
1512                         default:
1513                                 if (i > 0)
1514                                         cs_en = 0;
1515                                 break;
1516                         }
1517                         sa = common_dimm->base_address;
1518                         ea = sa + common_dimm->total_mem - 1;
1519                 } else if (!popts->memctl_interleaving) {
1520                         /*
1521                          * If memory interleaving between controllers is NOT
1522                          * enabled, the starting address for each memory
1523                          * controller is distinct.  However, because rank
1524                          * interleaving is enabled, the starting and ending
1525                          * addresses of the total memory on that memory
1526                          * controller needs to be programmed into its
1527                          * respective CS0_BNDS.
1528                          */
1529                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1530                         case FSL_DDR_CS0_CS1_CS2_CS3:
1531                                 sa = common_dimm->base_address;
1532                                 ea = sa + common_dimm->total_mem - 1;
1533                                 break;
1534                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1535                                 if ((i >= 2) && (dimm_number == 0)) {
1536                                         sa = dimm_params[dimm_number].base_address +
1537                                               2 * rank_density;
1538                                         ea = sa + 2 * rank_density - 1;
1539                                 } else {
1540                                         sa = dimm_params[dimm_number].base_address;
1541                                         ea = sa + 2 * rank_density - 1;
1542                                 }
1543                                 break;
1544                         case FSL_DDR_CS0_CS1:
1545                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1546                                         sa = dimm_params[dimm_number].base_address;
1547                                         ea = sa + rank_density - 1;
1548                                         if (i != 1)
1549                                                 sa += (i % cs_per_dimm) * rank_density;
1550                                         ea += (i % cs_per_dimm) * rank_density;
1551                                 } else {
1552                                         sa = 0;
1553                                         ea = 0;
1554                                 }
1555                                 if (i == 0)
1556                                         ea += rank_density;
1557                                 break;
1558                         case FSL_DDR_CS2_CS3:
1559                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1560                                         sa = dimm_params[dimm_number].base_address;
1561                                         ea = sa + rank_density - 1;
1562                                         if (i != 3)
1563                                                 sa += (i % cs_per_dimm) * rank_density;
1564                                         ea += (i % cs_per_dimm) * rank_density;
1565                                 } else {
1566                                         sa = 0;
1567                                         ea = 0;
1568                                 }
1569                                 if (i == 2)
1570                                         ea += (rank_density >> dbw_cap_adj);
1571                                 break;
1572                         default:  /* No bank(chip-select) interleaving */
1573                                 sa = dimm_params[dimm_number].base_address;
1574                                 ea = sa + rank_density - 1;
1575                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1576                                         sa += (i % cs_per_dimm) * rank_density;
1577                                         ea += (i % cs_per_dimm) * rank_density;
1578                                 } else {
1579                                         sa = 0;
1580                                         ea = 0;
1581                                 }
1582                                 break;
1583                         }
1584                 }
1585
1586                 sa >>= 24;
1587                 ea >>= 24;
1588
1589                 if (cs_en) {
1590                         ddr->cs[i].bnds = (0
1591                                 | ((sa & 0xFFF) << 16)/* starting address MSB */
1592                                 | ((ea & 0xFFF) << 0)   /* ending address MSB */
1593                                 );
1594                 } else {
1595                         debug("FSLDDR: setting bnds to 0 for inactive CS\n");
1596                         ddr->cs[i].bnds = 0;
1597                 }
1598
1599                 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
1600                 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1601                 set_csn_config_2(i, ddr);
1602         }
1603
1604         /*
1605          * In the case we only need to compute the ddr sdram size, we only need
1606          * to set csn registers, so return from here.
1607          */
1608         if (size_only)
1609                 return 0;
1610
1611         set_ddr_eor(ddr, popts);
1612
1613 #if !defined(CONFIG_FSL_DDR1)
1614         set_timing_cfg_0(ddr, popts, dimm_params);
1615 #endif
1616
1617         set_timing_cfg_3(ddr, popts, common_dimm, cas_latency);
1618         set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
1619         set_timing_cfg_2(ddr, popts, common_dimm,
1620                                 cas_latency, additive_latency);
1621
1622         set_ddr_cdr1(ddr, popts);
1623         set_ddr_cdr2(ddr, popts);
1624         set_ddr_sdram_cfg(ddr, popts, common_dimm);
1625         ip_rev = fsl_ddr_get_version();
1626         if (ip_rev > 0x40400)
1627                 unq_mrs_en = 1;
1628
1629         set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
1630         set_ddr_sdram_mode(ddr, popts, common_dimm,
1631                                 cas_latency, additive_latency, unq_mrs_en);
1632         set_ddr_sdram_mode_2(ddr, popts, unq_mrs_en);
1633         set_ddr_sdram_interval(ddr, popts, common_dimm);
1634         set_ddr_data_init(ddr);
1635         set_ddr_sdram_clk_cntl(ddr, popts);
1636         set_ddr_init_addr(ddr);
1637         set_ddr_init_ext_addr(ddr);
1638         set_timing_cfg_4(ddr, popts);
1639         set_timing_cfg_5(ddr, cas_latency);
1640
1641         set_ddr_zq_cntl(ddr, zq_en);
1642         set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
1643
1644         set_ddr_sr_cntr(ddr, sr_it);
1645
1646         set_ddr_sdram_rcw(ddr, popts, common_dimm);
1647
1648         return check_fsl_memctl_config_regs(ddr);
1649 }