1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
4 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
5 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
8 /* U-Boot - Startup Code for PowerPC based Embedded Boards
11 * The processor starts at 0x00000100 and the code is executed
12 * from flash. The code is organized to be at an other address
13 * in memory, but as long we don't jump around before relocating,
14 * board_init lies at a quite high address and when the cpu has
15 * jumped there, everything is ok.
16 * This works because the cpu gives the FLASH (CS0) the whole
17 * address space at startup, and board_init lies as a echo of
18 * the flash somewhere up there in the memory map.
20 * board_init will change CS0 to be positioned at the correct
21 * address and (s)dram will be positioned at address 0
23 #include <asm-offsets.h>
27 #include <ppc_asm.tmpl>
30 #include <asm/cache.h>
32 #include <asm/u-boot.h>
34 /* We don't want the MMU yet.
37 #define MSR_KERNEL ( MSR_ME | MSR_RI ) /* Machine Check and Recoverable Interr. */
40 * Set up GOT: Global Offset Table
42 * Use r12 to access the GOT
45 GOT_ENTRY(_GOT2_TABLE_)
46 GOT_ENTRY(_FIXUP_TABLE_)
49 GOT_ENTRY(_start_of_vectors)
50 GOT_ENTRY(_end_of_vectors)
51 GOT_ENTRY(transfer_to_handler)
55 GOT_ENTRY(__bss_start)
59 * r3 - 1st arg to board_init(): IMMP pointer
60 * r4 - 2nd arg to board_init(): boot flag
63 .long 0x27051956 /* U-Boot Magic Number */
68 lis r3, CONFIG_SYS_IMMR@h /* position IMMR */
71 /* Initialize machine status; enable machine check interrupt */
72 /*----------------------------------------------------------------------*/
73 li r3, MSR_KERNEL /* Set ME, RI flags */
75 mtspr SRR1, r3 /* Make SRR1 match MSR */
77 mfspr r3, ICR /* clear Interrupt Cause Register */
79 /* Initialize debug port registers */
80 /*----------------------------------------------------------------------*/
81 xor r0, r0, r0 /* Clear R0 */
82 mtspr LCTRL1, r0 /* Initialize debug port regs */
87 /* Reset the caches */
88 /*----------------------------------------------------------------------*/
90 mfspr r3, IC_CST /* Clear error bits */
93 lis r3, IDC_UNALL@h /* Unlock all */
97 lis r3, IDC_INVALL@h /* Invalidate all */
101 lis r3, IDC_DISABLE@h /* Disable data cache */
104 lis r3, IDC_ENABLE@h /* Enable instruction cache */
107 /* invalidate all tlb's */
108 /*----------------------------------------------------------------------*/
114 * Calculate absolute address in FLASH and jump there
115 *----------------------------------------------------------------------*/
117 lis r3, CONFIG_SYS_MONITOR_BASE@h
118 ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
119 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
125 /* initialize some SPRs that are hard to access from C */
126 /*----------------------------------------------------------------------*/
129 * Disable serialized ifetch and show cycles
130 * (i.e. set processor to normal mode).
131 * This is also a silicon bug workaround, see errata
137 /* Set up debug mode entry */
139 lis r2, CONFIG_SYS_DER@h
140 ori r2, r2, CONFIG_SYS_DER@l
143 /* set up the stack on top of internal DPRAM */
144 lis r3, CFG_SYS_INIT_SP@h
145 ori r3, r3, CFG_SYS_INIT_SP@l
150 lis r3, (CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE)@h
151 ori r3, r3, (CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE)@l
153 bl board_init_f_alloc_reserve
155 /* Zeroise the CPM dpram */
156 lis r4, CONFIG_SYS_IMMR@h
157 ori r4, r4, (0x2000 - 4)
164 bl board_init_f_init_reserve
166 /* let the C-code set up the rest */
168 /* Be careful to keep code relocatable ! */
169 /*----------------------------------------------------------------------*/
171 GET_GOT /* initialize GOT access */
173 lis r3, CONFIG_SYS_IMMR@h
174 bl cpu_init_f /* run low-level CPU init code (from Flash) */
176 li r3, 0 /* clear boot_flag for calling board_init_f */
177 bl board_init_f /* run 1st part of board init code (from Flash) */
179 /* NOTREACHED - board_init_f() does not return */
182 .globl _start_of_vectors
186 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
188 /* Data Storage exception. "Never" generated on the 860. */
189 STD_EXCEPTION(0x300, DataStorage, UnknownException)
191 /* Instruction Storage exception. "Never" generated on the 860. */
192 STD_EXCEPTION(0x400, InstStorage, UnknownException)
194 /* External Interrupt exception. */
195 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
197 /* Alignment exception. */
200 EXCEPTION_PROLOG(SRR0, SRR1)
205 addi r3,r1,STACK_FRAME_OVERHEAD
206 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
208 /* Program check exception */
211 EXCEPTION_PROLOG(SRR0, SRR1)
212 addi r3,r1,STACK_FRAME_OVERHEAD
213 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
216 /* No FPU on MPC8xx. This exception is not supposed to happen.
218 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
220 /* I guess we could implement decrementer, and may have
221 * to someday for timekeeping.
223 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
224 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
225 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
226 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
227 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
229 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
230 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
232 /* On the MPC8xx, this is a software emulation interrupt. It occurs
233 * for all unimplemented and illegal instructions.
235 STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
237 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
238 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
239 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
240 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
242 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
243 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
244 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
245 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
246 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
247 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
248 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
250 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
251 STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
252 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
253 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
256 .globl _end_of_vectors
263 * This code finishes saving the registers to the exception frame
264 * and jumps to the appropriate handler for the exception.
265 * Register r21 is pointer into trap frame, r1 has new stack pointer.
267 .globl transfer_to_handler
278 andi. r24,r23,0x3f00 /* get vector offset */
282 mtspr SPRG2,r22 /* r1 is now kernel sp */
283 lwz r24,0(r23) /* virtual address of handler */
284 lwz r23,4(r23) /* where to go when done */
289 rfi /* jump to handler, enable MMU */
292 mfmsr r28 /* Disable interrupts */
296 SYNC /* Some chip revs need this... */
311 lwz r2,_NIP(r1) /* Restore environment */
321 /*------------------------------------------------------------------------------*/
324 * void relocate_code(addr_sp, gd, addr_moni)
326 * This "function" does not return, instead it continues in RAM
327 * after relocating the monitor code.
331 * r5 = length in bytes
336 mr r1, r3 /* Set new stack pointer */
337 mr r9, r4 /* Save copy of Global Data pointer */
338 mr r10, r5 /* Save copy of Destination Address */
341 mr r3, r5 /* Destination Address */
342 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
343 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
344 lwz r5, GOT(__init_end)
346 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
351 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
357 /* First our own GOT */
359 /* then the one used by the C code */
369 beq cr1,4f /* In place copy is not necessary */
370 beq 7f /* Protect against 0 count */
389 * Now flush the cache: note that we must start from a cache aligned
390 * address. Otherwise we might miss one cache line.
394 beq 7f /* Always flush prefetch queue in any case */
402 sync /* Wait for all dcbst to complete on bus */
408 7: sync /* Wait for all icbi to complete on bus */
412 * We are done. Do not return, instead branch to second part of board
413 * initialization, now running from RAM.
416 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
423 * Relocation Function, r12 point to got2+0x8000
425 * Adjust got2 pointers, no need to check for 0, this code
426 * already puts a few entries in the table.
428 li r0,__got2_entries@sectoff@l
429 la r3,GOT(_GOT2_TABLE_)
430 lwz r11,GOT(_GOT2_TABLE_)
442 * Now adjust the fixups and the pointers to the fixups
443 * in case we need to move ourselves again.
445 li r0,__fixup_entries@sectoff@l
446 lwz r3,GOT(_FIXUP_TABLE_)
462 * Now clear BSS segment
464 lwz r3,GOT(__bss_start)
465 lwz r4,GOT(__bss_end)
478 mr r3, r9 /* Global Data pointer */
479 mr r4, r10 /* Destination Address */
483 * Copy exception vector code to low memory
486 * r7: source address, r8: end address, r9: target address
490 mflr r4 /* save link register */
493 lwz r8, GOT(_end_of_vectors)
495 li r9, 0x100 /* reset vector always at 0x100 */
498 bgelr /* return if r7>=r8 - just in case */
508 * relocate `hdlr' and `int_return' entries
510 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
511 li r8, Alignment - _start + EXC_OFF_SYS_RESET
514 addi r7, r7, 0x100 /* next exception vector */
518 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
521 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
524 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
525 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
528 addi r7, r7, 0x100 /* next exception vector */
532 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
533 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
536 addi r7, r7, 0x100 /* next exception vector */
540 mtlr r4 /* restore link register */