2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
6 * SPDX-License-Identifier: GPL-2.0+
9 /* U-Boot - Startup Code for PowerPC based Embedded Boards
12 * The processor starts at 0x00000100 and the code is executed
13 * from flash. The code is organized to be at an other address
14 * in memory, but as long we don't jump around before relocating,
15 * board_init lies at a quite high address and when the cpu has
16 * jumped there, everything is ok.
17 * This works because the cpu gives the FLASH (CS0) the whole
18 * address space at startup, and board_init lies as a echo of
19 * the flash somewhere up there in the memory map.
21 * board_init will change CS0 to be positioned at the correct
22 * address and (s)dram will be positioned at address 0
24 #include <asm-offsets.h>
29 #include <ppc_asm.tmpl>
32 #include <asm/cache.h>
34 #include <asm/u-boot.h>
36 /* We don't want the MMU yet.
39 #define MSR_KERNEL ( MSR_ME | MSR_RI ) /* Machine Check and Recoverable Interr. */
42 * Set up GOT: Global Offset Table
44 * Use r12 to access the GOT
47 GOT_ENTRY(_GOT2_TABLE_)
48 GOT_ENTRY(_FIXUP_TABLE_)
51 GOT_ENTRY(_start_of_vectors)
52 GOT_ENTRY(_end_of_vectors)
53 GOT_ENTRY(transfer_to_handler)
57 GOT_ENTRY(__bss_start)
61 * r3 - 1st arg to board_init(): IMMP pointer
62 * r4 - 2nd arg to board_init(): boot flag
65 .long 0x27051956 /* U-Boot Magic Number */
68 .ascii U_BOOT_VERSION_STRING, "\0"
73 lis r3, CONFIG_SYS_IMMR@h /* position IMMR */
76 /* Initialize machine status; enable machine check interrupt */
77 /*----------------------------------------------------------------------*/
78 li r3, MSR_KERNEL /* Set ME, RI flags */
80 mtspr SRR1, r3 /* Make SRR1 match MSR */
82 mfspr r3, ICR /* clear Interrupt Cause Register */
84 /* Initialize debug port registers */
85 /*----------------------------------------------------------------------*/
86 xor r0, r0, r0 /* Clear R0 */
87 mtspr LCTRL1, r0 /* Initialize debug port regs */
92 /* Reset the caches */
93 /*----------------------------------------------------------------------*/
95 mfspr r3, IC_CST /* Clear error bits */
98 lis r3, IDC_UNALL@h /* Unlock all */
102 lis r3, IDC_INVALL@h /* Invalidate all */
106 lis r3, IDC_DISABLE@h /* Disable data cache */
109 lis r3, IDC_ENABLE@h /* Enable instruction cache */
112 /* invalidate all tlb's */
113 /*----------------------------------------------------------------------*/
119 * Calculate absolute address in FLASH and jump there
120 *----------------------------------------------------------------------*/
122 lis r3, CONFIG_SYS_MONITOR_BASE@h
123 ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
124 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
130 /* initialize some SPRs that are hard to access from C */
131 /*----------------------------------------------------------------------*/
133 lis r3, CONFIG_SYS_IMMR@h /* pass IMMR as arg1 to C routine */
134 ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in internal DPRAM */
135 /* Note: R0 is still 0 here */
136 stwu r0, -4(r1) /* clear final stack frame so that */
137 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
140 * Disable serialized ifetch and show cycles
141 * (i.e. set processor to normal mode).
142 * This is also a silicon bug workaround, see errata
148 /* Set up debug mode entry */
150 lis r2, CONFIG_SYS_DER@h
151 ori r2, r2, CONFIG_SYS_DER@l
154 /* let the C-code set up the rest */
156 /* Be careful to keep code relocatable ! */
157 /*----------------------------------------------------------------------*/
159 GET_GOT /* initialize GOT access */
162 bl cpu_init_f /* run low-level CPU init code (from Flash) */
164 bl board_init_f /* run 1st part of board init code (from Flash) */
166 /* NOTREACHED - board_init_f() does not return */
169 .globl _start_of_vectors
173 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
175 /* Data Storage exception. "Never" generated on the 860. */
176 STD_EXCEPTION(0x300, DataStorage, UnknownException)
178 /* Instruction Storage exception. "Never" generated on the 860. */
179 STD_EXCEPTION(0x400, InstStorage, UnknownException)
181 /* External Interrupt exception. */
182 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
184 /* Alignment exception. */
187 EXCEPTION_PROLOG(SRR0, SRR1)
192 addi r3,r1,STACK_FRAME_OVERHEAD
193 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
195 /* Program check exception */
198 EXCEPTION_PROLOG(SRR0, SRR1)
199 addi r3,r1,STACK_FRAME_OVERHEAD
200 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
203 /* No FPU on MPC8xx. This exception is not supposed to happen.
205 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
207 /* I guess we could implement decrementer, and may have
208 * to someday for timekeeping.
210 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
211 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
212 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
213 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
214 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
216 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
217 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
219 /* On the MPC8xx, this is a software emulation interrupt. It occurs
220 * for all unimplemented and illegal instructions.
222 STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
224 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
225 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
226 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
227 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
229 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
230 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
231 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
232 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
233 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
234 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
235 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
237 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
238 STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
239 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
240 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
243 .globl _end_of_vectors
250 * This code finishes saving the registers to the exception frame
251 * and jumps to the appropriate handler for the exception.
252 * Register r21 is pointer into trap frame, r1 has new stack pointer.
254 .globl transfer_to_handler
265 andi. r24,r23,0x3f00 /* get vector offset */
269 mtspr SPRG2,r22 /* r1 is now kernel sp */
270 lwz r24,0(r23) /* virtual address of handler */
271 lwz r23,4(r23) /* where to go when done */
276 rfi /* jump to handler, enable MMU */
279 mfmsr r28 /* Disable interrupts */
283 SYNC /* Some chip revs need this... */
298 lwz r2,_NIP(r1) /* Restore environment */
309 * unsigned int get_immr (unsigned int mask)
311 * return (mask ? (IMMR & mask) : IMMR);
315 mr r4,r3 /* save mask */
316 mfspr r3, IMMR /* IMMR */
317 cmpwi 0,r4,0 /* mask != 0 ? */
319 and r3,r3,r4 /* IMMR & mask */
360 /*------------------------------------------------------------------------------*/
363 * void relocate_code (addr_sp, gd, addr_moni)
365 * This "function" does not return, instead it continues in RAM
366 * after relocating the monitor code.
370 * r5 = length in bytes
375 mr r1, r3 /* Set new stack pointer */
376 mr r9, r4 /* Save copy of Global Data pointer */
377 mr r10, r5 /* Save copy of Destination Address */
380 mr r3, r5 /* Destination Address */
381 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
382 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
383 lwz r5, GOT(__init_end)
385 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
390 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
396 /* First our own GOT */
398 /* then the one used by the C code */
408 beq cr1,4f /* In place copy is not necessary */
409 beq 7f /* Protect against 0 count */
428 * Now flush the cache: note that we must start from a cache aligned
429 * address. Otherwise we might miss one cache line.
433 beq 7f /* Always flush prefetch queue in any case */
441 sync /* Wait for all dcbst to complete on bus */
447 7: sync /* Wait for all icbi to complete on bus */
451 * We are done. Do not return, instead branch to second part of board
452 * initialization, now running from RAM.
455 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
462 * Relocation Function, r12 point to got2+0x8000
464 * Adjust got2 pointers, no need to check for 0, this code
465 * already puts a few entries in the table.
467 li r0,__got2_entries@sectoff@l
468 la r3,GOT(_GOT2_TABLE_)
469 lwz r11,GOT(_GOT2_TABLE_)
481 * Now adjust the fixups and the pointers to the fixups
482 * in case we need to move ourselves again.
484 li r0,__fixup_entries@sectoff@l
485 lwz r3,GOT(_FIXUP_TABLE_)
501 * Now clear BSS segment
503 lwz r3,GOT(__bss_start)
504 lwz r4,GOT(__bss_end)
517 mr r3, r9 /* Global Data pointer */
518 mr r4, r10 /* Destination Address */
522 * Copy exception vector code to low memory
525 * r7: source address, r8: end address, r9: target address
529 mflr r4 /* save link register */
532 lwz r8, GOT(_end_of_vectors)
534 li r9, 0x100 /* reset vector always at 0x100 */
537 bgelr /* return if r7>=r8 - just in case */
547 * relocate `hdlr' and `int_return' entries
549 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
550 li r8, Alignment - _start + EXC_OFF_SYS_RESET
553 addi r7, r7, 0x100 /* next exception vector */
557 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
560 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
563 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
564 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
567 addi r7, r7, 0x100 /* next exception vector */
571 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
572 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
575 addi r7, r7, 0x100 /* next exception vector */
579 mtlr r4 /* restore link register */