2 * Copyright (c) 2001 Navin Boppuri / Prashant Patel
3 * <nboppuri@trinetcommunication.com>,
4 * <pmpatel@trinetcommunication.com>
5 * Copyright (c) 2001 Gerd Mennchen <Gerd.Mennchen@icn.siemens.de>
6 * Copyright (c) 2001 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>.
8 * SPDX-License-Identifier: GPL-2.0+
12 * MPC8xx CPM SPI interface.
14 * Parts of this code are probably not portable and/or specific to
15 * the board which I used for the tests. Please send fixes/complaints
23 #include <linux/ctype.h>
30 #define SPI_EEPROM_WREN 0x06
31 #define SPI_EEPROM_RDSR 0x05
32 #define SPI_EEPROM_READ 0x03
33 #define SPI_EEPROM_WRITE 0x02
35 /* ---------------------------------------------------------------
36 * Offset for initial SPI buffers in DPRAM:
37 * We need a 520 byte scratch DPRAM area to use at an early stage.
38 * It is used between the two initialization calls (spi_init_f()
40 * The value 0xb00 makes it far enough from the start of the data
41 * area (as well as from the stack pointer).
42 * --------------------------------------------------------------- */
43 #ifndef CONFIG_SYS_SPI_INIT_OFFSET
44 #define CONFIG_SYS_SPI_INIT_OFFSET 0xB00
47 #define CPM_SPI_BASE_RX CPM_SPI_BASE
48 #define CPM_SPI_BASE_TX (CPM_SPI_BASE + sizeof(cbd_t))
50 /* -------------------
52 * ------------------- */
55 ssize_t spi_read (uchar *, int, uchar *, int);
56 ssize_t spi_write (uchar *, int, uchar *, int);
57 ssize_t spi_xfer (size_t);
59 /* -------------------
61 * ------------------- */
63 #define MAX_BUFFER 0x104
65 /* ----------------------------------------------------------------------
66 * Initially we place the RX and TX buffers at a fixed location in DPRAM!
67 * ---------------------------------------------------------------------- */
69 (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem
70 [CONFIG_SYS_SPI_INIT_OFFSET];
72 (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem
73 [CONFIG_SYS_SPI_INIT_OFFSET+MAX_BUFFER];
75 /* **************************************************************************
77 * Function: spi_init_f
79 * Description: Init SPI-Controller (ROM part)
83 * *********************************************************************** */
84 void spi_init_f (void)
86 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
87 cpm8xx_t __iomem *cp = &immr->im_cpm;
88 spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI];
89 cbd_t __iomem *tbdf, *rbdf;
91 /* Disable relocation */
92 out_be16(&spi->spi_rpbase, 0);
95 /* ------------------------------------------------
96 * Initialize Port B SPI pins -> page 34-8 MPC860UM
97 * (we are only in Master Mode !)
98 * ------------------------------------------------ */
100 /* --------------------------------------------
101 * GPIO or per. Function
102 * PBPAR[28] = 1 [0x00000008] -> PERI: (SPIMISO)
103 * PBPAR[29] = 1 [0x00000004] -> PERI: (SPIMOSI)
104 * PBPAR[30] = 1 [0x00000002] -> PERI: (SPICLK)
105 * PBPAR[31] = 0 [0x00000001] -> GPIO: (CS for PCUE/CCM-EEPROM)
106 * -------------------------------------------- */
107 clrsetbits_be32(&cp->cp_pbpar, 0x00000001, 0x0000000E); /* set bits */
109 /* ----------------------------------------------
110 * In/Out or per. Function 0/1
111 * PBDIR[28] = 1 [0x00000008] -> PERI1: SPIMISO
112 * PBDIR[29] = 1 [0x00000004] -> PERI1: SPIMOSI
113 * PBDIR[30] = 1 [0x00000002] -> PERI1: SPICLK
114 * PBDIR[31] = 1 [0x00000001] -> GPIO OUT: CS for PCUE/CCM-EEPROM
115 * ---------------------------------------------- */
116 setbits_be32(&cp->cp_pbdir, 0x0000000F);
118 /* ----------------------------------------------
119 * open drain or active output
120 * PBODR[28] = 1 [0x00000008] -> open drain: SPIMISO
121 * PBODR[29] = 0 [0x00000004] -> active output SPIMOSI
122 * PBODR[30] = 0 [0x00000002] -> active output: SPICLK
123 * PBODR[31] = 0 [0x00000001] -> active output: GPIO OUT: CS for PCUE/CCM
124 * ---------------------------------------------- */
126 clrsetbits_be16(&cp->cp_pbodr, 0x00000007, 0x00000008);
128 /* Initialize the parameter ram.
129 * We need to make sure many things are initialized to zero
131 out_be32(&spi->spi_rstate, 0);
132 out_be32(&spi->spi_rdp, 0);
133 out_be16(&spi->spi_rbptr, 0);
134 out_be16(&spi->spi_rbc, 0);
135 out_be32(&spi->spi_rxtmp, 0);
136 out_be32(&spi->spi_tstate, 0);
137 out_be32(&spi->spi_tdp, 0);
138 out_be16(&spi->spi_tbptr, 0);
139 out_be16(&spi->spi_tbc, 0);
140 out_be32(&spi->spi_txtmp, 0);
143 /* Set up the SPI parameters in the parameter ram */
144 out_be16(&spi->spi_rbase, CPM_SPI_BASE_RX);
145 out_be16(&spi->spi_tbase, CPM_SPI_BASE_TX);
147 /***********IMPORTANT******************/
150 * Setting transmit and receive buffer descriptor pointers
151 * initially to rbase and tbase. Only the microcode patches
152 * documentation talks about initializing this pointer. This
153 * is missing from the sample I2C driver. If you dont
154 * initialize these pointers, the kernel hangs.
156 out_be16(&spi->spi_rbptr, CPM_SPI_BASE_RX);
157 out_be16(&spi->spi_tbptr, CPM_SPI_BASE_TX);
160 /* Init SPI Tx + Rx Parameters */
161 while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG)
164 out_be16(&cp->cp_cpcr, mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) |
166 while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG)
170 /* Set SDMA configuration register */
171 out_be32(&immr->im_siu_conf.sc_sdcr, 0x0001);
174 /* Set to big endian. */
175 out_8(&spi->spi_tfcr, SMC_EB);
176 out_8(&spi->spi_rfcr, SMC_EB);
179 /* Set maximum receive size. */
180 out_be16(&spi->spi_mrblr, MAX_BUFFER);
183 /* tx and rx buffer descriptors */
184 tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
185 rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
187 clrbits_be16(&tbdf->cbd_sc, BD_SC_READY);
188 clrbits_be16(&rbdf->cbd_sc, BD_SC_EMPTY);
190 /* Set the bd's rx and tx buffer address pointers */
191 out_be32(&rbdf->cbd_bufaddr, (ulong)rxbuf);
192 out_be32(&tbdf->cbd_bufaddr, (ulong)txbuf);
195 out_8(&cp->cp_spim, 0); /* Mask all SPI events */
196 out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */
201 /* **************************************************************************
203 * Function: spi_init_r
205 * Description: Init SPI-Controller (RAM part) -
206 * The malloc engine is ready and we can move our buffers to
211 * *********************************************************************** */
212 void spi_init_r (void)
214 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
215 cpm8xx_t __iomem *cp = &immr->im_cpm;
216 spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI];
217 cbd_t __iomem *tbdf, *rbdf;
219 /* Disable relocation */
220 out_be16(&spi->spi_rpbase, 0);
222 /* tx and rx buffer descriptors */
223 tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
224 rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
226 /* Allocate memory for RX and TX buffers */
227 rxbuf = (uchar *) malloc (MAX_BUFFER);
228 txbuf = (uchar *) malloc (MAX_BUFFER);
230 out_be32(&rbdf->cbd_bufaddr, (ulong)rxbuf);
231 out_be32(&tbdf->cbd_bufaddr, (ulong)txbuf);
236 /****************************************************************************
237 * Function: spi_write
238 **************************************************************************** */
239 ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len)
243 memset(rxbuf, 0, MAX_BUFFER);
244 memset(txbuf, 0, MAX_BUFFER);
245 *txbuf = SPI_EEPROM_WREN; /* write enable */
247 memcpy(txbuf, addr, alen);
248 *txbuf = SPI_EEPROM_WRITE; /* WRITE memory array */
249 memcpy(alen + txbuf, buffer, len);
250 spi_xfer(alen + len);
251 /* ignore received data */
252 for (i = 0; i < 1000; i++) {
253 *txbuf = SPI_EEPROM_RDSR; /* read status */
256 if (!(rxbuf[1] & 1)) {
262 printf ("*** spi_write: Time out while writing!\n");
268 /****************************************************************************
270 **************************************************************************** */
271 ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len)
273 memset(rxbuf, 0, MAX_BUFFER);
274 memset(txbuf, 0, MAX_BUFFER);
275 memcpy(txbuf, addr, alen);
276 *txbuf = SPI_EEPROM_READ; /* READ memory array */
279 * There is a bug in 860T (?) that cuts the last byte of input
280 * if we're reading into DPRAM. The solution we choose here is
281 * to always read len+1 bytes (we have one extra byte at the
282 * end of the buffer).
284 spi_xfer(alen + len + 1);
285 memcpy(buffer, alen + rxbuf, len);
290 /****************************************************************************
292 **************************************************************************** */
293 ssize_t spi_xfer (size_t count)
295 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
296 cpm8xx_t __iomem *cp = &immr->im_cpm;
297 spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI];
298 cbd_t __iomem *tbdf, *rbdf;
301 /* Disable relocation */
302 out_be16(&spi->spi_rpbase, 0);
304 tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
305 rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
307 /* Set CS for device */
308 clrbits_be32(&cp->cp_pbdat, 0x0001);
310 /* Setting tx bd status and data length */
311 out_be16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_LAST | BD_SC_WRAP);
312 out_be16(&tbdf->cbd_datlen, count);
314 /* Setting rx bd status and data length */
315 out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_WRAP);
316 out_be16(&rbdf->cbd_datlen, 0); /* rx length has no significance */
318 clrsetbits_be16(&cp->cp_spmode, ~SPMODE_LOOP, SPMODE_REV | SPMODE_MSTR |
319 SPMODE_EN | SPMODE_LEN(8) | SPMODE_PM(0x8));
320 out_8(&cp->cp_spim, 0); /* Mask all SPI events */
321 out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */
323 /* start spi transfer */
324 setbits_8(&cp->cp_spcom, SPI_STR); /* Start transmit */
326 /* --------------------------------
327 * Wait for SPI transmit to get out
328 * or time out (1 second = 1000 ms)
329 * -------------------------------- */
330 for (tm=0; tm<1000; ++tm) {
331 if (in_8(&cp->cp_spie) & SPI_TXB) /* Tx Buffer Empty */
333 if ((in_be16(&tbdf->cbd_sc) & BD_SC_READY) == 0)
338 printf ("*** spi_xfer: Time out while xferring to/from SPI!\n");
341 /* Clear CS for device */
342 setbits_be32(&cp->cp_pbdat, 0x0001);
346 #endif /* CONFIG_SPI */