arch/powerpc/cpu/mpc8xx/reginfo.c

   1 /*
   2  * (C) Copyright 2000
   3  * Subodh Nijsure, SkyStream Networks, snijsure@skystream.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <mpc8xx.h>
  10 #include <asm/io.h>
  11 #include <asm/ppc.h>
  12
  13 void print_reginfo(void)
  14 {
  15         immap_t __iomem     *immap  = (immap_t __iomem *)CONFIG_SYS_IMMR;
  16         memctl8xx_t __iomem *memctl = &immap->im_memctl;
  17         sysconf8xx_t __iomem *sysconf = &immap->im_siu_conf;
  18         sit8xx_t __iomem *timers = &immap->im_sit;
  19
  20         /* Hopefully more PowerPC  knowledgable people will add code to display
  21          * other useful registers
  22          */
  23
  24         printf("\nSystem Configuration registers\n"
  25                 "\tIMMR\t0x%08X\n", get_immr());
  26
  27         printf("\tSIUMCR\t0x%08X", in_be32(&sysconf->sc_siumcr));
  28         printf("\tSYPCR\t0x%08X\n", in_be32(&sysconf->sc_sypcr));
  29
  30         printf("\tSWT\t0x%08X", in_be32(&sysconf->sc_swt));
  31         printf("\tSWSR\t0x%04X\n", in_be16(&sysconf->sc_swsr));
  32
  33         printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n",
  34                in_be32(&sysconf->sc_sipend), in_be32(&sysconf->sc_simask));
  35         printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n",
  36                in_be32(&sysconf->sc_siel), in_be32(&sysconf->sc_sivec));
  37         printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n",
  38                in_be32(&sysconf->sc_tesr), in_be32(&sysconf->sc_sdcr));
  39
  40         printf("Memory Controller Registers\n");
  41         printf("\tBR0\t0x%08X\tOR0\t0x%08X\n", in_be32(&memctl->memc_br0),
  42                in_be32(&memctl->memc_or0));
  43         printf("\tBR1\t0x%08X\tOR1\t0x%08X\n", in_be32(&memctl->memc_br1),
  44                in_be32(&memctl->memc_or1));
  45         printf("\tBR2\t0x%08X\tOR2\t0x%08X\n", in_be32(&memctl->memc_br2),
  46                in_be32(&memctl->memc_or2));
  47         printf("\tBR3\t0x%08X\tOR3\t0x%08X\n", in_be32(&memctl->memc_br3),
  48                in_be32(&memctl->memc_or3));
  49         printf("\tBR4\t0x%08X\tOR4\t0x%08X\n", in_be32(&memctl->memc_br4),
  50                in_be32(&memctl->memc_or4));
  51         printf("\tBR5\t0x%08X\tOR5\t0x%08X\n", in_be32(&memctl->memc_br5),
  52                in_be32(&memctl->memc_or5));
  53         printf("\tBR6\t0x%08X\tOR6\t0x%08X\n", in_be32(&memctl->memc_br6),
  54                in_be32(&memctl->memc_or6));
  55         printf("\tBR7\t0x%08X\tOR7\t0x%08X\n", in_be32(&memctl->memc_br7),
  56                in_be32(&memctl->memc_or7));
  57         printf("\n\tmamr\t0x%08X\tmbmr\t0x%08X\n", in_be32(&memctl->memc_mamr),
  58                in_be32(&memctl->memc_mbmr));
  59         printf("\tmstat\t0x%04X\tmptpr\t0x%04X\n", in_be16(&memctl->memc_mstat),
  60                in_be16(&memctl->memc_mptpr));
  61         printf("\tmdr\t0x%08X\n", in_be32(&memctl->memc_mdr));
  62
  63         printf("\nSystem Integration Timers\n");
  64         printf("\tTBSCR\t0x%04X\tRTCSC\t0x%04X\n",
  65                in_be16(&timers->sit_tbscr), in_be16(&timers->sit_rtcsc));
  66         printf("\tPISCR\t0x%04X\n", in_be16(&timers->sit_piscr));
  67
  68         /*
  69          * May be some CPM info here?
  70          */
  71 }