1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2000-2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 #include <mpc8xx_irq.h>
10 #include <asm/cpm_8xx.h>
11 #include <asm/processor.h>
14 /************************************************************************/
17 * CPM interrupt vector functions.
19 struct interrupt_action {
20 interrupt_handler_t *handler;
24 static struct interrupt_action cpm_vecs[CPMVEC_NR];
25 static struct interrupt_action irq_vecs[NR_IRQS];
27 static void cpm_interrupt_init(void);
28 static void cpm_interrupt(void *regs);
30 /************************************************************************/
32 void interrupt_init_cpu(unsigned *decrementer_count)
34 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
36 *decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
38 /* disable all interrupts */
39 out_be32(&immr->im_siu_conf.sc_simask, 0);
41 /* Configure CPM interrupts */
45 /************************************************************************/
48 * Handle external interrupts
50 void external_interrupt(struct pt_regs *regs)
52 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
58 * read the SIVEC register and shift the bits down
59 * to get the irq number
61 vec = in_be32(&immr->im_siu_conf.sc_sivec);
63 v_bit = 0x80000000UL >> irq;
66 * Read Interrupt Mask Register and Mask Interrupts
68 simask = in_be32(&immr->im_siu_conf.sc_simask);
69 clrbits_be32(&immr->im_siu_conf.sc_simask, 0xFFFF0000 >> irq);
71 if (!(irq & 0x1)) { /* External Interrupt ? */
75 * Read Interrupt Edge/Level Register
77 siel = in_be32(&immr->im_siu_conf.sc_siel);
79 if (siel & v_bit) { /* edge triggered interrupt ? */
81 * Rewrite SIPEND Register to clear interrupt
83 out_be32(&immr->im_siu_conf.sc_sipend, v_bit);
87 if (irq_vecs[irq].handler != NULL) {
88 irq_vecs[irq].handler(irq_vecs[irq].arg);
90 printf("\nBogus External Interrupt IRQ %d Vector %ld\n",
92 /* turn off the bogus interrupt to avoid it from now */
96 * Re-Enable old Interrupt Mask
98 out_be32(&immr->im_siu_conf.sc_simask, simask);
101 /************************************************************************/
104 * CPM interrupt handler
106 static void cpm_interrupt(void *regs)
108 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
112 * Get the vector by setting the ACK bit
113 * and then reading the register.
115 out_be16(&immr->im_cpic.cpic_civr, 1);
116 vec = in_be16(&immr->im_cpic.cpic_civr);
119 if (cpm_vecs[vec].handler != NULL) {
120 (*cpm_vecs[vec].handler) (cpm_vecs[vec].arg);
122 clrbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
123 printf("Masking bogus CPM interrupt vector 0x%x\n", vec);
126 * After servicing the interrupt,
127 * we have to remove the status indicator.
129 setbits_be32(&immr->im_cpic.cpic_cisr, 1 << vec);
133 * The CPM can generate the error interrupt when there is a race
134 * condition between generating and masking interrupts. All we have
135 * to do is ACK it and return. This is a no-op function so we don't
136 * need any special tests in the interrupt handler.
138 static void cpm_error_interrupt(void *dummy)
142 /************************************************************************/
144 * Install and free an interrupt handler
146 void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
148 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
150 if ((vec & CPMVEC_OFFSET) != 0) {
153 if (cpm_vecs[vec].handler != NULL)
154 printf("CPM interrupt 0x%x replacing 0x%x\n",
155 (uint)handler, (uint)cpm_vecs[vec].handler);
156 cpm_vecs[vec].handler = handler;
157 cpm_vecs[vec].arg = arg;
158 setbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
161 if (irq_vecs[vec].handler != NULL)
162 printf("SIU interrupt %d 0x%x replacing 0x%x\n",
163 vec, (uint)handler, (uint)cpm_vecs[vec].handler);
164 irq_vecs[vec].handler = handler;
165 irq_vecs[vec].arg = arg;
166 setbits_be32(&immr->im_siu_conf.sc_simask, 1 << (31 - vec));
170 void irq_free_handler(int vec)
172 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
174 if ((vec & CPMVEC_OFFSET) != 0) {
177 clrbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
178 cpm_vecs[vec].handler = NULL;
179 cpm_vecs[vec].arg = NULL;
182 clrbits_be32(&immr->im_siu_conf.sc_simask, 1 << (31 - vec));
183 irq_vecs[vec].handler = NULL;
184 irq_vecs[vec].arg = NULL;
188 /************************************************************************/
190 static void cpm_interrupt_init(void)
192 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
196 * Initialize the CPM interrupt controller.
199 cicr = CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1 |
200 ((CPM_INTERRUPT / 2) << 13) | CICR_HP_MASK;
202 out_be32(&immr->im_cpic.cpic_cicr, cicr);
203 out_be32(&immr->im_cpic.cpic_cimr, 0);
206 * Install the error handler.
208 irq_install_handler(CPMVEC_ERROR, cpm_error_interrupt, NULL);
210 setbits_be32(&immr->im_cpic.cpic_cicr, CICR_IEN);
213 * Install the cpm interrupt handler
215 irq_install_handler(CPM_INTERRUPT, cpm_interrupt, NULL);
218 /************************************************************************/
221 * timer_interrupt - gets called when the decrementer overflows,
222 * with interrupts disabled.
223 * Trivial implementation - no need to be really accurate.
225 void timer_interrupt_cpu(struct pt_regs *regs)
227 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
229 /* Reset Timer Expired and Timers Interrupt Status */
230 out_be32(&immr->im_clkrstk.cark_plprcrk, KAPWR_KEY);
233 Clear TEXPS (and TMIST on older chips). SPLSS (on older
234 chips) is cleared too.
236 Bitwise OR is a read-modify-write operation so ALL bits
237 which are cleared by writing `1' would be cleared by
240 immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS;
242 The same can be achieved by simple writing of the PLPRCR
243 to itself. If a bit value should be preserved, read the
244 register, ZERO the bit and write, not OR, the result back.
246 setbits_be32(&immr->im_clkrst.car_plprcr, 0);
249 /************************************************************************/