2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <mpc8xx_irq.h>
11 #include <asm/processor.h>
15 /************************************************************************/
18 * CPM interrupt vector functions.
20 struct interrupt_action {
21 interrupt_handler_t *handler;
25 static struct interrupt_action cpm_vecs[CPMVEC_NR];
26 static struct interrupt_action irq_vecs[NR_IRQS];
28 static void cpm_interrupt_init (void);
29 static void cpm_interrupt (void *regs);
31 /************************************************************************/
33 int interrupt_init_cpu (unsigned *decrementer_count)
35 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
37 *decrementer_count = get_tbclk () / CONFIG_SYS_HZ;
39 /* disable all interrupts */
40 out_be32(&immr->im_siu_conf.sc_simask, 0);
42 /* Configure CPM interrupts */
43 cpm_interrupt_init ();
48 /************************************************************************/
51 * Handle external interrupts
53 void external_interrupt (struct pt_regs *regs)
55 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
61 * read the SIVEC register and shift the bits down
62 * to get the irq number
64 vec = in_be32(&immr->im_siu_conf.sc_sivec);
66 v_bit = 0x80000000UL >> irq;
69 * Read Interrupt Mask Register and Mask Interrupts
71 simask = in_be32(&immr->im_siu_conf.sc_simask);
72 clrbits_be32(&immr->im_siu_conf.sc_simask, 0xFFFF0000 >> irq);
74 if (!(irq & 0x1)) { /* External Interrupt ? */
78 * Read Interrupt Edge/Level Register
80 siel = in_be32(&immr->im_siu_conf.sc_siel);
82 if (siel & v_bit) { /* edge triggered interrupt ? */
84 * Rewrite SIPEND Register to clear interrupt
86 out_be32(&immr->im_siu_conf.sc_sipend, v_bit);
90 if (irq_vecs[irq].handler != NULL) {
91 irq_vecs[irq].handler (irq_vecs[irq].arg);
93 printf ("\nBogus External Interrupt IRQ %d Vector %ld\n",
95 /* turn off the bogus interrupt to avoid it from now */
99 * Re-Enable old Interrupt Mask
101 out_be32(&immr->im_siu_conf.sc_simask, simask);
104 /************************************************************************/
107 * CPM interrupt handler
109 static void cpm_interrupt (void *regs)
111 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
115 * Get the vector by setting the ACK bit
116 * and then reading the register.
118 out_be16(&immr->im_cpic.cpic_civr, 1);
119 vec = in_be16(&immr->im_cpic.cpic_civr);
122 if (cpm_vecs[vec].handler != NULL) {
123 (*cpm_vecs[vec].handler) (cpm_vecs[vec].arg);
125 clrbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
126 printf ("Masking bogus CPM interrupt vector 0x%x\n", vec);
129 * After servicing the interrupt,
130 * we have to remove the status indicator.
132 setbits_be32(&immr->im_cpic.cpic_cisr, 1 << vec);
136 * The CPM can generate the error interrupt when there is a race
137 * condition between generating and masking interrupts. All we have
138 * to do is ACK it and return. This is a no-op function so we don't
139 * need any special tests in the interrupt handler.
141 static void cpm_error_interrupt (void *dummy)
145 /************************************************************************/
147 * Install and free an interrupt handler
149 void irq_install_handler (int vec, interrupt_handler_t * handler,
152 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
154 if ((vec & CPMVEC_OFFSET) != 0) {
157 if (cpm_vecs[vec].handler != NULL) {
158 printf ("CPM interrupt 0x%x replacing 0x%x\n",
160 (uint) cpm_vecs[vec].handler);
162 cpm_vecs[vec].handler = handler;
163 cpm_vecs[vec].arg = arg;
164 setbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
167 if (irq_vecs[vec].handler != NULL) {
168 printf ("SIU interrupt %d 0x%x replacing 0x%x\n",
171 (uint) cpm_vecs[vec].handler);
173 irq_vecs[vec].handler = handler;
174 irq_vecs[vec].arg = arg;
175 setbits_be32(&immr->im_siu_conf.sc_simask, 1 << (31 - vec));
179 void irq_free_handler (int vec)
181 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
183 if ((vec & CPMVEC_OFFSET) != 0) {
186 clrbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
187 cpm_vecs[vec].handler = NULL;
188 cpm_vecs[vec].arg = NULL;
191 clrbits_be32(&immr->im_siu_conf.sc_simask, 1 << (31 - vec));
192 irq_vecs[vec].handler = NULL;
193 irq_vecs[vec].arg = NULL;
197 /************************************************************************/
199 static void cpm_interrupt_init (void)
201 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
205 * Initialize the CPM interrupt controller.
208 cicr = CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1 |
209 ((CPM_INTERRUPT / 2) << 13) | CICR_HP_MASK;
211 out_be32(&immr->im_cpic.cpic_cicr, cicr);
212 out_be32(&immr->im_cpic.cpic_cimr, 0);
215 * Install the error handler.
217 irq_install_handler (CPMVEC_ERROR, cpm_error_interrupt, NULL);
219 setbits_be32(&immr->im_cpic.cpic_cicr, CICR_IEN);
222 * Install the cpm interrupt handler
224 irq_install_handler (CPM_INTERRUPT, cpm_interrupt, NULL);
227 /************************************************************************/
230 * timer_interrupt - gets called when the decrementer overflows,
231 * with interrupts disabled.
232 * Trivial implementation - no need to be really accurate.
234 void timer_interrupt_cpu (struct pt_regs *regs)
236 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
238 /* Reset Timer Expired and Timers Interrupt Status */
239 out_be32(&immr->im_clkrstk.cark_plprcrk, KAPWR_KEY);
242 Clear TEXPS (and TMIST on older chips). SPLSS (on older
243 chips) is cleared too.
245 Bitwise OR is a read-modify-write operation so ALL bits
246 which are cleared by writing `1' would be cleared by
249 immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS;
251 The same can be achieved by simple writing of the PLPRCR
252 to itself. If a bit value should be preserved, read the
253 register, ZERO the bit and write, not OR, the result back.
255 setbits_be32(&immr->im_clkrst.car_plprcr, 0);
258 /************************************************************************/